A High Frequency Active Voltage Doubler in Standard CMOS Using Offset-Controlled Comparators for Inductive Power Transmission

Abstract

In this paper, we present a fully integrated active voltage doubler in CMOS technology using offset-controlled high speed comparators for extending the range of inductive power transmission to implantable microelectronic devices (IMD) and radio-frequency identification (RFID) tags. This active voltage doubler provides considerably higher power conversion efficiency (PCE) and lower dropout voltage compared to its passive counterpart and requires lower input voltage than active rectifiers, leading to reliable and efficient operation with weakly coupled inductive links. The offset-controlled functions in the comparators compensate for turn-on and turn-off delays to not only maximize the forward charging current to the load but also minimize the back current, optimizing PCE in the high frequency (HF) band. We fabricated the active voltage doubler in a 0.5-μm 3M2P std. CMOS process, occupying 0.144 mm² of chip area. With 1.46 V peak AC input at 13.56 MHz, the active voltage doubler provides 2.4 V DC output across a 1 kΩ load, achieving the highest PCE = 79% ever reported at this frequency. In addition, the built-in start-up circuit ensures a reliable operation at lower voltages.

I. Introduction

IMPLANTABLE microelectronic devices (IMD) have already been used successfully in the form of cochlear implants to substitute a sensory modality (hearing) that might be lost due to diseases or injuries [1]. More recent IMD applications demand higher performance and more power efficiency to enable very sophisticated treatment paradigms, such as retinal implants for the blind or bidirectional cortical brain-computer-interfaces (BCI) with sensory feedback for amputees or those suffering from severe paralysis [2]–[4]. These IMDs require more power to handle more functions on a larger scale, particularly when they need stimulation through a large number of electrodes at high rates, which power level is less dependent on the circuit efficiency [5]. Therefore, the new IMD power consumption is going to be orders of magnitude higher than more traditional IMDs, e.g., pacemakers [6], and supplying them with primary batteries will not be an option. Inductive power transmission across the skin is, however, a viable solution to overcome size, cost, and longevity while providing sufficient power to such IMDs [5], [7]–[9]. Considering that the temperature at the outer surface of the IMD should not increase more than 2°C for the surrounding tissue to survive [10], it is of utmost importance for the inductive link and the IMD power management circuitry to maintain very high power transfer efficiency. There are also other applications such as inductively powered wireless sensors, radio frequency identification (RFID), and near-field communication (NFC), in which the size and cost of neither primary nor secondary (i.e., rechargeable) batteries are justified, while high power efficiency and robustness even through weak inductive links are highly desired [11], [12].

Fig. 1 shows the block diagram of an inductively-powered IMD with emphasis on the inductive power transmission that consists of three main components: power transmitter (Tx), inductive link, and IMD (Rx). On the Tx side, the primary coil, L₁, is driven by a power amplifier (PA) at the carrier frequency, f_c. This signal induces power in the secondary coil, L₂, and the active voltage doubler converts the AC voltage in L₂C₂ tank to a DC voltage (V_OUT) at higher levels than the peak input voltage.

Fig. 1.

Block diagram of an inductively-powered device (e.g., an IMD) with emphasis on the inductive power transmission through the proposed active voltage doubler.

The size of L₂ is significantly constrained when it is meant to be implantable in the human body or embedded in a small RFID tag, resulting in small L₂ value and low V_IN [13]–[15]. There are also IMDs under development, in which the secondary coil has to be embedded in the stimulator package (e.g., to be injectable) or directly implemented on the backside of the microelectrode array to facilitate the system microassembly and packaging by eliminating the flex cable that would otherwise be needed to place L₂ under the skin [16], [17]. In such cases, the distance between L₁ and L₂ can be considerably larger than the size of L₂, significantly limiting V_IN. This condition renders even the most efficient rectifiers either ineffective or highly inefficient. Thus, similar to far field RFID tags in the UHF band, in order to generate the desired V_OUT from a small V_IN while maintaining high efficiency, a viable solution could be using voltage doublers which can operate at lower V_IN,peak while providing sufficient V_OUT. This can also increase the read range in the RFID tags that operate in the HF band.

Both rectifiers and voltage doublers have been widely used for inductively-powered applications. Passive rectifiers and voltage doublers using diode-connected transistors suffer from large forward voltage drops and power losses because of their threshold voltages [9], [18]–[22]. A bridge rectifier using Schottky diodes has low dropout voltage [23], but it has high leakage current and it is not available in a standard CMOS process without extra fabrication steps. In addition, its reverse breakdown voltage may not be high enough for stimulation applications. Several V_Th compensation techniques have been proposed to reduce the effective V_Th [24]–[29]. However, they still need to deal with several issues such as sensitivity to process variations, leakage, and back currents.

Synchronous active rectifiers have achieved high power conversion efficiency (PCE) because their pass transistors operate as switches in deep triode region with low dropout voltages [30]–[44]. However, their peak input voltages, which may be significantly limited by weakly coupled inductive links, need to be always higher than the desired output voltages, resulting in lower operating range or higher voltages on the Tx side. In order to address such limitations, comparator-based active voltage doublers have been recently proposed [45], [46]. However, these topologies only operate at low frequencies (< 1 kHz) in applications such as energy scavenging from vibrations using piezoelectric transducers. Improved voltage doublers are required for IMD and RFID applications with inductive links that operate within the HF band, such as 13.56 MHz, in the Industrial, Scientific, and Medical (ISM) band.

In this paper, we propose a fully-integrated power-efficient active voltage doubler employing high speed comparators for inductively-powered applications such as IMD, RFID, and NFC. Comparators are equipped with offset control functions to compensate for both turn-on and turn-off delays. The active voltage doubler achieves high PCE comparable to the active rectifiers while generating the desired DC output voltage with much lower AC inputs than either active rectifiers or passive voltage doublers. Section II describes the concept, operating principle, and PCE analysis of the active voltage doubler. Section III presents circuit details and design considerations including the effects of the proposed offset-control functions in high speed comparators. Simulation and measurement results are in Section IV, followed by conclusions in Section V.

II. Active Voltage Doubler Architecture

A. Operating Principle of the Voltage Doubler

Fig. 2 shows the topology of the conventional passive voltage doubler using either diodes or diode-connected transistors. It consists of one capacitor, C_IN, and two diodes, D_N and D_P, with forward dropout voltages of V_DN and V_DP, respectively. Rectified output voltage, V_OUT, is low pass filtered by C_L, and supplies the load resistor, R_L. The sinusoidal input voltage, V_IN, generated across the secondary resonance circuit, L₂C₂, has a peak amplitude of V_IN,peak, which depends on the inductive link parameters and V_PA at the output of the power amplifier (PA), shown in Fig. 1 [14].

Fig. 2.

Schematic diagram of the passive voltage doubler using diodes or diode-connected transistors.

When V_IN goes below −V_DN, V_VD is connected V_SS to through D_N, and C_IN is charged to V_IN,peak − V_DN, with V_VD as the positive node. When V_IN increases above −V_IN,peak, D_N turns off again and the isolated V_VD increases by following V_IN,peak − V_DN + V_IN. When V_VD > V_OUT + V_DP, D_P turns on and current flows from V_IN to V_OUT to charge the R_LC_L load. In this step, the charge stored in C_IN decreases by the amount of charge delivered to the load, but C_IN is charged again to V_IN,peak − V_DN in the next cycle. Due to the dropout voltage across D_P, V_OUT can reach a maximum voltage of 2V_IN,peak − V_DN − V_DP. The total dropout voltage of the voltage doubler, V_Drop, can be calculated from

$$V_{\mathit{Drop}}=2V_{IN,\mathit{peak}}-V_{\mathit{OUT}}=V_{DN}+V_{DP}.$$ (1)

This equation shows that the diode dropout voltages, V_DN and V_DP, directly affect the voltage doubler output voltage and consequently its PCE. Thus, substituting them with fast MOS switches with low on-resistance and leakage would be an effective way of reducing V_Drop and improving the PCE.

B. Implementation of the Active Voltage Doubler

Fig. 3 shows a simplified schematic diagram of the proposed active voltage doubler, in which two pass transistor switches, N₁ and P₁, are driven by high-speed comparators, CMP_N and CMP_P, respectively. When V_VD < V_SS, CMP_N output goes high, N₁ turns on with a low dropout voltage, V_DS(N1), and C_IN is charged to V_IN,peak − V_DS(N1) in the shown polarity. Similarly, when V_VD < V_OUT, CMP_P output goes low, P₁ turns on with a low dropout voltage, V_SD(P1), and current flows through P₁ to charge R_LC_L in the shown polarity. Therefore, after a few cycles, V_OUT is charged up to 2V_IN,peak − V_DS(N1) − V_SD(P1), and the total dropout voltage, V_Drop = V_DS(N1) + V_SD(P1), which results from the instantaneous input current flowing through the on-resistance of N₁ and P₁, will be much smaller than that of the passive voltage doubler in Fig. 2 (V_GS(N) + V_SG(P)).

Fig. 3.

Schematic diagram of the proposed active voltage doubler employing high speed offset-controlled comparators, CMP_N and CMP_P, to drive N₁ and P₁ pass transistors, respectively, and achieve higher PCE.

To drive N₁ and P₁ at high frequencies in the order of 13.56 MHz, comparators are equipped with internal offset-control functions that are externally adjustable (CTL0:3) to reduce the effects of the comparators' delay. Also, the separated N-well body terminal of P₁ needs to be connected to the highest potential on the chip to prevent latch-up and substrate leakage problems. Therefore, in Fig. 3 we have adopted the dynamic body biasing technique from [18] with auxiliary transistors, P₃ and P₄, automatically connecting V_BODY to the highest potential between V_VD and V_OUT.

Since the comparators are supplied from V_OUT, which is initially at 0 V, it is necessary for the active voltage doubler to have startup capability. The startup block in Fig. 3, which has been described in Section III.C, generates a complementary pair of startup enable signals, SU and SU_B, depending on the V_OUT level to control the startup switches, N₂ and P₂, as well as the comparators. When V_OUT is too low to operate the comparators, the startup circuit sets SU = high and SU_B = low, which turn on N₂ and P₂, respectively, while disabling the comparators. In this condition, both N₁ and P₁ are diode-connected to form a passive voltage doubler, which starts charging V_OUT regardless of the comparators' status. When V_OUT exceeds a certain level that is sufficient to operate the comparators, SU and SU_B toggle and turn N₂ and P₂ off, while enabling the comparators to normally run the active voltage doubler.

C. PCE Analysis and Optimization

The PCE of the active voltage doubler can be expressed as

$$\text{PCE}=\frac{P_{\mathit{OUT}}}{P_{IN}}=\frac{P_{\mathit{Load}}}{P_{\mathit{Load}}+P_{\mathit{CMP}}+P_{Tr,sw}+P_{Tr,\mathit{Ron}}}$$ (2)

where P_Load is the power delivered to the load and P_CMP is the internal power consumption of comparators excluding the power needed to drive the gates of P₁ and N₁. P_Tr.sw and P_Tr.Ron are the power losses in the pass transistors due to gate switching and dissipation in R_on, respectively. The sizing of P₁ and N₁ plays an important role in the PCE optimization since P_Tr.sw and P_Tr.Ron are affected by W and L of each pass transistor. Some of the terms in (2) can be approximated by

$$P_{\mathit{Load}}=\frac{V_{\mathit{OUT}}^2}{R_L}$$ (3)

$$P_{Tr,sw}\approx W_p{C}_{gp}{V}_{\mathit{OUT}}^2{f}_c+W_n{C}_{gn}{V}_{\mathit{OUT}}^2{f}_c$$ (4)

$$\begin{array}{cc}\hfill P_{Tr,\mathit{Ron}}& \approx I_p^2{R}_{\mathit{onp}}D+I_n^2{R}_{\mathit{onn}}D\hfill \\ \hfill & =\frac{1}{D}{(I_{\mathit{Load}}+I_{\mathit{CMP}}+I_{Tr,sw})}^2(R_{\mathit{onp}}+R_{\mathit{onn}})\hfill \\ \hfill & =\frac{V_{\mathit{OUT}}^2}{D}{\left(\frac{1}{R_L}+\frac{P_{\mathit{CMP}}+P_{Tr,sw}}{V_{\mathit{OUT}}^2}\right)}^2(R_{\mathit{onp}}+R_{\mathit{onn}})\hfill \end{array}$$ (5)

where W_p and W_n are the widths of P₁ and N₁, and C_gp and C_gn are the gate capacitance per unit width of P₁ and N₁, respectively. F_c = 13.56 MHz is the carrier frequency, and D is the operating duty cycle (see Appendix). I_p and I_n are currents flowing through P₁ and N₁, respectively, and they are assumed to be equal. We also found P_CMP at each V_OUT from simulations (0.1 ~ 0.8 mW), and used it in the PCE analysis. L_p and L_n are 0.6 μm, the minimum length in this process.

Even though larger widths of pass transistors decrease P_Tr.ron, they increase switching losses, P_Tr.sw, due to larger parasitic gate capacitances. Hence, each pass transistor has an optimal size for minimum power dissipation depending on several parameters, such as V_OUT, R_L, and f_c. In the Appendix, we have derived detailed equations for the PCE and V_Drop while calculating optimal sizing of pass transistors for our target specifications.

III. Circuit Details and Design Considerations

A. Offset-Controlled High Speed Comparator

CMP_N and CMP_P need to drive large gate capacitances of N₁ and P₁ at high frequencies, respectively. Thus, key design parameters are drive capability and short delay. Comparator delay can reduce the PCE by either decreasing the input power that could otherwise be delivered to the load or allowing instantaneous back currents that flow from C_L back to L₂C₂ tank when V_IN < V_OUT. To reduce such delays, we have designed high-speed comparators with adjustable internal offsets, which basic concept was introduced in [44]. These built-in offset control functions help comparators turn their pass transistors on and off at proper times, leading to higher PCE.

Fig. 4 shows the schematic diagram of two symmetrical high-speed comparators, CMP_N in Fig. 4(a) and CMP_P in Fig. 4(b), each of which is equipped with three built-in offset-control functions. In Fig. 4(a), P₇-P₈, N₃-N₄, and P₁₅-N₇ form a common-gate comparator, which input terminals at the sources of N₃ and N₄ are connected to V_SS and V_VD, respectively. P₆ and R₁ form a biasing branch, which is mirrored on to P₇ and P₈. Thus, the comparator requires a minimum supply voltage of V_TH(P6) in order to start its operation. Since the gate of the diode-connected N₃ is coupled with N₄, currents flowing through N₃ and N₄ depend on their source voltages, V_SS and V_VD, respectively. When V_VD < V_SS, the current flowing through N₄ tends to be larger than that of N₃, P₇, and P₈. Hence, V₁, the input of the P₁₅-N₇ inverter rapidly drops, leading to a high comparator output voltage, V_CN, which turns N₁ on.

Fig. 4.

Schematic diagram showing three offset-control functions built-in our high speed comparators, (a) CMP_N and (b) CMP_P : Offset-1 for turn-on delay, Offset-2 for turn-off delay, and Offset-3 for reliable turn-off operation.

Even though common-gate comparators are considered high speed due to their low input impedance and simple structure, their speed of operation in our 0.5-μm process was not fast enough to drive large capacitive loads (N₁ and P₁) at 13.56 MHz. Therefore, we added Offset-1_N and Offset-2_N-inside CMP_N (and their duals in CMP_P) in order to compensate for the turn-on and turn-off delays, respectively. Offset-1_N block is implemented using N₅ current source, controlled by N₆ switch, which can pull additional offset current from CMP_N output branch, leading V₁ to start dropping earlier when this offset mechanism is activated by V_OS1N = high. Constant Offset-2_N has been implemented using the size mismatch between P₈ and P₇. The larger W/L ratio of P₈ pushes additional offset current into the comparator output branch to increase V1 early.

The offset control signal, V_OS1N, is provided by an offset control block that consists of the current-starved inverter, P₁₆-P₁₇-N₈, and other logic gates in Fig. 4(a). When V_VD > V_SS, V_CN = low, and V_OS1N = high. Thus, N₆ turns N₅ on to pull offset current in parallel with N₄ at a level that is higher than the additional current that is pushed in P₈ by Offset-2_N. Therefore, V_VD starts to increase earlier to turn on N₁a bit before V_VD falls below V_SS to compensate for the comparator turn-on delay. Once V_CN = high, the Offset-1_N block turns off, and the offset current pushing through P₈ becomes dominant. As a result, V_CN starts to decrease earlier to turn N₁ off a bit before V_VD exceeds V_SS to compensate for the comparator turn-on delay. In this case, V_OS1N goes high after the delay generated by the current- starved inverter, which should be shorter than one carrier cycle period. Since switches to high when V_VD is much higher than V_SS, it does not cause any fluctuation or instability issues through its feedback loop.

Sudden variations in V_VD may occur with rapid changes in the forward current due to interconnect parasitic inductance between L₂C₂ tank and the voltage doubler. These variations may disrupt proper switching of the pass transistors and should be avoided. To protect the comparators against such effects, we have added a 3rd offset branch, Offset-3_N, which consists of P₉ current source, controlled by P₁₃ switch. When V_CN goes low, it takes a while before the current-starved inverter output goes high. During this time, V_OS3N = low, activating the Offset-3_N branch to inject additional current into V₁ node and prevent V_CN from undesired changes due to V_VD variations. This will keep N₁ off until the next carrier cycle.

Fig. 5 shows the timing relationship between the input, output, and comparator voltages of the voltage doubler and the offset control signals of each comparator. All transitions of the offset control signals occur fast with negligible rising and falling times even in the gray area in Fig. 5. When the current-starved inverter delay is changed, the transitions of V_OS1,3N and V_OS1,3P may start earlier or later, but their rising and falling times still remain very small. V₁ and V₂ in Fig. 4 also have small rising and falling times. Based on simulation results, V₁ starts to drop ~ 2.5 ns earlier before V_VD < V_SS (due to Offset-1_N) and starts to increase ~ 4 ns earlier before V_VD > V_SS (due to Offset-2_N), expediting V_CN transitions.

Fig. 5.

Timing diagram showing the relationship between the operating voltages of the active voltage doubler and the offset control signals of each comparator.

It should be noted that the current-starved inverter delay does not need to be accurate, and its changes due to process variations can be tolerated as long as the delay time is terminated before the next transition time. For example, V_OS1N goes low when V_VD < V_SS, and it should go back high again sometime after V_VD > V_SS and before V_VD goes below V_SS again in the next cycle. Therefore, the low-to-high transition of V_OS1N can occur anytime during V_VD > V_SS. When designing comparators for this active voltage doubler, the current-starved inverter delay should be set first, and then Offset-1, -2, and -3 should to be tuned in this order by adjusting the sizes of their current source transistors because modifying each parameter can affect the timing and values of the following parameters.

In addition, we have added 4-bit off-chip digital control signals, two for each comparator, CTL0:1 (CMP_N) and CTL2:3 (CMP_P), which should be connected to either V_OUT (high) or V_SS (low), to adjust the switching times of the voltage doubler against process variations before the chip is used. For example, when CTL0 = low, the reduced current in P₈ drives node V₁ more weakly, delaying V_CN decrement and the onset of turning N₁ off. On the contrary, when CTL1 = low, P₁₀ increases the size mismatch in the Offset-2_N, V_CN increases more rapidly, and N₁ turns off earlier. Moreover, startup control switches, P₁₂ and N₁₆, are added in CMP_N and CMP_P, respectively, for a reliable startup operation as a passive voltage doubler. These switches turn on during the initial startup period and ensure that V_CN and V_CP are connected to V_SS and V_OUT, respectively.

B. PCE Optimization With Offset-Control Functions

To further clarify the effects of offset-control functions on the PCE, in Fig. 6(a) and (b) we have compared simulation results that show the voltage doubler input/output voltages (V_VD and V_OUT), comparator output voltages (V_CN and V_CP), and input power waveforms with the offsets disabled and enabled, respectively. In these simulations, we applied an AC voltage of V_IN,peak = 2 V at f_c = 13.56 MHz to the input and connected R_LC_L = 1 kΩ ∥ 2 nF to the output of the active voltage doubler. Fig. 6(a) shows that without offset-control functions, because of the comparator turn-on delays, V_CN and V_CP turn on N₁ and P₁ too late, respectively. This results in power conduction delays through the pass transistors, from L₂C₂ tank to the load, when V_VD < V_SS or V_VD > V_OUT. Moreover, comparator turn-off delays result in V_CN and V_CP turning off N₁ and P₁ too late, inducing back currents flowing from C_IN to V_SS and from the output load to the L₂C₂ tank, respectively. Both of these effects significantly decrease V_OUT (= 2.4 V) and PCE (= 28%).

Fig. 6.

Simulation results of the active voltage doubler showing waveforms of the input/output voltages and input power with V_IN,peak = 2 V, R_LC_L = 1 kΩ ∥ 2 nF, C_IN = 2 nF, and f_c = 13.56 MHz. (a) Without any offset-control functions. (b) With all three offset-control functions in the nominal and four process corner conditions.

Fig. 6(b) shows that the abovementioned conduction delays and back currents can be significantly reduced using offset-control functions utilized in Fig. 4 comparators. Offset-1 and offset-2 functions compensate for the turn-on and turn-off delays, respectively, such that V_CN and V_CP can turn on/off their pass transistors at the right time, leading to the highest possible PCE. Thanks to these offset-control functions, the active voltage doubler can achieve much higher V_OUT (= 3.43 V) and PCE (= 80%) with the same V_IN,peak and loading. Offset-3 function forces V_CN and V_CP to stay at V_SS and V_OUT, respectively, after their conduction periods in order to provide reliable pass transistor turn-off against spurious V_VD variations (not shown in these simulations).

C. Self-Startup Capability

The active voltage doubler is cable of starting up before its supply rail, V_OUT, is charged up to the level that is needed for the comparators to operate. The startup circuit in Fig. 7 reconfigures the doubler circuit as a diode-connected passive voltage doubler by generating SU and SU_B signals based on V_OUT. When V_OUT = 0 V, comparator outputs, V_CN and V_CP in Fig. 3, are also at 0 V. In this condition, P₁ and N₁ are diode-connected and conduct when V_VD > V_Th(P1) and V_VD < −V_Th(N1), respectively, and V_OUT starts to charge up. In Fig. 7, when V_OUT < V_Th(N22) + V_Th(P24), P₂₄ stays off and V₃ remains at 0 V through R₄. SU and SU_B follow V_OUT and V_SS and result in N₁ and P₁ to stay diode-connected. During the same period, P₁₂ and N₁₆ in Fig. 4(a) and (b) force V_CN and V_CP to be low and high, respectively, further supporting N₁ and P₁ to be diode- connected. When V_OUT > V_Th(N22) + V_Th(P24), N₂₂ turns on creating sufficient voltage across R₃ to turn on P₂₄ and pull V₃ up. This, SU and SU_B become V_SS and V_OUT, respectively, turning N₂ and P₂ off, releasing the comparator outputs, and allowing N₁ and P₁ to operate as switches. Both R₃ and R₄ have 1 MΩ values to reduce static power consumption.

Fig. 7.

Schematic diagram of the startup circuit, which generates the startup enable signals, SU and SU_B.

Fig. 8 shows the simulated waveforms for the self-startup process of the active voltage doubler, which guarantees that V_OUT is charged up to about 1.4 V before resuming its normal operation. Since sub-threshold operation of transistors also conducts a small amount of currents, the startup switching voltage may practically be less than the theoretical limit of V_Th(N22) + V_Th(P24).

Fig. 8.

Simulation results showing self-startup capability of the active voltage doubler (V_IN,peak = 1.5 V, V_OUT = 2.4 V, R_L = 1 kΩ, C_IN = C_L = 1 nF, and f_c = 13.56 MHz).

IV. Simulation and Measurement Results

A. Chip Micrograph and Measured Waveforms

The active voltage doubler was fabricated in the ON Semiconductor 0.5-μm 3M2P standard CMOS process for its relatively high voltage handling capability. Fig. 9 shows the chip micrograph of the active voltage doubler, which includes comparators (CMP_N and CMP_P), pass transistors (N₁ and P₁), control switches (N₂ and P_2–4), and the startup circuit (SU). The active voltage doubler occupies 0.144 mm² of silicon area with W_p/L_p = 2100 μm/0.6 μm and W_n/L_n = 1200 μm/0.6 μm. In our test setup, a class-C power amplifier drives the inductive link, which specifications are shown in Table II, to provide the active voltage doubler with 13.56 MHz sinusoidal input.

Fig. 9.

Fabricated chip micrograph and floor plan of the active voltage doubler in ON-Semi 0.5-μm Std. CMOS process, occupying an area of 0.144 mm².

TABLE II.

Additional Active Voltage Doubler Specifications

VTh(N) / VTh(P)	0.75 V / 0.9 V
Nominal output power	4 ~ 20 mW
Input capacitor (CIN) / Load capacitor (CL)	1 μF / 1 μF
Output ripple (RL = 1 kΩ)	22 mVpp
Comparator power consumption	0.1 ~ 0.8 mW*
Primary coil diameter / Inductance (L1)	16.8 cm / 0.88 μH
Secondary coil diameter / Inductance (L2)	3.0 cm / 0.41 μH
Pass transistor P1 size (Wp/Lp)	2100 μm / 0.6 μm
Pass transistor N1 size (Wn / Ln)	1200 μm / 0.6 μm
Total area on chip	0.144 mm2

^*From simulation

Fig. 10 shows the measured input and output waveforms of the active voltage doubler under two conditions when (V_IN,peak, V_OUT) = (1.46 V, 2.4 V) and (2 V, 3.2 V). Directly probing the comparator outputs induces extra loading, which results in undesired additional delays. Hence, we inferred the underlying events in the circuit by inspecting V_IN and V_VD = V_IN + V_Cin. In Fig. 3 once V_VD exceeds V_OUT, P₁ turns on, and a large current flows from the L₂C₂ tank to charge R_LC_L load. This forward current flow creates a voltage drop across the parasitic coil resistance and the interconnect inductance, resulting in a small dip in V_VD. While P₁ is on, V_VD = V_OUT + I_pR_op, which is fairly constant due to large C_L and L₂ that keep V_OUT and I_P constant, respectively. When P₁ turns off, the charging current instantaneously stops leading to a small bump in V_VD waveform following which V_VD returns to its normal sinusoidal shape. Therefore, P₁ and N₁ switching times can be estimated from V_VD variations, as shown in Fig. 10. We considered the peak voltages of V_IN and V_VD when P₁ and N₁ just turned on or off in order to measure V_IN·pp (= 2V_IN,peak) and V_VD,peak, respectively. In these measurements, R_L = 1 kΩ, C_IN = 1 μF, and f_c = 13.56 MHz.

Fig. 10.

Measured waveforms of key nodes in the active voltage doubler, showing V_IN, V_VD, V_OUT, and V_SS for (V_IN,peakV_OUT = (1.46 V, 2.4 V) and (2 V, 3.2 V) when R_L = 1 kΩ, C_IN = C_L = 1 μF, and f_c = 13.56 MHz.

B. PCE and Dropout Voltage Measurements

To consider key factors that affect the active voltage doubler performance, we measured the PCE and V_Drop while sweeping 1) V_OUT, 2) R_L, and 3) f_c. Each panel in Figs. 11 – 13 shows the calculated, simulated, and measured (in two conditions) values of the PCE and V_Drop to verify the accuracy of our measurements and circuit models, while providing insight for improvements. Calculated PCE and V_Drop have been derived from (1) to (5) and the active voltage doubler model in the Appendix, where the switching times are assumed to be ideal.

Fig. 11.

Measured (a) PCE and (b) V_Drop versus V_OUT with R_L = 0.5 and 1 kΩ, C_IN = C_L = 1 μF, and f_c = 13.56 MHz.

Simulations are post-layout and include estimations of parasitic inductances. To measure the input current, we connected a small current-sense resistor, R_sense = 10 Ω, in series with the voltage doubler input and differentially measured the voltage across it. P_IN was then calculated offline by integrating the instantaneous product of the input current and voltage samples. V_OUT was also measured to calculate ${\mathrm{P}}_{\mathit{Load}}=V_{\mathit{OUT}}^2∕R_L$. We also considered V_Drop = V_IN,pp − V_OUT.

Fig. 11 shows the measured, simulated, and calculated PCE and V_Drop versus V_OUT for R_L = 0.5 kΩ and 1 kΩ, C_IN = C_L = 1 μF, and f_c = 13.56 MHz. In our measurements, the highest PCE was 79% achieved at V_OUT = 2.4 V, which was the onset of circuit operation with 1 kΩ loading. Unlike rectifiers in which the dropout voltage stays more or less constant with the PCE generally improving with higher V_OUT (see [44]), we observed increments in V_Drop and reductions in the PCE with increased V_OUT, which is evident in Fig. 11. These are some of the possible reasons behind this observation: First, increasing V_OUT with constant R_L requires higher input current, resulting in higher power loss (P_Tr,Rom) in the pass transistors. The power dissipation of comparators (P_CMP) and gate switching (P_Tr,sw) also increase as the comparator supply voltage, V_OUT, increases. Second, it turned out that the 2-bit offset control that we have included in each comparator was only sufficient to adjust the switching times around V_OUT = 2 ~ 2.8 V. Therefore, the voltage doubler operation was not optimized for V_OUT > 2.8 V, resulting in both measured and simulated PCEs in Fig. 11(a) to degrade at higher V_OUT. It can be observed in Fig. 10 that P₁ and N₁ turn off too early when V_OUT = 3.2 V, limiting the input power delivered to the load and decreasing the PCE. Third, increasing V_OUT resulted in higher peaks on V_IN and V_VD, which were also noticeable in Fig. 10, because of larger input current variations and more prominent effect of parasitic inductance. When V_VD > V_OUT + V_Th(P1), P₁ is forced to conduct as a diode-connected transistor even after CMP_P tries to turn it off (due to suboptimal timing). This forced conduction in saturation region results in more power loss in P₁, and consequently lowers the PCE. Similarly, if V_VD < V_SS − V_{PN − junction}, it results in substrate leakage in N₁ because all NMOS body terminals should be connected to V_SS in this standard CMOS process. Therefore, some portion of the input current can flow through the parasitic PN junction instead of the N₁ switch, leading to additional power loss.

Calculated results in Fig. 11(a) and (b) show considerably higher PCE (86%) and lower V_Drop (0.27 V) compared to both simulated and measured results. Because in the theoretical circuit model we have assumed that the comparators turn the pass transistors on/off sharply with ideal timing regardless of variations in V_OUT, R_L, and f_c to achieve the maximum possible PCE, while the switching times in simulations and measurements are optimized for a certain operating condition, V_OUT = 2.4 V, R_L = 1 kΩ, and f_c = 13.56 MHz.

Fig. 12 shows the measured, simulated, and calculated PCE and V_Drop versus R_L. In Fig. 12(a), the maximum PCE was achieved with the designated R_L = 1 kΩ. As R_L increases above 1 kΩ, I_Load drops and P_Load for the same V_OUT decreased. Therefore, the internal power dissipation (P_Tr.sw + P_CMP) in (2) becomes more dominant, reducing the PCE. On the other hand, when R_L decreased below 1 kΩ, higher input current is required to drive the heavy load, increasing P_Tr.Ron and V_Drop, as shown in Fig. 12(b), and resulting in the PCE to decrease.

Fig. 12.

Measured (a) PCE and (b) V_Drop versus R_L with V_OUT = 2.4 and 3.2 V, C_IN = C_L = 1 μF, and f_c = 13.56 MHz.

Fig. 13 shows the measured, simulated, and calculated PCE and V_Drop versus f_c with R_L = 1 kΩ. The comparator offsets of the proposed voltage doubler were designed for operation around f_c = 13.56 MHz. The PCE in Fig. 13(a) sharply decreased at higher f_c because the comparator delays became too long and allowed for back current to flow from C_L back to the L₂C₂ tank. At lower operating frequencies the PCE decreased again, though at a slower rate, due to the fixed comparator offsets and CS inverter delays leading the pass transistors to turn off earlier than they should, thus conducting smaller amount of power to the load. Fig. 13(b) shows the measured versus V_Drop, f_c which is also affected by the switching times. Even though V_OUT and R_L were fixed in all frequencies, lower PCE required higher input power to achieve the same V_OUT. Therefore, V_Drop increased at frequencies that had lower PCE.

Fig. 13.

Measured (a) PCE and (b) V_Drop versus f_c with V_OUT = 2.4 and 3.2 V, R_L = 1 kΩ, and C_IN = C_L = 1 μF.

We have measured three different chips, all of which showed similar characteristics as in Figs. 11 – 13, where the measured PCE is slightly lower than the simulated PCE due to process variations. Since the active voltage doubler has been optimized for a certain operating condition, i.e., V_OUT = 2.4 V, R_L = 1 kΩ, and f_c = 13.56 MHz, the PCE somewhat deviates from its optimal point when the operating condition changes. However, the voltage doubler still operates properly with PCE > 74% within the range of V_OUT (2 ~ 4 V) and R_L (0.5 ~ 1.5 kΩ), as long as f_c remains at 13.56 MHz. f_c is unlikely to change, because it is often controlled externally by a crystal-based oscillator that drives the power amplifier, shown in Fig. 1. The best way to oppose such PCE deviations from the optimal point is to form another closed loop around the voltage doubler at the system level to monitor V_OUT and change CTL0:3 at any operating condition via a well-defined search algorithm.

Fig. 14 shows post-layout simulated power consumption in the key components of the active voltage doubler in a pie-chart, when V_IN,peak = 1.45 V, V_OUT = 2.4 V, R_L = 1 kΩ, C_IN = C_L = 1 μF, and f_c = 13.56 MHz. It can be seen that 80% of the input power has been delivered to the load, while the majority of the remaining 20% dissipates in the pass transistors (N₁ and P₁), followed by the comparators (CMP_N and CMP_P). Losses in N₁ (6.3%) and P₁ (6.4%) are due to their R_on, which are represented in our model by P_Tr.Ron. Power dissipation in CMP_N (2.6%) and CMP_P (4.6%) include the comparators' internal power consumption as well as the switching loss, which are represented in the model by P_CMP and P_Tr.sw, respectively. In addition, the offset-controlled functions in CMP_N and CMP_P consume only 29 μW and 45 μW, which are 0.4% and 0.6% of the total power consumption, respectively.

Fig. 14.

Simulated power consumption pie-chart when V_IN,peak = 1.45 V, V_OUT = 2.4 V, R_L = 1 kΩ, C_IN = C_L = 1 μF, and f_c = 13.56 MHz.

C. Performance Summary and Comparison

Table I benchmarks several recently reported rectifiers and voltage doublers used in various power management blocks along with the proposed active voltage doubler. In rectifiers, a major limitation is that V_OUT is always less than V_IN,peak, as expected. Passive voltage doublers cannot provide high PCE for the reasons discussed in Section I. Two active voltage doublers have been recently reported in the literature for energy scavenging from mechanical vibrations via piezoelectric transducers, which are designed to operate at low frequencies in the order of 100 Hz [45], [46]. Even though these active voltage doubles offer high PCE, they are not suitable for inductively powered biomedical applications, which operate at much higher frequencies through near-field inductive links. What we have presented in the last column is, to the best of our knowledge, the first active voltage doubler that can operate at 13.56 MHz in the ISM-band, providing 2.4 V of DC supply to a 1 kΩ load from a peak AC input voltage of only 1.46 V, while offering the highest measured PCE of 79%. This is made possible with the accurate timing provided by offset-controlled high speed comparators for both rising and falling slopes of the carrier signal to maximize the power delivered to the load when turning the pass transistors on, while minimizing the back currents when turning them off. Table II summarizes the specifications of the active voltage doubler and the inductive link used in our measurements.

TABLE I.

Rectifier and Voltage Doubler Benchmarking

Publication		2007 [23]	2009 [32]	2009 [33]	2011 [44]	[47]	2009 [28]	2011 [29]	2008 [45]	2011 [46]	This work
Technology		0.5 μm CMOS	0.35 μm CMOS	0.18 μm CMOS	0.5 μm CMOS	Discrete (1N4148)	0.18 μm CMOS	0.8 μm HVCMOS	0.35 μm CMOS	Discrete (TLV3702)	0.5 μm CMOS
Structure		Passive rectifier (Schottky)	Active rectifier	Active rectifier	Active rectifier	Passive voltage doubler	VTh-cancelled voltage multiplier	VTh-cancelled voltage doubler	Active voltage doubler	Active voltage doubler	Active voltage doubler
VIN, peak (V)		5	2.4	1.25	3.8	2.3	0.8	11.1	N/A	1.2	1.46
VOUT (V)		4.2	2.08	0.96	3.12	2.4	1.8	20	3	2.24	2.4
VCE (%)*		84	86.7	76.8	82.1	52.2	56.3	90.1	N/A	93.3	82.2
RL (kΩ)		2.8	0.1	2	0.5	1	270	20	400	0.1	1
CIN / CL (μF)		− / 0.0022**	− / 1	− / 200 pF	− / 10	1 / 1	N/A	− / 1	N/A	− / 100	1 / 1
fc (MHz)		4	0.2~1.5	10	13.56	13.56	13.56	13.56	200 Hz	20 Hz	13.56
Area (mm2)		N/A	0.4	0.86	0.18	N/A	0.83	N/A	N/A	N/A	0.144
PCE (%)	Sim.	N/A	87	N/A	87	N/A	N/A	90.5	95	N/A	80
	Meas.	75	N/A	76	80.2	51	54.9	N/A	> 90	83	79

^*Voltage conversion efficiency (VCE) = V_Out / (V_IN,peak × multiplication factor)

^**On-chip capacitor. All other C_IN and C_L are off-chip components.

V. Conclusions

Comparator-based active rectifiers are considered the most promising solutions to achieve not only high PCE but also low dropout voltage in inductive power transmission. These AC-to-DC converters, however, need peak input voltage that should always be higher than the desired output voltage. This will limit the operation range and safe voltages of most inductively- powered devices, such as IMDs and RFID tags, which tend to have weakly coupled links. In order to overcome this limitation, we have developed a fully integrated power-efficient active voltage doubler with offset-controlled high speed comparators, which can offer high PCE and low dropout voltage comparable to active rectifiers, while increasing V_OUT well above the V_IN,peak. Three different offset control functions, built in the comparators, compensate for their turn-on and turn-off delays to maximize forward current to the load, while minimizing the back current. In addition, a novel startup circuit has been added to the voltage doubler to guarantee its reliable initial operation as a passive voltage doubler when V_OUT = 0 V. The relationship between the active voltage doubler PCE, dropout voltage, and several power loss factors has also been analyzed to provide designers with better insight towards maximizing the PCE.

Biographies

Hyung-Min Lee (S'06) received the B.S. degree (summa cum laude) in electrical engineering from Korea University, Seoul, Korea in 2006, and the M.S. degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2008.

Since 2009, he has been with the GT-Bionics lab in the Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, where he is working toward the Ph.D. degree. His research interests include analog/mixed-signal integrated circuits and power management integrated circuits for biomedical implantable systems. He has received the Silver Prize in the 16th Human-Tech Thesis Prize from Samsung Electronics, Korea, and the Commendation Award in the 4th Outstanding Student Research Award from Taiwan Semiconductor Manufacturing Company, Taiwan, both in 2010.

Maysam Ghovanloo (S'00–M'04–SM'10) was born in Tehran, Iran, in 1973. He received the B.S. degree in electrical engineering from the University of Tehran, Tehran, Iran, in 1994, the M.S. degree in biomedical engineering from the Amirkabir University of Technology, Tehran, Iran, in 1997, and the M.S. and Ph.D. degrees in electrical engineering from the University of Michigan, Ann Arbor, in 2003 and 2004, respectively.

From 2004 to 2007, he was an Assistant Professor in the Department of Electrical and Computer Engineering, North Carolina State University, Raleigh. He joined the faculty of the Georgia Institute of Technology, Atlanta, in 2007, where he is currently an Associate Professor and the founding director of the Georgia Tech Bionics Laboratory in the School of Electrical and Computer Engineering. He has authored or coauthored more than 100 conference and journal publications.

Dr. Ghovanloo is an Associate Editor of the IEEE Transactions on Biomedical Circuits and Systems and the IEEE Transactions on Biomedical Engineering. He has received awards in the 40th and 41st Design Automation Conference (DAC)/International Solid-State Circuits Conference (ISSCC) Student Design Contests. He has organized special sessions and was a member of Technical Review Committees for several major conferences, such as ISSCC and ISCAS, in the areas of biomedical circuits, sensors, and systems. He is a member of the Tau Beta Pi, the Sigma Xi, and the IEEE Solid-State Circuits Society, the IEEE Circuits and Systems Society, and the IEEE Engineering in Medicine and Biology Society.

Appendix

In this section, we calculate the PCE in (2) and V_Drop in (1) using simplified voltage doubler waveforms shown in Fig. 15. In this analysis, D is the voltage doubler operating duty cycle, V_Cin is the voltage across C_IN, and T = 1/f_c is the period of one operating cycle. In this simplified model, we assume: 1) V_IN (t) is sinusoidal, 2) C_L and C_IN are large enough to maintain V_OUT and V_Cin almost constant during T/2, i.e., ΔV ≈ 0 V, 3) comparators turn on and off their pass transistors, P₁ and N₁, at ideal times and their outputs, V_CP and V_CN, have negligible rising and falling times, and 4) V_VD,peak − V_OUT = V_SS − V_VD,min, therefore, V_Cin can be expressed as V_OUT/2.

Fig. 15.

Simplified voltage waveforms of the active voltage doubler for the theoretical PCE analysis.

For this analysis, we also used the optimal size ratio ofP₁ and N₁ in [48] which leads to minimum R_onp + R_onn in a given area

$${\left(\frac{W_p}{W_n}\right)}_{\mathit{opt}}=\sqrt{\frac{{\mu }_n{C}_{ox}(V_{\mathit{OUT}}-V_{\mathit{Thn}})}{{\mu }_p{C}_{ox}(V_{\mathit{OUT}}-\mid V_{\mathit{Thp}}\mid )}}.$$ (6)

While (3) and (4) can be solved directly by knowing circuit parameters, D needs to be derived to obtain P_Tr.Ron in (5)

$$D=\frac{T_b-T_a}{T}=\frac{T_d-T_c}{T}$$ (7)

$$\begin{array}{cc}\hfill & T_a=\frac{T}{4}-\frac{DT}{2},T_b=\frac{T}{4}+\frac{DT}{2},\hfill \\ \hfill & T_c=\frac{3T}{4}-\frac{DT}{2},T_d=\frac{3T}{4}+\frac{DT}{2}.\hfill \end{array}$$ (8)

The charging current flowing through pass transistors, P₁ and N₁, needs to be the same as the total output and dissipated currents of the voltage doubler. Therefore

$$\begin{array}{cc}\hfill {\int }_{T_a}^{T_b}{I}_{p}dt& ={\int }_{T_c}^{T_d}{I}_{n}dt\hfill \\ \hfill & ={\int }_0^T(I_{\mathit{Load}}+I_{\mathit{CMP}}+I_{Tr,sw})dt\hfill \end{array}$$ (9)

$$\begin{array}{cc}\hfill {\int }_{T_a}^{T_b}{I}_{p}dt& ={\int }_{T∕4-DT∕2}^{T∕4+DT∕2}\frac{V_{VD}\left(t\right)-V_{\mathit{OUT}}}{R_{\mathit{onp}}}dt\hfill \\ \hfill & =\left(\frac{V_{\mathit{OUT}}}{R_L}+\frac{P_{\mathit{CMP}}}{V_{\mathit{OUT}}}+\frac{P_{Tr,sw}}{V_{\mathit{OUT}}}\right)T.\hfill \end{array}$$ (10)

In (10), V_VD (t) can be written as

$$\begin{array}{cc}\hfill V_{VD}\left(t\right)& =V_{IN}\left(t\right)+V_{Cin}=V_{IN}\left(t\right)+\frac{V_{\mathit{OUT}}}{2}\hfill \\ \hfill & =V_{IN,\mathit{peak}}\sin \left(\frac{2\pi }{T}t\right)+\frac{V_{\mathit{OUT}}}{2}\hfill \\ \hfill & =\frac{\frac{V_{\mathit{OUT}}}{2}}{\sin \left(\frac{2\pi }{T}{T}_a\right)}\sin \left(\frac{2\pi }{T}t\right)+\frac{V_{\mathit{OUT}}}{2}.\hfill \end{array}$$ (11)

By substituting (11) in (10), D can be obtained with given values of R_onp, R_L, and V_OUT from

$$\begin{array}{cc}\hfill R_{\mathit{onp}}& =\left(\frac{1}{R_L}+\frac{P_{\mathit{CMP}}+P_{Tr,sw}}{V_{\mathit{OUT}}^2}\right)\hfill \\ \hfill & =\left(\frac{\cos \left(\right(\frac{1}{2}-D\left)\pi \right)-\cos \left(\right(\frac{1}{2}+D\left)\pi \right)}{4\pi \sin \left(\right(\frac{1}{2}-D\left)\pi \right)}-\frac{D}{2}\right)\hfill \end{array}$$ (12)

where P_CMP and P_Tr,sw can be approximated from the simulation results and (4), respectively. Then, we can solve P_Tr.Ron in (5) using D from (12), and the PCE can be calculated by substituting (3) – (5) in (2). In addition, using MATLAB we can easily try various R_onp values (e.g., by changing W_p) and find the optimal size of the pass transistors, which results in minimum power loss and maximize the PCE. V_Drop can also be estimated by obtaining V_IN,peak from (11) and substituting it in (1).