An Adaptive Reconfigurable Active Voltage Doubler/Rectifier for Extended-Range Inductive Power Transmission

Abstract

We present an adaptive reconfigurable active voltage doubler (VD)/rectifier (REC) (VD/REC) in standard CMOS, which can adaptively change its topology to either a VD or a REC by sensing the output voltage, leading to more robust inductive power transmission over an extended range. Both active VD and REC modes provide much lower dropout voltage and far better power conversion efficiency (PCE) compared to their passive counterparts by adopting offset-controlled high-speed comparators that drive the rectifying switches at proper times in the high-frequency band. We have fabricated the active VD/REC in a 0.5-µm 3-metal 2-poly CMOS process, occupying 0.585 mm² of chip area. In an exemplar setup, VD/REC extended the power transmission range by 33% (from 6 to 8 cm) in relative coil distance and 41.5% (from 53° to 75°) in relative coil orientation compared to using the REC alone. While providing 3.1-V dc output across a 500-Ω load from 2.15- (VD) and 3.7-V (REC) peak ac inputs at 13.56 MHz, VD/REC achieved measured PCEs of 70% and 77%, respectively.

I. Introduction

Modern implantable microelectronic devices (IMDs) require high power efficiency and performance to enable more efficacious therapies, particularly in neuroprostheses such as retinal and cochlear implants [1]. Inductive wireless power transmission across the skin is currently the only viable solution for providing sufficient power to such IMDs without imposing size and power constraints of implanted batteries [2]. On the downside, unlike batteries that provide a stable power source, unexpected variations in the coils’ mutual coupling M, which mainly result from coil misalignments, can lead to wide variations in the received voltage across the secondary to the extent that the input voltage may not be sufficient to supply the IMD [3]. Hence, there is a need to improve the robustness of the inductive power links without sacrificing efficiency to allow the IMDs to operate over a wider range of received input voltages. There are also other applications such as wireless sensors, radio frequency identification, and near-field communication, in which extending the range of loosely coupled inductive links is highly desired [4].

Active rectifiers (RECs) and voltage doublers (VDs) using synchronous switches have been widely used to convert ac input signals to dc outputs for inductively powered applications [5]–[8]. RECs require peak inputs higher than the desired outputs, which may be temporarily limited by the weak coupling of the inductive links. On the contrary, active VDs are capable of generating higher output voltages, but their power conversion efficiencies (PCEs) are generally lower than those of active RECs with similar size. In order to address such limitations, we have proposed a power-efficient reconfigurable active VD/REC for robust wireless power transmission through inductive links over an extended range. Both VD and REC modes are integrated into a single structure, employing low dropout active synchronous switches, leading to high PCE. Moreover, by adding an output-voltage-sensing circuit, VD/REC can automatically change its operating mode to either VD or REC depending on which one is a better choice for generating the desired output voltage to accommodate with a wider range of mutual coil arrangements.

Fig. 1 shows the block diagram of a wireless power transmission link that includes the proposed VD/REC. A power amplifier (PA) drives the primary coil L₁ at the designated carrier frequency (f_c = 13.56 MHz), which improves the coils’ quality factors (Q) and increases the overall power transmission efficiency, while maintaining the sizes of LC components small for implantable applications [3]. A coupled signal across the secondary L₂ creates an ac voltage V_IN (= V_INP − V_INN) across L₂C₂ which is tuned at f_c. VD/REC, which follows the L₂C₂ tank, converts V_IN to an automatically adjusted dc voltage V_OUT for supplying the load after regulation. If V_IN falls below a certain level, which is determined by comparing a portion of V_OUT with a reference voltage V_REF using a hysteresis comparator, then Mode = 1 and VD/REC operates in VD mode. Since the VD can generate the desired V_OUT with much lower V_IN than the REC, VD/REC can still provide sufficient V_OUT to the load even with decreased V_IN. On the other hand, if V_IN increases above V_REF + hysteresis window, then Mode = 0 and VD/REC will operate in the REC mode, which can achieve higher PCE than the VD mode while generating the desired V_OUT.

Fig. 1.

Block diagram of an inductively powered device with emphasis on the wireless power transmission through the proposed active VD/REC converter.

The rest of this brief, which is an extended version of [9], is organized as follows. Section II describes the concept and implementation of active VD/REC. Section III presents the circuit details and design considerations including the offset-controlled high-speed comparators, start-up circuit, and mode selection circuit. The measurement results are in Section IV, followed by the conclusion in Section V.

II. Active VD/REC Architecture

A. Concept of the Active VD/REC

The concept of active VD/REC starts from combining two separate ac-to-dc converters, a REC and a VD, into a single structure in which the operating mode, REC or VD, is selected by an external mode selection signal. Fig. 2 shows the conceptual diagram of the active VD/REC converter which consists of a full-wave REC and a VD with active diodes. The full-wave REC requires two diodes D₁ and D₂ and a cross-coupled NMOS pair N₁ and N₂. Either the D₁−N₂ path or the D₂−N₁ path is activated depending on the amplitudes of V_INP and V_INN to transfer the input power to the output filtering capacitors C_F/2. The VD requires only two diodes D₁ and D_N1, charging one C_F per half cycle depending on the polarity and amplitude of V_IN (= V_INP − V_INN). Therefore, V_OUT becomes almost doubled compared to the peak voltage of V_IN. In order for VD/REC to include both structures, D₁ is shared, and D₂ and N₂ have enable functions to turn them on/off in the REC and VD modes, respectively. N₁ operates as part of a cross-coupled pair in the REC mode, while it is reconfigured as an NMOS diode D_N1 in the VD mode. V_INN and V_M are also shorted through a switch N₃ in the VD mode. VD/REC utilizes active diodes D₁, D₂, and D_N1, in which rectifying pass transistors are driven by fast comparators to operate as switches in the deep triode region with low dropout voltages. Therefore, these active diodes dissipate less power compared to passive diodes, leading to higher PCE in both operating modes.

Fig. 2.

Conceptual diagram of the active VD/REC converter in which a full-wave REC and a VD are combined using active diodes.

B. Implementation of the Active VD/REC

Fig. 3 shows a simplified schematic diagram of the VD/REC, consisting of PMOS and NMOS active diodes D₁, D₂, and D_N1, in which pass transistors P₁, P₂, and N₁ are driven by high-speed comparators CMP_P1, CMP_P2, and CMP_N1, respectively, to minimize ac–dc dropout voltage and power loss. Mode signals EN and EN_B, which are derived from the mode control circuit, can reconfigure the VD/REC topology for rectification or doubling functions, as shown in Fig. 2. In the REC mode (EN = 0 and EN_B = 1), the gates of N₁ and N₂ are connected to V_INN and V_INP, respectively, resulting in a cross-coupled NMOS pair with positive feedback, while CMP_N1 is deactivated. Both PMOS active diodes are utilized in this mode, alternating every half cycle to transfer input power to the load. For example, when V_INP > V_INN, N₂ turns on, while N₁ turns off. Then, when V_INP > V_OUT, the CMP_P1 output goes low, turning P₁ on with a low dropout voltage. The input current in this case flows from V_INP through P₁ to charge C_F/2 and returns back to V_INN through N₂. In the VD mode (EN = 1 and EN_B = 0), P₂ and N₂ are always off, and CMP_P2 is deactivated. Only P₁ and N₁ operate as active diodes, while N₃ strongly connects V_INN to V_M for charging the filtering capacitors C_F, one per half cycle, to almost double V_OUT in reference to V_SS.

Fig. 3.

Schematic diagram of the proposed VD/REC employing active diodes to achieve lower dropout voltage and higher PCE for both REC and VD modes.

Since the comparators in active diodes are supplied from V_OUT, which is initially at 0 V, self-start-up capability is a feature necessary in active VD/REC. The start-up circuit in Fig. 3 monitors V_OUT and sets SU = EN = EN_B = 0 when V_OUT is too low. At start-up, N₁ and N₂ are cross-coupled through multiplexers (MUXs), and P₁ and P₂ are diode connected through P₃ and P₄, respectively, forming a passive REC, which charges V_OUT regardless of the comparators’ status up to the point where V_OUT reaches a desired level. Then, SU toggles to enable VD/REC to operate normally. PMOS body terminals V_B1 and V_B2 are always connected to the highest potential among V_INP,N and V_OUT via their body bias circuits.

III. Circuit Details and Design Considerations

In order to drive large pass transistors at 13.56 MHz, comparators need to have short turn-on/turn-off delays, which may otherwise reduce the PCE by either decreasing the input power delivered to the load or allowing instantaneous reverse current back from C_F. We have used high-speed comparators with built-in offset-control functions to expedite V_OUT transitions by compensating for both turn-on and turn-off delays [10]. Fig. 4 shows the schematic diagram of the high-speed comparator CMP_P, which is equipped with three offset-control functions: turn-on, turn-off, and output-locking offsets. In Fig. 4, P₆, P₇, N₇, N₈, P₁₁, and N₁₄ form a common-gate comparator, in which input voltages (V_OUT and V_INP,N) are applied to the sources of P₆ and P₇. The turn-on offset block, consisting of P₈ and P₉ current sources and P₁₀ control switch, injects additional offset current to force V₁ to increase earlier, leading to fast turn-on of P_1,2 in Fig. 3. The offset-control signal V_OS1P deactivates P₁₀ just after turning P_1,2 on and activates it again after the current-starved inverter (INV₁ and N₁₅) delay, which does not need to be accurate as long as it is shorter than one carrier cycle. The turn-off offset function utilizes the size mismatch between N₇ and N₈, where the larger N₈ pulls additional current from the V₁ node, forcing V₁ to start dropping earlier to turn P_1,2 off at the right time. After the comparator output V_CP goes high and turns P_1,2 off, N₁₁ is activated by V_OS2P for the current-starved inverter delay time to keep V₁ low and prevent V_CP from bouncing due to V_INP,N variations. CMP_N has a similar but symmetrical structure. In addition, 4-bit off-chip digital control signals, CTL0:1 for CMP_P and CTL2:3 for CMP_N, are utilized to adjust the switching times of VD/REC against process variations.

Fig. 4.

Schematic diagram showing three built-in offset-control functions, which are turn-on, turn-off, and output-locking offsets, in our high-speed comparator CMP_P [10].

In the start-up circuit in Fig. 5(a), when V_OUT is very low, P₁₂ turns off and SU goes low, resulting in P₁ and P₂ in Fig. 3 to stay diode connected through P₃ and P₄, respectively. During the same period, both EN and EN_B of the mode control circuit in Fig. 5(b) become low, so all comparators are in the sleep mode while N₁ and N₂ are cross-coupled through MUXs, leading the VD/REC to operate as a passive REC. With SU = EN_B = 0, N₁₃ in Fig. 4 forces V_CP1,2 to be high, further supporting P₁ and P₂ to be diode connected. When V_OUT > V_Th(N16) + V_Th(P12), SU toggles high, turning P₃ and P₄ off, releasing the comparator outputs, and allowing P₁ and P₂ to operate as switches [10]. The mode control circuit consists of two pairs of level shifters and logic gates, one of which is shown in Fig. 5(b), to level shift the mode signal to either V_B1 or V_B2 (in Fig. 3) for creating the EN and EN_B signals, which control various switches at proper voltage levels. In Fig. 5(c), the body bias circuit automatically connects V_B1 and V_B2 to max(V_INP, V_OUT) and max(V_INN, V_OUT), respectively, through P₁₇ and P₁₈ [6].

Fig. 5.

Schematic diagrams of the (a) start-up circuit, (b) mode control circuit, and (c) body bias circuit.

IV. Measurement Results

A. Chip Micrograph and Measured Waveforms

VD/REC was fabricated in the ON Semiconductor 0.5-µm 3M2P n-well standard CMOS process, occupying 0.585 mm². Fig. 6 shows the chip micrograph and floor plan of the VD/REC, low dropout regulator (LDO), and bandgap reference (BGR). The sizes of the main rectifying transistors are as follows: W_P1,2 = 3300 µm, W_N1,2 = 1800 µm, and W_N3 = 12 000 µm with a minimum length of L = 0.6 µm.

Fig. 6.

Fabricated chip micrograph of the VD/REC in the ON Semiconductor 0.5-µm standard CMOS process, occupying an area of 0.585 mm².

Fig. 7 shows the measured input/output waveforms in the REC and VD modes with R_L‖C_F/2 = 1 kΩ‖0.5 µF (no regulator) at f_c = 13.56 MHz. The same supply voltage was applied to the PA on the primary side to verify the V_OUT difference between the REC and VD modes. In the REC mode (Mode = 0), V_INP and V_INN charge V_OUT alternatively, resulting in V_IN,peak(REC) = 3.35 V and V_OUT = 2.7 V. In the VD mode (Mode = 1), V_INN is shorted via N₃ to V_M, the middle voltage of V_OUT, and V_INP goes well above V_IN,peak(REC) to achieve V_OUT = 3.55 V with V_IN,peak(VD) = 2.6 V. Large instantaneous input currents flow into the VD/REC during the conduction period, inducing the voltage drop across N₃, which is V_INN − V_M. V_IN,peak(VD) is less than V_IN,peak(REC) because of a reduction in the inductive link Q factor due to higher input and output currents in the VD mode.

Fig. 7.

Measured input/output voltage waveforms in the (top) REC and (bottom) VD modes when R_L‖C_F/2 = 1 kΩ‖0.5 µF (no regulator) and f_c = 13.56 MHz.

B. Power Transmission Range and PCE Measurements

In order to verify the benefits of using the VD/REC over a REC, we have measured V_IN,peak and V_OUT while sweeping the relative distance (d) and orientation (θ) between a pair of coupled coils L₁ and L₂, as shown in Fig. 8. In this test setup, whose specifications are shown in Table II, a class-C PA on the transmitter side (Tx) drives the inductive link to induce a 13.56-MHz sinusoidal signal across the VD/REC. Fig. 9 shows the measured V_IN,peak and V_OUT versus d and θ and demonstrates how using the VD/REC extends the inductive link power transmission range in terms of the coils’ relative distance and angular misalignment compared to REC only. The hysteresis window of the off-chip comparator was set to 2.6–3.7 V and indicated on the graphs as horizontal dashed lines. In the d-sweep test, the VD/REC operates in the REC mode when d is small. V_OUT drops as d increases, and when d > 5.5 cm, VD/REC switches to the VD mode, increasing V_OUT by 0.8 V (30.8%). As a result, VD/REC maintains sufficient V_OUT > 2.5 V for coil separations up to d = 8cm, compared to the REC only, which fails at d > 6 cm (a 33% improvement). Similarly, VD/REC improved the inductive link tolerance to coil rotations by extending the range from θ = 53° (REC only) to θ = 75° (VD/REC) at d = 3 cm (a 41.5% improvement).

Fig. 8.

Test setup for measuring the PCE and input/output voltages of the active VD/REC ac-to-dc converter when sweeping the relative coil (top) distance and (bottom) orientation.

TABLE II.

Additional Active VD/REC Measurement Setup Specifications

Nominal output power	6 ~ 37 mW
Output filtering capacitor (CF)	1 µF
Output ripple (RL = 0.5 kΩ)	50 mVpp
Bandgap reference voltage (VREF)	1.187 V
Primary coil diameter / inductance (L1)	16.8 cm / 0.88 µH
Secondary coil diameter / inductance (L2)	3.0 cm / 0.41 µH
Total area of the VD/REC	0.585 mm2

Fig. 9.

Measured input and output voltages while sweeping the coil relative distance (d) and orientation (θ) in Fig. 8, which clarify that using VD/REC extends the inductive link power transmission range.

To consider the practical conditions in which the output voltage of the VD/REC varies due to coil misalignments as well as loading changes, we measured the PCE while sweeping V_OUT by adjusting the Tx output power delivered to the primary coil L₁. The PCE of VD/REC can be defined as the delivered power to the load over the input power from the L₂C₂ tank. Fig. 10 shows the measured PCE versus V_OUT in both REC and VD modes with R_L = 0.5 and 1 kΩ at f_c = 13.56 MHz. The highest PCEs of the REC and VD modes were 77% and 70%, respectively, at V_OUT = 3.1 V with R_L = 0.5 kΩ. The PCE drops for V_OUT > 3.7 V and V_OUT < 2.8 V are mainly due to the pass transistor sizing and comparator offsets which were designed for V_OUT = 2.8−3.7 V. The VD/REC still operates properly against V_OUT variations with PCE > 74% within V_OUT = 2.6−4.3 V in the REC mode and PCE > 68.5% within V_OUT = 2.5−3.7 V in the VD mode for R_L = 0.5 kΩ. The V_OUT range is determined based on the hysteresis comparator window of 2.6–3.7 V. Table I benchmarks the proposed active VD/REC against several recently reported RECs and VDs. Table II provides a few additional specifications of the VD/REC and the inductive link used in our measurements.

Fig. 10.

Measured PCE versus V_OUT with R_L = 0.5 and 1 kΩ at f_c = 13.56 MHz, leading to the highest PCEs of 77% and 70% in the REC and VD modes, respectively.

TABLE I.

REC and VD Benchmarking

Publication		[5]	[6]	[7]	[8]	This work
Technology		0.18µm	0.5µm	0.18µm	0.8µm	0.5µm CMOS
Structure		REC	REC	Multiplier	VD	Active VD/REC
						VD	REC
VIN, peak (V)		1.25	3.8	0.8	11.1	2.15	3.7
VOUT (V)		0.96	3.12	1.8	20	3.1	3.1
VCE (%)*		76.8	82.1	56.3	90.1	72.1	83.8
RL (kΩ)		2	0.5	270	20	0.5
fc (MHz)		10	13.56	13.56	13.56	13.56
Area (mm2)		0.86	0.18	0.83	N/A	0.585
PCE (%)	Sim.	N/A	87	N/A	90.5	75	81
	Meas.	76	80.2	54.9	N/A	70	77

^*Voltage conversion efficiency (VCE) = V_OUT/(V_{IN, peak} × multiplication factor)

C. In Vitro Experiments

Inductively powered IMDs that employ the active VD/REC converter need to be hermetically sealed in biocompatible materials and placed in a conductive tissue environment with high permittivity, which can affect not only the secondary coil characteristics but also the VD/REC performance [11]. In order to emulate the implant environment, we conducted in vitro experiments with the test setup in Fig. 11, in which the secondary coil (L₂) was wrapped in a piece of steak (bovine sirloin). Fig. 12 shows the measured V_IN,peak and V_OUT while sweeping the coils’ relative distance (d) in the air (Fig. 8) and muscle (Fig. 11) environments. The muscle environment leads to a small reduction in both V_IN,peak and V_OUT compared to the air environment when d is increased. This is because wrapping L₂ with a piece of steak increases its parasitic capacitance and resistance, leading the quality factor (Q) of the secondary coil to decrease and the power loss in its parasitic resistance to increase. However, these curves show that using the VD/REC still extends the inductive link power transmission range in both environments to d > 8 cm.

Fig. 11.

Test setup for in vitro experiments that resemble an IMD environment with the secondary coil L₂ wrapped in a piece of steak.

Fig. 12.

Measured input and output voltages while sweeping the coils’ relative distance in the air (Fig. 8) and muscle (Fig. 11) environments.

V. Conclusion

Inductive power transmission across the skin is considered the most promising solution for providing sufficient power to IMDs without suffering from size and power constraints of implanted batteries. However, large variations in the received voltage across the secondary coil, which mainly result from coil misalignments or loading variations, can lead to insufficient supply voltage for the IMD. In order to overcome this limitation, we have developed a power-efficient reconfigurable active VD/REC, which can automatically change its operating mode to operate as either a VD or a REC, depending on which one is more suitable for generating the desired output voltage at the highest possible PCE, enabling robust power transmission across the inductive link over an extended range. The presented VD/REC has been equipped with active diodes, in which high-speed comparators synchronously control MOS switches at proper times owing to their turn-on and turn-off offset functions, achieving high PCE and low dropout voltage. The measured results while sweeping the coils’ relative distance and orientation clearly verify that using the VD/REC extends the inductive power transmission range in both air and muscle environments.