Design of an ultra low power third order continuous time current mode ΣΔ modulator for WLAN applications

Abstract

This paper presents a third order continuous time current mode ΣΔ modulator for WLAN 802.11b standard applications. The proposed circuit utilized feedback architecture with scaled and optimized DAC coefficients. At circuit level, we propose a modified cascade current mirror integrator with reduced input impedance which results in more bandwidth and linearity and hence improves the dynamic range. Also, a very fast and precise novel dynamic latch based current comparator is introduced with low power consumption. This ultra fast comparator facilitates increasing the sampling rate toward GHz frequencies. The modulator exhibits dynamic range of more than 60 dB for 20 MHz signal bandwidth and OSR of 10 while consuming only 914 μW from 1.8 V power supply. The FoM of the modulator is calculated from two different methods, and excellent performance is achieved for proposed modulator.

Introduction

Today, according to progressive extension of digital system applications and abilities, digitizing the environmental analog world is more essential, especially in higher speeds and resolutions. Due to their capabilities to achieve high resolutions with a simple comparator, ΣΔ modulators are the case of interest. Because of their intrinsic oversampling, design of anti-aliasing filter is become more relaxed in ΣΔ modulators and also the size of required capacitances is reduced [1]. ΣΔ Modulators are now trends to cover not only audio [2] and biomedical [3] applications, but also growing through wireless applications such as WLAN, WCDMA, and GSM [4]. These applications require high speed modulators with high speed performance, i.e., wide bandwidth. For example, the required bandwidth for WLAN application is as wide as 20 MHz which the maximum Over Sampling Rate (OSR) is limited by the CMOS process restrictions.

Continuous Time ΣΔ Modulators (CTΣΔM) have been attained interesting performances in low power [5] and high speed [6] applications. The required bandwidth for CTΣΔM’s building blocks is more relaxed in comparison with switched capacitor techniques which results a significant reduction in their consumed power. Also, CTΣΔM requires much simpler anti-aliasing circuits [2]. ΣΔ modulators are designed by switched capacitor techniques and mostly by voltage mode circuits, but in the result of decreasing transistor feature sizes and hence decreasing the power supply and voltage headroom, these techniques have encountered with several problems in recent years.

Instead, current mode techniques can be suitable alternatives for switched capacitor circuits because of their less sensitivity to voltage headroom. The other benefits of current mode circuits over their voltage mode counterparts are smaller propagation delay and therefore more speed, compatibility with smaller feature sizes, less sensitivity to electrostatic discharge, suitability for sensors and electrodes, and no need for linear capacitances which are very difficult to be implemented in the state-of-the-art digital VLSI technology.

One of the most traditional circuit blocks for implementing of continuous time current mode integrators is current mirror. Because the current output of other circuits, e.g., current conveyors or OTAs, cannot be shared simply with other circuits, multiple outputs may be required for constructing a filter. But, it is obtained very simply by making as very replica circuits as need by current mirror circuits [7]. This paper proposes a current sharing technique to improve the bandwidth of the current mirror based integrator which also results a much simpler biasing circuitry for the integrator. Also, a novel comparator is introduced based on dynamic latches.

The paper is organized as follows: in Section 2, system design and scaling are described. Section 3 introduces circuit implementation of modulator’s building blocks. Section 4 gives the simulation results followed by a conclusion in Section 5.

Methodology

System level design

A traditional solution for system level design of CTΣΔM problem is starts from equivalent discrete time system and then converting the attained characteristics to their continuous time counterparts by impulse invariant transform [8]. Feedback structure is used for more stability, no need for fast and precise current adders and having no out-of-band peaking in its signal transfer function. Since the system is designed for WLAN standard, it is required at least 7 bits of resolution (43 dB of Dynamic Range (DR)) and 20 MHz of Bandwidth (BW) [9]. For the defined characteristics, the required OSR could be calculated from Eq. (1):

$$\text{OSR}={\left(\frac{\frac{2}{3}\text{DR}\times {\pi }^{2L}}{(2L+1){(2^N-1)}^2}\right)}^{\frac{1}{2L+1}}$$ (1)

where L is the order of the modulator and N is the number of quantizer’s bits. Considering N ≡ 1 (monobit quantizer), one could sketch a diagram for DR versus L and OSR as shown in Fig. 1.

Fig. 1.

Dynamic range diagram of monobit Sigma–Delta modulators versus the modulator order and OSR.

It can be seen from Fig. 1 that, for second order modulator, the required OSR is more than 16. This OSR could be achieved by a sampling rate as much as 640 MHz which is hardly attainable by 0.18 μm standard CMOS process. Hence, choosing of the third order modulator is more reasonable which requires OSR of 10 and therefore the sampling rate of 400 MHz, a much simpler value to be achieved. Fig. 2 illustrates the system schematic of the feedback formed third order ΣΔ modulator.

Fig. 2.

The system of proposed modulator.

The Noise Transfer Function (NTF) of such a system could be calculated by Scheirer toolbox as follows:

$$\text{NTF}(z)=\left(\frac{{(z-1)}^3}{(z-0.6694)(z^2-1.531z+0.6639)}\right)$$ (2)

The desired continuous time system is achieved by transforming the attained NTF from discrete time system by impulse invariant technique to its continuous time equivalence and equalizing it with the resulting NTF from continuous time block diagram, which itself could be calculated from standard signal flow-graph techniques such as Mason method. The method is completely described by Ortmanns and Gerfers [8]. The equivalent continuous time transfer function is:

$$\text{NTF}(s)=\frac{s(s-0.3184)(s+0.121)}{(s+0.4014)(s^2+0.4096s+0.1644)}$$ (3)

As the results, system coefficients are calculated. After defining coefficients, the system is scaled to achieve suitable levels for integrators and quantizer. Power spectrum density and dynamic range diagrams are illustrated in Figs. 3 and 4, respectively. The system exhibits 68 dB of dynamic range and 61 dB of maximum SNDR for Over Sampling Ratio (OSR) of 10 and bandwidth of 20 MHz compatible with WLAN standard. Now, the system is ready to be implemented by transistor circuits.

Fig. 3.

PSD of the system of Fig. 2.

Fig. 4.

The dynamic range of system of Fig. 2.

Circuit level design

Subsequent to system design and optimization, modulator’s building blocks must be implemented in circuit level. All circuit blocks are implemented in 0.18 μm standard CMOS technology. The modulator is comprised of three major building blocks as follows:

Integrator

The most important building block of the ΣΔ modulator is the integrator. Fig. 5 illustrates a simple current mirror continuous time integrator. Neglecting the output impedance of transistors and parasitic capacitances and assuming identical transistors, circuit transfer function can be obtained from:

$$\frac{i_{\mathit{op}}-i_{\mathit{on}}}{i_{\mathit{ip}}-i_{\mathit{in}}}=\frac{-g_m}{\mathit{Cs}}$$ (4)

which determines the continuous time integrating operation of the circuit. From CTΣΔM theory [11], the below conditions must be satisfied;

$$\frac{g_m}{C}=\frac{1}{T}$$ (5)

where T is the sampling period. The more precise transfer function of the circuit, by considering ro and C_gd, is [12]

$$\frac{i_{\mathit{op}}-i_{\mathit{on}}}{i_{\mathit{ip}}-i_{\mathit{in}}}=A_0\frac{1-\frac{s}{z_1}}{1+\frac{s}{p_1}}$$ (6)

where z₁ is the zero of the circuit and given by

$$z_1=\frac{g_m-g_{\mathit{ds}}}{2C_{\mathit{gd}}}$$ (7)

also, p₁ is the system’s pole and A₀ is the integrator DC gain:

$$p_1=\frac{2g_{\mathit{ds}}}{C+4C_{\mathit{gd}}}$$ (8)

$$A_0=\frac{g_m-g_{\mathit{ds}}}{2g_{\mathit{ds}}}$$ (9)

As a rule of thumb, DC gain must be equal with or more than the OSR [13]. The desired values for achieving a modulator with 20 MHz bandwidth and 400 MHz sampling rate are:

$$A_0⩾\text{OSR}\to A_0⩾10$$ (10)

Integrating capacitance, C, is defined by technological and layout considerations and chosen to be 0.5 pF. By neglecting C_gd in comparison with C and choosing the system pole to be smaller than 100 KHz satisfying WLAN standard criterion, gds become less than 100 nS which is translates to 10 MΩ of output resistance. This huge amount of output resistance may not realizable by a single stage current mirror and employing of cascade structure is inevitable. For achieving the desired DC gain, A₀ must satisfies Eq. (10) and hence g_m > 15g_ds. This could be attained by cascade structure with low biasing current. Eq. (5) implies that the integrator gain (gm/C) must be greater than the sampling frequency (e.g., 4 × 108 here), and hence, gm must be greater than 200 μS.

Fig. 5.

A simple current mirror integrator introduced by Aboushady et al. [10].

One of the most important problems of cascade structures is their biasing circuit complexities. Such circuits need three different bias sources, in addition to the supply source, for proper working which may be difficult to be achieved precisely. In this paper, the cascade circuit is configured to reduce the number of required bias sources to two. Also, by suitable design of transistor sizes, in addition to satisfying all mentioned conditions, these biasing sources became equal, and hence, the number of biasing sources reduced to one which implies the extremely simple biasing circuit.

A notable characteristic of current mode circuits, which is completely in contrary with their voltage mode counterparts, is their input and output resistances. In addition to loading effects considerations, input resistance should be as low as possible to enhance the integrator dynamic range and bandwidth. Increasing the dynamic range as the result of decreasing the input resistance is justified by this fact that when a specific current inputs the circuit, causes lower variations in the voltage of input node. If these variations are large, the voltage of input node may reach to one of its two extremes (cutting off the input transistors and/or pushing them toward triode region), which degrades the operation of the circuit. Therefore, the smaller the input resistance, the larger the input current need to conveys the circuit to its extremes. This fact is implying that the smaller the input resistance, the larger the attained dynamic range. Also, decreasing the input resistance far the higher frequency pole of the integrator to much higher frequencies and hence increase the bandwidth of the integrator.

The proposed integrator is realized by a modified current mirror circuit that drives the integrating capacitors. This method reduces the input resistance of cascade current mirror integrator by diode connecting of cross-connected load PMOS transistors (M55 and M66) as illustrated in Fig. 6. By this technique, the input resistance becomes:

$$R_{\mathit{in}}\approx \frac{1}{g_{\mathit{mN}}}||\frac{1}{g_{\mathit{mP}}}\approx \frac{1}{2g_m}$$ (11)

Fig. 6.

The proposed integrator schematics.

This is equal to the half of input resistance of traditional cascade current mirror integrators. This approach generates a fast signal path and increases the integrating bandwidth through several GHz which is completely appropriate for high speed and low power applications.

DAC

The DAC has a return-to-zero (RZ) structure which results preventing from large errors in consequence of continuously injection of the current. A monobit DAC is employed for ideal linearity (Fig. 7). The switching transistors (Mdf1, Mdf4 and Mdf2, Mdf3) work inversely according to the incoming differential signals from the comparator. This structure could push/pull the current into/from the integrator and produce a proper negative feedback. Nevertheless, this circuit has its own non-idealities such as spiking response and switching problems. Fortunately, these non-idealities are effectively smoothed at the input node of integrator due to low resistance path which results in negligible changes at the input node and cause no considerable effects on normal operation of the integrator and its linear work.

Fig. 7.

The accomplished return-to-zero DAC.

Comparator

The quantizer is based on positive feedback cross-coupled latch [12]. Transistors M_C7 and M_C8 perform sampling. When the input differential signals applied to the drains of M_C3 and M_C4, due to the difference between them, regeneration accomplished and the comparator rapidly converges to one of its stable Equilibria. There is a problem encountered with convergence of this type of comparators; if the difference between the input signals be not large enough, the comparator remains at its unstable equilibrium (i.e., metastable point), that is, a value between its two stable points. The smallest perturbation, which moves the state of the comparator toward of its stable Equilibria, determines the comparator resolution.

One of the most important characteristics of high speed comparators is their propagation delay that is prominent for high speed applications. Dynamical latch comparators have been experienced extensively in both voltage and current mode circuits. Although dynamical latch based comparators achieve very high speed and low propagation delays in voltage mode circuits, as low as 50 ps [14], their current mode counterparts do not exhibit good propagation delay performances [15]. Propagation delay determines the maximum clock frequency by the following rule: Max f_clock = 0.3/(propagation delay) [16].

Dynamical analysis of the latch based comparator could be instructional. As mentioned, dynamical latch is a dynamical system with three Equilibria. The stable Equilibria are related to two decision states, and the unstable one is related to resetting state which should be forced (here by the clock signal) to remain in its position (like a reverse pendulum). When that force removed, sufficiently strong perturbations or incoming signals can move the state of the system from that unstable equilibrium to one of those stable Equilibria according to the direction of applied perturbation. The required transition time for that movement is translated to propagation delay. Hence, the transient behavior of the latch is achievable by a simple one-dimensional dynamical analysis. By the analysis of the latch and considering the latch as two back-to-back coupled negative amplifiers, the below relation is achieved:

$$v_{\mathit{out}}(t)=\left({\displaystyle \prod _{i=0}^{(t/\delta t)-1}}A(t-i\delta t)\right)v_0$$ (12)

where v_out(t) is the output of each inverter at time t, A(t − iδt) is the gain of the amplifier, δt is the requiring time for inverters to response, and v₀ is the initial voltage of the amplifier. Decreasing the propagation delay demands to rapidly increasing the v_out(t), which could be done by increasing A and/or v₀ and/or decreasing δt. Increasing A and decreasing δt require more power consumption, and hence, the only remaining solution for low power applications is increasing the initial value of input voltage at input of the comparator.

Just before the starting of the regeneration, the input resistance of the comparator is equal with the half of output resistance of transistors M_C3 and M_C4. This causes the less infusing current into the comparator because the output stage of the integrator connects to this high impedance point and may not be able to push all of its current to the comparator. A current buffer circuit with low input and high output impedances could improve the performance of both integrator (by preventing the returning the current of the output stage of the integrator back to the integrator circuit and saturate its transistors) and comparator (by providing a very high output impedance which is able to steer all of its current into the comparator). Therefore, this circuit increases the initial voltage of the regenerative comparator and hence according to Eq. (12) decreases the propagation delay of the comparator. Fig. 8 illustrates the proposed comparator and its transient response. All of its Equilibria are notified in the transient analysis. It can be seen that the transient response of the comparator slows down near the unstable equilibrium. This phenomenon is as the result of a bifurcation point around the location of unstable equilibrium (like the unstable equilibrium of the reverse pendulum). Existence of that metastable point is one of the most important sources of the propagation delay in the dynamic latch based comparators. The proposed comparator exhibits about 200 ps of propagation delay for 100 nA of input signal. As mentioned, this delay is short enough for the comparator to handle as fast sampling rate as 1.5 G sample/s.

Fig. 8.

Schematic of proposed high speed current comparator.

The dominant source of offset in the latch is the dynamic offset as the result of mismatch between M_C1,2, and M_C3,4 and M_C5,6. But, input referred offset of this part is get divided by the gain of preamplifier (current to voltage convertor). The same procedure is occurred for kickback as well. In addition, M_C1,2 and M_C3,4 offsets are divided by the voltage gain of latch itself which reduce the input referred offset more.

Fig. 9 illustrates the whole modulator’s circuit. As shown, the modulator is implemented by a relatively simple circuit which is a notable characteristic of the current mode circuits.

Fig. 9.

The fully differential continuous time current mode current mirror ΣΔ modulator.

Results and discussion

The simulation results of this third order ΣΔ modulator have been executed for a sampling frequency of 400 MHz and oversampling ratio (OSR) of 10 with a signal bandwidth of 20 MHz. The voltage sources of 1.8 V (as the power supply) and 1 V (for biasing circuitry) are employed where the overall consumed power from 1.8 V power supply is about 610 μW which mentioned an ultra low power modulator.

Figs. 10 and 11 show the in-band and out-of-band power spectrum density, respectively, and show the third order noise shaping. Fig. 12 sketches the SNDR versus input signal level and denotes the maximum SNDR of 56 and dynamic range of 60.7 dB which are excellent for a third order system with monobit quantizer and that low OSR and is completely satisfy WLAN standard requirements.

Fig. 10.

Out-of-band noise shaping of the circuit of Fig. 9.

Fig. 11.

In-band noise shaping of the circuit of Fig. 9.

Fig. 12.

The dynamic range schema of the circuit of Fig. 9.

One of the traditional touchstones for comparing ΣΔMs is the consumed energy per cycle denoted as Figure of Merit (FoM). The FoM_SNDR of ΣΔMs is described as [17]:

$${\text{FoM}}_{\text{SNDR}}=\frac{\mathit{Consumed}\mathit{Power}}{2\times \text{BW}\times 2^{\mathit{ENoB}}}$$ (13)

where ENoB is the effective number of bits and calculated by:

$$\text{ENoB}=\frac{\text{SNDR}-1.76}{6.02}$$ (14)

Also, another method for calculating of FoM is proposed by Schreier and Temes [18] based on dynamic range as follows:

$${\text{FoM}}_{\text{DR}}=\text{Dynamic Range}(\text{dB})+10{\log }_{10}\left(\frac{\text{BW}}{P}\right)$$ (15)

The calculated FoM from Eq. (13) is expressed mostly on pJ. It is obvious that the less FoM, the better performance achieved for the modulator. On the other hand, the calculated FoM from Eq. (15) is in dB and its larger values are better.

Table 1 compares the performance of the proposed circuit with the literature. It can be seen that the proposed circuit has an excellent performance in the FoM point of view for both calculations.

Table 1.

Comparison between the proposed modulator with some works in the literature.

Ref.	SNDR (dB)	DR (dB)	BW (KHz)	OSR	Power (mW)	Arch.	FoMSNDR (pJ)	FoMDR (dB)
[3]	68	70	4	125	0.4	second order	24.35	140
[4]	73	75	1250	32	12.74	2-1	1.39	154.91
[5]	82	86	100	65	1.8	fourth order	0.874	163.44
[19]	65	50	5000	50	28	first order	1.926	132.51
[20]	57	62	0.4	125	0.08	second order	172.8	128.99
[21]	79	81	100	130	5	third order	3.432	154.01
[22]	60.96	74	10000	35.8	31	third order	1.698	159.08
[23]	47.7	54.3	1000	30	1	third order	2.522	144.3
This work	56	60.7	20000	10	0.914	third order	0.004	164.1

Conclusions

Third order fully differential continuous time current mode ΣΔ modulator have been designed and simulated in 0.18 μm standard CMOS technology. By decreasing the input resistance, an integrator with very wide band and proper dynamic range has been achieved. By special design and configuration of the cascade structure, the biasing circuit became very simple and reduced to just one biasing source. A very fast current comparator is proposed with the ability to work in GHz sampling rates and low power consumption. The SNDR of the proposed circuit was about 56 dB and its dynamic range was 60.7 dB for signal bandwidth of 20 MHz by OSR of 10 and sampling frequency of 400 MHz. The proposed circuit exhibits excellent FoM for two different criteria in comparison with related works.

Conflict of interest

The authors have declared no conflict of interest.