Silicon epitaxy on H-terminated Si (100) surfaces at 250 °C

Abstract

Low temperature Si epitaxy has become increasingly important due to its critical role in the encapsulation and performance of buried nanoscale dopant devices. We demonstrate epitaxial growth up to nominally 25 nm, at 250°C, with analysis at successive growth steps using STM and cross section TEM to reveal the nature and quality of the epitaxial growth. STM images indicate that growth morphology of both Si on Si and Si on H-terminated Si (H: Si) is epitaxial in nature at temperatures as low as 250 °C. For Si on Si growth at 250 °C, we show that the Si epitaxial growth front maintains a constant morphology after reaching a specific thickness threshold. Although the in-plane mobility of silicon is affected on the H: Si surface due to the presence of H atoms during initial sub-monolayer growth, STM images reveal long range order and demonstrate that growth proceeds by epitaxial island growth albeit with noticeable surface roughening.

1. Introduction

Recent advances in atomic scale patterning of phosphorus dopants on hydrogen terminated Si (100) surfaces using STM lithography have resulted in a variety of atomic scale devices, including wires^[1],[2], quantum dots^[3],[4] and single atom transistors^[5]. As the building blocks for the Si based Kane quantum computer^[6],[7],[8], most of these approaches rely on patterning a hydrogen resist layer^[9],[10] and selectively adsorbing dopant atoms in areas defined by lithographic patterns^[11],[12]. Electrical performance of these devices depends strongly on the quality of the silicon matrix surrounding the device layer. It is necessary, therefore, to embed devices in high quality crystalline Si in order to isolate atomically doped regions from surfaces and interfaces that can potentially disturb their local electronic environment as well as to fully activate the dopant atoms.

Low temperature silicon epitaxy has become widely recognized as a suitable method to suppress dopant segregation and diffusion during growth to achieve near atomic scale doped devices^[13],[14]. It has also been reported that epitaxial growth of silicon can occur at temperatures as low as room temperature^[15], and that Si film growth at room temperature up to several monolayers’ thickness has been successfully used as a locking layer to maintain ultra-sharp dopant profiles^[16]. Electrical measurements by McKibbin et al.^[17] show 100% dopant activation at 250 °C encapsulation temperatures. Furthermore, it was shown that epitaxial encapsulation above 270 °C leads to dopant segregation with no improvement in the quality of overgrowth with a notable 50 % drop in carrier concentration. These data demonstrate the acute importance of strictly limiting the thermal budget to 250 °C during silicon overgrowth in order to prevent diffusion and segregation of the incorporated phosphorous^[18],[19].

Since the temperature required for epitaxial growth (T_epi) is strongly dependent on the flux rate^[20], it is possible to lower T_epi by decreasing the flux rate. Mo et al.^[21] showed the formation of Si dimer chains at temperatures ranging from 75 °C to 227 °C with low flux rates (0.1 ML/min, ML= monolayer). Earlier studies with extremely low growth rates (0.06 ML/min) indicated ordering and epitaxy for sub-monolayer growth at 250 °C^[22]. However, these rates are too low and unsuitable for practical atomic device applications that rely Si overgrowth due to increased contamination and potential segregation. Si crystalline growth quality, purity, and dopant segregation are all critically dependent on growth rates and temperatures.

For device fabrication based on hydrogen resist lithography, a temperature of 250 °C is not sufficient to remove the hydrogen resist layer and the residual hydrogen dissociated from PH₃ precursor that influence the growth quality of the encapsulation layer. Previous studies have shown that H impurities in the chamber can lead to the breakdown of low temperature silicon epitaxy^{[14],[23],[24]}. Lagally et al.^[25] reported an increase in Si island density at 177 °C as hydrogen coverage was increased from 0 % to 8 %, and showed that this effect disappeared when the temperature was increased to above 277 °C. Nara et al.^[26] have investigated early phase growth formation of one dimensional Si islands on H: Si surface at 277 °C and 327 °C with low flux rates (0.3 ML/min). McKibbin et al.^[22] showed that the presence of a hydrogen resist layer results in an overall increase in roughness during 10 nm to 25 nm overgrowth. Although there are reports showing epitaxial overgrowth at 250 °C and more than 20 nm, a comprehensive analysis of the growth morphology from sub monolayer to a target encapsulation thickness (~ 25 nm) comparing hydrogen terminated and clean silicon surfaces provides an important understanding of the underlying growth dynamics are essential to optimization. The key emphasis of the work presented here is to demonstrate epitaxial Si growth on H: Si and Si up to nominally 25 nm thickness while strictly limiting the temperature to 250 °C. We present a systematic study using STM analysis and cross section TEM to examine the epitaxial growth from sub-monolayer coverage (0.15 ML) to 25 nm thickness at relatively higher flux rates from 0.4 ML/min to 3 ML/min with comparison to growth on bare Si (100) surfaces. These growth parameters cover an essential range where high quality epitaxy and electrical activation can be achieved in atomic scale devices while minimizing contamination and dopant segregation.

2. Experimental method

Front and backside polished p type boron doped Si (100) (thickness of 300 ± 25 μm) wafers with resistivity of 5 ~ 10 ohm-cm were used in the experiments. Samples of 4 mm × 10 mm size were diced from the wafer. The samples were cleaned using a standard piranha and RCA recipe, followed by a dip in 2 % hydrofluoric acid^[27],[28]. Afterwards, the samples were mounted on a standard Omicron sample holder^* and loaded into a UHV preparation chamber with an in situ UHV heater (base pressure 5 × 10⁻⁸ Pa). Samples were then degassed for 12 hours at 550 °C by passing current through the sample with additional radiative heating power of nominally 20 W. This was followed by flash heating at 1200 °C (2 ~ 3 times) and annealing for 2 ~ 4 hours at 1050 °C. The Si (100) surfaces were passivated at 320 °C or less by back filling H to 1.3 × 10⁻⁴ Pa for 10 min using a filament-type hydrogen cracker (W, 0.7 Ω, 2.6 A). Samples were then transferred to the STM chamber and an RHK Pan Scan STM^* was used for room temperature imaging.

An intrinsic silicon sublimation source (SUSI 40) was mounted in the preparation chamber for ultra-pure and low flux Si sublimation. The growth rate as a function of the filament current was calibrated by using a surface profilometer, atomic force microscope, ellipsometer and quartz crystal microbalance (QCM). Fig. 1(a) is a picture of the SUSI 40 showing the intrinsic Si filament arch. Fig. 1(b) compares the real flux rate measurement with specifications at the same deposition distance of 10 cm. The two curves have nearly the same slope indicating the exponential growth rate as a function of filament current. Before Si overgrowth, the sample temperature was monitored by a pyrometer with an uncertainty of ± 0.5 % in the 50 °C to 400 °C range. Combined with the calibrated QCM monitor, we were able to achieve growth control with a precision of 0.05 ML over the range from sub-monolayer to tens of nanometers.

Fig. 1.

(a) Main parts of the intrinsic Si sublimation source and (b) amorphous growth rate as a function of filament current.

3. Experimental results and discussion

3.1. Sub-monolayer Si deposition on H: Si (100) and Si (100) surfaces

Figs. 2(a) and 2(c) show 0.15 ML and 0.4 ML Si deposition on a H terminated Si (100) 2×1 surface at 250 °C with the same flux rate of 0.4 ML/min, respectively. Since the temperature of H desorption from a Si surface is nominally above 400 °C^[29], the underlying Si 2 × 1 dimer reconstruction with persistent H passivation is still clearly visible in both STM images. At 0.15 ML, Si adatoms formed clusters containing several atoms. At 0.4 ML coverage, these adatom clusters are much denser and begin to order into short dimer rows, along with a slight increase in the surface room mean square (RMS) roughness from 1.07 ± 0.11 Å to 1.56 ± 0.19 Å. The island number density calculated from STM images for 0.15 ML and 0.4 ML are estimated to be 3.5 × 10¹³/cm² and 5.0 × 10¹³/cm², respectively. This corresponds to short 1D islands with two or three dimers, consistent with Nara’s observations at 277 °C^[26]. The island number density increases with Si coverage indicating that the adatoms nucleate to form new islands rather than attach to existing islands due to the low 250 °C growth temperature^[30]. Although Lagally et al.^[25] reported Si island number densities of 2.0 × 10¹²/cm² with a H coverage of 0.08% at 250 °C, the starting H surfaces here all have 1 ML of H that is shown to result in a higher island number density. This demonstrates the influence of significant H coverage on Si island formation, consistent with the conclusions of Lagally.

Fig. 2.

Empty states STM images of (a) 0.15ML and (c) 0.4ML Si deposition on H terminated Si (100) surface at 250°C with a deposition rate of 0.4ML/min; (b) and (d) are subsequent annealing at 500°C for 10 min and H terminated at 320°C for (a) and (c), respectively.

Fig. 2(b) and Fig. 2(d) are STM images after a subsequent 500 °C anneal for 10 min for both the 0.15 ML and 0.4 ML films respectively. Upon annealing, the small clusters and short rows coalesce to form 2D islands on the Si surface. Note that the second layer of adatoms on top of the clusters in Fig. 2(c) begin to form well-ordered short dimer rows on top of the islands in Fig. 2(d). The surface morphology after 500 °C anneal agrees with the well-known island growth mode. It should also be noted that the islands in Fig. 2(d) corresponding to a coverage of 0.4 ML have more vacancies in comparison with that in Fig. 2 (b) from the 0.15 ML coverage. With the higher deposition amounts, the adatoms tend to form relatively large clusters spontaneously upon deposition [in Fig. 2(c)]. The comparison shows that the larger the cluster size, the lower the mobility which results in an increase in the vacancy density in the islands which is consistent with observations of Oberbeck et al.^[31].

Previous studies have shown the rate of desorption peak at about 470 °C^[29], and hence a 500 °C anneal for 10 min is sufficient to remove nearly all of the H atoms from the surface. However, from these data it cannot be determined whether H desorption plays a dominant role in the island growth, since the surface diffusion coefficient D is highly dependent on the substrate temperature T as follows^[32]:

$$\begin{array}{l}D=a^2{k}_S\\ k_S\propto \exp \left\{-V_S/k_{B}T\right\}\end{array}$$ (1)

where a, k_S, V_S, and k_B represent the effective hopping distance between sites, the hopping rate of an adatom, the potential energy barrier from site to site and the Boltzmann constant, respectively. Based on this theory, a 500 °C anneal not only would desorb the H atoms, but also will increase the Si adatom mobility. To better understand this dynamic, we performed controlled Si growth experiments on bare Si surfaces at 250 °C.

Fig. 3(a) shows a 0.4 ML Si deposition on bare Si (100) 2 × 1 surface at 250 °C with a flux rate of 0.4 ML/min. It is evident from this image that the Si adatoms tend to form elongated 2D island chains in the dimer row direction. The silicon atoms have enough mobility to diffuse and form these 2D island chains at this temperature. The second layer begins to form before the first layer completes, which is typical of this growth mechanism^[33]. This is direct evidence that epitaxial growth of Si on Si (100) surfaces proceeds by an island growth mechanism at this temperature and flux rate. Fig. 3(a) can be compared directly with Fig. 2(a) and 2(c) to show the effect of H on Si growth at 250 °C. It is clear from the comparison that H atoms on Si decrease the in-plane diffusion of adatoms in the sub-monolayer regime. As a supporting conclusion for the previous studies^[23],[34], this comparison directly demonstrates the role of H atoms on Si diffusion in the sub-monolayer growth regime.

Fig. 3.

Empty states STM images of (a) 0.4ML Si deposition on bare Si (100) surface at 250°C (deposition rate is 0.4ML/min) and H terminated at 140°C; (b) after annealing at 500°C for 10 min and H terminated at 320°C. The inset STM image shows a compact island formed after 500 °C annealing in another identical experiment.

Furthermore, it should also be noted that the 2D islands in Fig. 3(a) are smaller than that in Fig. 2(d), because of the reduced mobility at 250 °C. Upon annealing at 500 °C for 10 min the 2D island chains coalesce to form larger islands as shown in Fig. 3(b) with the inset STM image showing a small compact 2D island. At this temperature the adjacent island chains seen in Fig. 3(a) merge together to form larger elongated islands. A reduced anneal time for this process, rapid thermal anneal^[16],[23], has been applied as a strategy to reduce roughness and improve the overgrown surface quality while minimizing higher temperature exposure of the previous temperature sensitive phosphorus processes.

3.2. Beyond sub-monolayer Si deposition on H: Si (100) and Si (100) surfaces

Going beyond the sub-monolayer regime and investigating the growth on thicker films, Fig. 4(a) and 4(b) show 1 ML and 7 ML thick Si depositions on H: Si surfaces at 250 °C, respectively. Compared with sub-monolayer Si growth, the RMS roughness of Fig. 4(a) is reduced to 0.74 ± 0.05 Å which is the result of the post-deposition surface having more average coverage and the adjacent dimer rows having fewer voids. The adatoms on top of the first layer appear more scattered and isolated in comparison with Fig. 3(a) where adatoms form very compact and well-ordered dimer rows on top of the first layer. As the thickness is increased to 7 ML in Fig. 4(b) there is a considerable increase in RMS roughness to 1.53 ± 0.15 Å and the substrate step edges are not as well defined as in Fig. 4(a). Although the surface appears rougher with larger clusters, we still observe long range order with perpendicular dimer rows in successive layers, characteristic of an ordered silicon (2×1) reconstructed surface. Fig. 4(c) shows the topography of a 15 nm Si deposition on H: Si at 250 °C. Based on the STM image, the RMS surface roughness is 3.72 ± 0.17 Å with a large distribution of 3D islands.

Fig. 4.

Empty states STM images of (a) 1ML and (b) 7 ML Si deposition on H terminated Si (100) surface at 250°C with a deposition rate of 0.4ML/min and H termination at 250°C; (c) and (d) are STM image and cross section TEM image of a 15 nm Si deposition on H terminated Si (100) surface at 250°C with a deposition rate of 1.2ML/min.

Fig. 4(d) shows a cross section TEM image of the 15 nm Si overgrowth on H: Si surface. The region between the solid lines is the overgrown film and is nominally 15 nm. The TEM image indicates that the growth is epitaxial up to 15 nm thickness and the overgrown film has very limited defects and the growth seems to proceed with continuous atomic order. Since the STM images show rough surface topography with numerous voids and vacancies at 7 ML and 250 °C, we conclude that these vacancies are filled as the growth proceeds due to the recrystallization of the underlying material. This further supports previous arguments in the literature that most H atoms segregate with the growth front by exchange with incoming Si ad-atoms^{[14],[24],[25]}. The presence of the H atoms at the growth front increase the roughness surfaces as seen in Fig. 4(a–c). The combined STM and TEM results demonstrate that we can achieve epitaxial growth of Si on H: Si up to 15 nm thickness at 250 °C. Earlier work by Copel and Tromp^[35] reported Si epitaxy temperatures of around 200 °C on H: Si surface, achieving 20 ML (2.7nm) of Si on a surface with 1 ML H coverage. Here we will extend this work by increasing the growth rate and thickness and demonstrate epitaxy on H: Si up to 25 nm, an essential thickness for practical atomic scale device fabrication. It is essential that this encapsulation layer be crystalline in order to achieve optimum dopant activation and carrier densities. Furthermore, high quality low temperature Si overgrowth not only improves the performance of 2D patterned devices, but also plays an important role in extended applications involving 3D architectures^{[2],[36],[37]}.

In contrast, Fig. 5(a) shows the morphology of 7 ML Si growth (flux rate: 0.4 ML/min) on bare Si (100) surface at 250 °C. Dimer rows typical on the Si (100) 2 × 1 surface are observed indicating that the growth is epitaxial. Unlike the isolated 2D island growth shown in Fig. 3(b), this surface exhibits a much denser 3D island growth with long dimer rows on each successive layer rotated by 90°. An 18 nm thick deposition layer at 250 °C is shown in Fig. 5(b). The original substrate step and terrace structure is still visible in Fig. 5(b) inset demonstrating that the growth is conformal to the underlying substrate. The morphology of the 7 ML and 18 nm (Fig. 5(a) and 5(b)) at 250 °C grown films is very similar indicating that the nature of the growth in this thickness regime is nearly identical. The RMS roughness for 7 ML and 18 nm thick Si overgrowth (shown in Fig. 5(d)) are comparable at 2.88 ± 0.15 Å and 2.96 ± 0.10 Å, respectively. The data in Fig. 5(d) show that there is no trend of increase in surface roughness in this case as opposed to the case for the H: Si surfaces.

Fig. 5.

(a) Empty states STM image of 7 ML Si deposition on bare Si (100) surface at 250°C with a deposition rate of 0.4ML/min and H terminated at 140°C; (b) STM images of a 18 nm Si deposition on bare Si (100) surface at 250°C with a deposition rate of 1.2ML/min and then H terminated at 250°C; (c)cross section TEM image of an identical 15 nm Si deposition on bare Si (100) surface at 250°C with a deposition rate of 1.2 ML/min;(d) RMS roughness of Si grown on Si and H: Si at 250°C in this letter. The selected area for each RMS roughness calculation is 20 nm × 20 nm.

Fig. 5(c) shows one of several high resolution-cross section TEM images obtained from several locations studied on a 15 nm thick Si deposition on clean Si (100) at 250 °C. There is again no noticeable interface and the growth continuity supports epitaxial growth interpretation at the thicknesses studied.

For practical atomic scale device applications, growing silicon at a higher rate is preferred to minimize dopant segregation and residual contamination. To further explore this domain, we have grown 25 nm of silicon at 250°C at a growth rate of 3 ML/min. Fig. 6(a) shows STM image that clearly demonstrating long range atomic order. The island growth consists of perpendicular dimer rows between successive layers and is consistent with the starting Si (100) 2 × 1 reconstructed surface. These STM data show atomic order and confirm that the growth is epitaxial even with these higher growth rates and thicknesses. The large area scan in Fig. 6(b) shows step and terrace patterns and that the original steps are likely preserved during the overgrowth. The stability of unique step and terrace patterns during Si overgrowth is useful since local landmarks can be key to identify the location of a nanometer scale patterned area. It should also be noted that since the overgrowth process is quite sensitive to the flux rate and growth temperature, that the specific source used, such as the SUSI source used here, may have an effect on growth and morphology.

Fig. 6.

Empty state STM images showing 25 nm Si deposition on H: Si surface at 250°C with a deposition rate of 3 ML/min and 140°C H termination: (a) 50 nm × 50 nm; (b) 1 μm × 1 μm. The original step and terrace structures are still visible after 25 nm Si overgrowth on H: Si (100).

4. Conclusion

We have demonstrated clear differences in the nature of growth between a bare Si and a H: Si (100) 2 × 1 surface starting from the sub-monolayer coverages up to a thickness of nominally 25 nm. It is evident that hydrogen on the silicon substrate significantly influences the growth behavior. On a bare silicon surface the initial growth is found to be epitaxial for temperatures as low as 250 °C and the growth front continues to proceed epitaxially to a thickness of 18 nm with a nominally constant surface morphology and roughness. A key observation of this study is that although H reduces the mobility of in-plane silicon atoms and limits the quality of silicon overgrowth, epitaxial growth is still possible and sufficient for encapsulating patterned phosphorus doped devices. This study also suggests that hydrogen atoms tend to segregate vertically with the growth front by exchange with the incoming Si adatoms to achieve Si epitaxy for Si overgrowth beyond the 1 ML regime. The growth parameters studied here cover an essential range needed to achieve high quality epitaxy and electrical activation for atomic scale device fabrication while minimizing contamination and dopant segregation.