Thickness Considerations of Two-Dimensional Layered Semiconductors for Transistor Applications

Abstract

Layered two-dimensional semiconductors have attracted tremendous attention owing to their demonstrated excellent transistor switching characteristics with a large ratio of on-state to off-state current, I_on/I_off. However, the depletion-mode nature of the transistors sets a limit on the thickness of the layered semiconductor films primarily determined by a given I_on/I_off as an acceptable specification. Identifying the optimum thickness range is of significance for material synthesis and device fabrication. Here, we systematically investigate the thickness-dependent switching behavior of transistors with a wide thickness range of multilayer-MoS₂ films. A difference in I_on/I_off by several orders of magnitude is observed when the film thickness, t, approaches a critical depletion width. The decrease in I_on/I_off is exponential for t between 20 nm and 100 nm, by a factor of 10 for each additional 10 nm. For t larger than 100 nm, I_on/I_off approaches unity. Simulation using technical computer-aided tools established for silicon technology faithfully reproduces the experimentally determined scaling behavior of I_on/I_off with t. This excellent agreement confirms that multilayer-MoS₂ films can be approximated as a homogeneous semiconductor with high surface conductivity that tends to deteriorate I_on/I_off. Our findings are helpful in guiding material synthesis and designing advanced field-effect transistors based on the layered semiconductors.

The first successful demonstration of field-effect transistors (FETs) based on monolayer molybdenum disulfide (MoS₂) with appealing performance¹,² has stimulated intensive research on two-dimensional (2D) transition metal dichalcogenides (TMDs). The planar nature of these 2D semiconductor materials could potentially lead complementary metal-oxide-semiconductor (CMOS) technology to the ultimate size scaling envisioned by Moore’s law and beyond³,⁴,⁵. MoS₂, a representative layered TMD, has a satisfactory bandgap in the range of 1.3 to 1.8 eV⁶,⁷, which is advantageous over the well-studied gapless graphene with respect to the standby leakage current of its FETs⁸. The bandgap of MoS₂ is thickness-dependent and it is 1.8 eV for monolayers. As a result, transistors of both single- and multilayer-MoS₂ films have an exhibited high ratio of on-state to off-state current (I_on/I_off > 10⁶) with reasonable electron mobility¹,⁹,¹⁰,¹¹. All this makes the layered TMDs promising in fields of low-power switches/circuits¹¹,¹², nonvolatile memory devices¹³,¹⁴, ultrasensitive photodetectors¹⁵,¹⁶, etc.

In FET applications, multilayer MoS₂ with a smaller bandgap is of greater potential than the monolayer counterpart¹⁷. First, multilayer MoS₂ has a 3-fold higher density of states and conducts current along multiple channels, which can be translated to a considerably high drive current¹¹,¹⁸. Second, the interlayer screening effect leads to a higher carrier mobility¹⁹,²⁰ and better noise immunity²¹ in multilayer MoS₂. Compared to the direct-bandgap monolayer MoS₂ requiring a strict thickness control, the electronic properties of multilayer MoS₂ manifested by an indirect bandgap are relatively insensitive to layer thickness. Hence, multilayer MoS₂ is better suited for large-area and/or high-density electronics²²,²³,²⁴. However, multilayer MoS₂ and other TMD semiconductors have so far gained limited attention for their use in electronics, compared to their monolayer counterparts.

Usually, MoS₂ is an n-type semiconductor that is determined by both intrinsic and extrinsic effects, such as sulfur vacancies, impurities or other structural defects²⁵,²⁶,²⁷. Control of the electron mobility and carrier density in MoS₂ FETs can be achieved by engineering on the gate structure and dielectrics²⁸,²⁹,³⁰. In multilayer MoS₂, the gate control of the electron density in the channel is weakened with increasing MoS₂ thickness. When the MoS₂ thickness is larger than the maximum depletion width, W_max, the electrostatic gating loses control over the electrons in the excess part of the MoS₂ film beyond W_max. This situation is well known in the partially depleted silicon-on-insulator (SOI) technology. If there is no energy barrier at the source or drain terminals, the electrons in this excess MoS₂ will contribute significantly to the leakage current. The potential advantages of multilayer MoS₂ are, then, offset by a high I_off, leading to a significantly reduced I_on/I_off. Hence, identifying the optimum thickness range is of significance for material synthesis and practical device application of the 2D TMDs. For digital logic applications, I_on/I_off of at least 10³ is generally required³¹. In this work, we will use this I_on/I_off = 10³ ratio as a design criterion, especially when an optimum layer thickness is concerned for achieving high performance with acceptable I_on/I_off. In view of performance variation associated with probable non-uniformity with unintentional n-doping in the starting MoS₂ material as well as from device fabrication, this work builds on a statistical study of the key device parameters in order to gain a comprehensive understanding of the switching properties. Specifically, we investigate the thickness-dependent I_on/I_off in multilayer MoS₂ by a statistical analysis of more than 80 devices in a wide thickness range. Differences in I_on/I_off are large amounting to several orders of magnitude with increasing layer thickness. The optimum layer thickness is defined by W_max, beyond which I_on/I_off is reduced below 10³.

Results

A schematic representation of a back-gate multilayer-MoS₂ transistor used in our work is shown in Fig. 1a, whereas a typical top view photomicrograph of a fabricated device is given in Fig. 1b. Isolated MoS₂ flakes on the SiO₂/Si substrate were exfoliated from a bulk MoS₂ crystal using a conventional mechanical exfoliation technique³². The sample preparation and device fabrication are detailed in Methods. The thickness of different flakes, t, was measured by means of atomic force microscopy (AFM), as illustrated in Fig. 2. Only one channel length of 10 μm is used for all devices and it is defined by the spacing of a Cu grid shadow mask. However, the channel width that is determined by the width of the flakes varies in the range of 2–60 μm as a result of the stochastic nature of the MoS₂ exfoliation process. The source and drain metal used in our devices is 50 nm Au with a 5 nm thick Ti adhesion layer. The Ti adhesion layer that is in intimate contact with MoS₂ has a work function of ∼4.3 eV, which is very close to the conduction band edge of thin-layer MoS₂⁹,³³. Furthermore, Ti is a transition metal with its d-electron orbitals mixing favorably with the 4d states of Mo and resulting in an increase in the density of states at the Fermi level and a strong Fermi level pinning at the contact⁹,³⁴,³⁵. Therefore, this favorable interface geometry is expected to facilitate a good chemical bonding and allow for a maximized electron injection at the source/drain contacts with an increased overlap between the states at the interface.

Figure 1.

(a) Schematic representation and (b) Optical image of the field-effect transistor based on multilayer MoS₂.

Figure 2.

(a–d) AFM images of 9, 27, 60 and 103-nm thick MoS₂ films on SiO₂/Si substrate. The height profiles are measured along the dashed lines in the images.

The transfer characteristics of a multilayer-MoS₂ FET shows a typical n-type unipolar carrier transport behavior (Fig. 3a). This confirms a rather small (<0.1 eV), if not negligible, Schottky barrier height (SBH) for electrons at the Au/Ti-MoS₂ contacts (Supplementary Fig. S1). The SBH for holes is, thus, high (>1.2 eV) since the sum of electron SBH and hole SBH should approximately be equal to the energy bandgap (1.3 eV) of MoS₂ (inset in Fig. 3a). Tunneling through the Schottky barrier at the metal/MoS₂ contacts not only limits the charge injection in the device at its on-state but also plays a critical role when evaluating the device off-state in the subthreshold region of the transistor. The small electron SBH facilitates the injection of accumulated electrons at positive gate voltage, V_g, while the large hole SBH suppresses the injection of inverted holes at negative V_g. This results in the n-type unipolar behavior with a high I_on/I_off and is in stark contrast to the ambipolar conduction behavior in graphene FETs with a low I_on/I_off³². The FET with a 30-nm-thick multilayer MoS₂ in Fig. 3a operates as a depletion-mode FET with a large negative threshold voltage, V_t, and a high I_on/I_off of 10⁵. All the FETs fabricated in this work exhibit the same n-type characteristics, regardless of the thickness of the MoS₂ film in channel (Supplementary Fig. S2).

Figure 3.

(a) Transfer characteristics of a representative transistor with a 30-nm-thick MoS₂ film on a linear scale (left y-axis) and a log scale (right y-axis). The threshold voltage, V_t, is determined by the intercept on the x-axis with the regression fitted line to the linear scale characteristics. The insets represent the energy band diagrams corresponding to the applied V_g in three distinct regions: (1) at flat band, (2) below threshold, and (3) above threshold. ϕ_bn and ϕ_bp indicate electron and hole SBH, respectively. (b) Dependence of I_on and I_off on MoS₂ flake thickness. The grey dashed line serves as a guide to the eye. (c) Thickness-dependence of I_on/I_off. The red dashed line serves as a guide to the eye. Inset is the zoom in for the first 100 nm. The red solid line in the inset is a linear fit on the semi-log scale.

The depletion-mode nature of the transistors will set a limit on the thickness of the multilayer MoS₂ films primarily determined by the preset I_on/I_off = 10³ as an acceptable specification. Over 80 multilayer-MoS₂ FETs were fabricated and characterized. Their I_on and I_off versus t ranging from 6 nm to 225 nm are plotted in Fig. 3b. The minimum I_off occurring for the smallest t is limited by the noise level in the devices. A clear trend is observed for I_off; it increases rapidly with increasing t below 100 nm. Beyond t = 100 nm, I_off becomes comparable with I_on and is almost independent of layer thickness. The stochastic variation of the flake widths makes the variation of I_on with t unspecific. However, I_on/I_off is unaffected by the width variation due to the same width-dependence of I_on and I_off³⁶. In the first 20–30 nm, I_on/I_off exhibits a gradual decrease with increasing t, see Fig. 3c, likely caused by the I_off variation. This is followed by an exponential decrease in I_on/I_off with t until it approaches unity for t > 100 nm. This is better seen in the inset of Fig. 3c where the best linear fit to the logarithmic I_on/I_off versus t in the range of 20–100 nm gives

It is well known that in the monolayer 2D materials, the charge carriers are confined in the 2D planes. This confinement can result in some unique characteristics not common in 3D materials, e.g. Si. When the layer thickness is increased, the carriers can hop freely between neighboring layers and move in the whole 2D layered material³⁷. As a result, the carriers distribute fairly uniformly in the 2D material. In this aspect, multilayer-MoS₂ films can be approximated as a homogeneous semiconductor and simulated with traditional device simulators. We have therefore used a commercial simulation tool SILVACO TCAD³⁸ to numerically solve the coupled Poisson and continuity equations for the multilayer-MoS₂ FETs. Our focus here is on charge and current distributions in MoS₂. For simplicity, the electron SBH is set to 0.1 eV and the unintentional n-doping concentration, N_d, in MoS₂ is assumed to be 3.5 × 10¹⁷ cm⁻³, in order to attain identical V_t between the simulation and experiments. The doping concentration³⁹ in MoS₂ is found to vary from 10¹⁶ to 10¹⁹ cm⁻³. The other material parameters used in the simulation are shown in Supplementary Table S1¹¹,³⁹,⁴⁰. The simulated transfer characteristics of multilayer-MoS₂ FETs for various channel thicknesses (Fig. 4a) and the variation of I_on/I_off with t (Fig. 4b) are in good agreement with the experimental results. In particular, the simulated I_on/I_off shows a steep decrease with t around ~50 nm, matching very well with the data in Fig. 3c. This critical thickness is strongly correlated with W_max that is related to N_d by the following formula³⁶:

Figure 4.

(a) Simulated transfer curves of FETs with various MoS₂ thicknesses. (b) Simulated thickness-dependence of I_on/I_off.

where, k is the Boltzmann constant, T is absolute temperature, q is elementary charge, ε_s is the relative dielectric constant of multilayer MoS₂ (~11)³⁹,⁴¹, ε₀ is the vacuum permittivity, and n_i = 1.6 × 10⁸ cm⁻³ is the intrinsic carrier concentration in MoS₂ due to thermal interband excitation¹¹. The calculated W_max with the given N_d is ~60 nm. The spatial distribution of charge carriers is inhomogeneous, due to charge screening, along the depth of the multilayer-MoS₂ film. Specifically, the charge carriers in the MoS₂ layers close to the SiO₂ interface are effectively controlled by V_g. The electrostatic gate control of the carriers are weakened gradually, or even completely lost, in the MoS₂ layers further away from the SiO₂ interface on the account of charge screening.

As the device switching behavior is mainly determined by I_off, the carrier distribution at negative V_g is shown, respectively, in Fig. 5a,b for t < W_max and t > W_max. At a negative V_g, electrons are repelled from while holes are attracted to the MoS₂/SiO₂ interface. For t < W_max, electrons are depleted in the whole MoS₂ film at V_g < −25 V. Simultaneously, an inversion layer populated with holes is formed at the MoS₂/SiO₂ interface. However, when t > W_max, the carrier concentration close to the sample surface (away from the MoS₂/SiO₂ interface) remains constant independent of V_g. This is a result of charge screening effect that results in a poor electrostatic control of the electrons in the excess part of the MoS₂ film. This high and uncontrolled electron concentration in this excess MoS₂ close to the sample surface, shown in Fig. 5c, contributes to I_off. Although a hole inversion layer is formed under large negative V_g, the hole conduction current can be neglected due to a large SBH at the contact interfaces (see Fig. 5d).

Figure 5.

Carrier distribution in 50-nm (a) and 100-nm (b) MoS₂ at various V_g. (c,d) Electron and hole current distributions in a 100-nm-thick MoS₂ at V_g = −30 V.

It is established now that W_max is an important parameter determining the switching behavior of multilayer-MoS₂ FETs. When t ≪ W_max, the electrons can be fully depleted from the entire channel region under negative V_g and an excellent switching behavior with a very low leakage current prevails. Under such circumstances, I_on/I_off is rather insensitive to t, as manifested by the slowly descending I_on/I_off with t shown in Figs 3c and 4b. When t around W_max, the electrons in the excess part of the MoS₂ film cannot be fully depleted easily. An exponential decrease in I_on/I_off by about 4 orders of magnitude with t changing from 30 to 65 nm. Moreover, W_max depends on doping concentration. The stochastic doping concentration in the MoS₂ flakes can induce a variation in W_max, which in its turn results in a large spread in the switching property at ~60 nm (indicated by a circle in the inset of Fig. 3c).

Discussion

In view of its significance in device physics, design and fabrication, quantifying the transistor switching behavior as a function of the layer thickness of the 2D semiconductor materials is of vital importance. A critical parameter W_max is discussed when characterizing layered TMD semiconductors such as MoS₂ as the channel material in FETs. Both experimental and theoretical studies show W_max = 50–60 nm for the multilayer-MoS₂ FETs. At this thickness, the FETs are characterized by an acceptable I_on/I_off around 10³. If the multilayer-MoS₂ film is thinner than this W_max, an excellent switching behavior with a low leakage current and a much higher I_on/I_off (than 10³) will prevail. If the multilayer-MoS₂ film is substantially thicker than this W_max, a large leakage current will persist and the switching behavior becomes inferior. An exponential decrease in I_on/I_off is found in the 20–100 nm thickness range, by a factor of 10 for each additional 10 nm. The findings in this work are useful in guiding material synthesis and designing advanced FETs with layered TMD semiconductors. It appears that the device physics established for traditional semiconductors such as Si is applicable for the layered TMD semiconductors, as it should be.

Methods

Thin MoS₂ flakes were peeled off from bulk MoS₂ (SPI supplies) by mechanical exfoliation. They were subsequently transferred to a heavily doped p-type Si substrate with a 300-nm-thick thermally grown SiO₂. The SiO₂/Si substrate was pre-cleaned by sonication in acetone, isopropyl alcohol, and deionized water. The transferred MoS₂ flakes were identified using an optical microscope (Keyence digital microscope VHX-600). The thickness of the MoS₂ flakes was measured using AFM (Dimension 3100 with Nanoscope IIIa controller, Veeco) operated in tapping mode under ambient conditions. In order to avoid contamination from photolithography or electron-beam lithography, a 10-μm spacing copper grid was placed on top of the thin MoS₂ flakes as a shadow mask for the electrode fabrication. A bilayer stack Ti/Au of 5/50 nm thickness was then deposited by means of electron-beam evaporation as the source and drain electrodes. The heavily doped Si substrate was used as the common back gate for the fabricated MoS₂ FETs. Electrical characterization of the devices was carried out in a shielded probe station with Keithley 4200 semiconductor characterization system in ambient environments.

Additional Information

How to cite this article: Zhang, Y. et al. Thickness Considerations of Two-Dimensional Layered Semiconductors for Transistor Applications. Sci. Rep. 6, 29615; doi: 10.1038/srep29615 (2016).