Depletion-Mode GaN HEMT Q-Spoil Switches for MRI Coils

Abstract

Q-spoiling is the process of decoupling an MRI receive coil to protect the equipment and patient. Conventionally, Q-spoiling is performed using a PIN diode switch that draws significant current. In this work, a Q-spoiling technique using a depletion-mode Gallium Nitride HEMT device was developed for coil detuning at both 1.5 T and 3 T MRI. The circuits with conventional PIN diode Q-spoiling and the GaN HEMT device were implemented on surface coils. SNR was measured and compared for all surfaces coils. At both 1.5 T and 3 T, comparable SNR was achieved for all coils with the proposed technique and conventional Q-spoiling. The GaN HEMT device has significantly reduced the required power for Q-spoiling. The GaN HEMT device also provides useful safety features by detuning the coil when unpowered.

I. Introduction

Q-Spoiling is the process of decoupling and de-tuning an MRI receive coil during transmit mode to prevent induced currents that can compromise patient and equipment safety. Conventionally, Q-spoiling is performed using PIN diode switches [1], [2] which require high bias currents of 50 to 100 mA, though many other RF switch technologies exist [3]–[9]. PIN diode switches are often accompanied by passive crossed diodes [10]–[12] on the coil for additional safety. However, interest is growing in lightweight wearable arrays with optical or wireless data streaming. Present MRI receive chains can consume over 1 W per channel. A fully autonomous battery or wireless powered system will require lower power receive chains especially as the channel count of arrays rises. In addition, they must be safe for patients during unexpected power failures. Finding an alternative lower power replacement for PIN diodes would be an important first step toward realizing wearable and wireless arrays.

One possibility for the Q-spoiling switch is a field effect transistor (FET). Semiconductor technology has made great strides in high power FET devices with saturation currents exceeding several amperes while having small parasitic capacitance. Historically, Gallium Arsenide (GaA) devices [13], [14] have been commonplace as RF switches but did not have adequate power handling for use as a Q-spoiling switch. Now, Gallium Nitride (GaN) devices [15]–[18] offer the higher current, and lower on-resistance and off-capacitance requirements needed for power RF switches [19]–[29].

Though FET RF switches for MRI Q-spoiling have been proposed [30], [31], they were only recently demonstrated for 1.5 T with enhancement mode GaN (eGaN) FETs [32], [33] but these devices have a large off-capacitance (42 pF), which leads to greater circuit complexity and performance degradation at 3T. Second, enhancement-mode devices do not perform Q-spoiling when the device is unpowered, creating safety concerns during power faults. Q-spoiling has also been demonstrated using MEMs switches [34]–[38], but these devices have limited commercial availability and require additional DC-DC boost converters to reach the 70–80V control voltages. Phase-change Germanium Telluride (GeTe) switches [39], [40] are another up-and-coming technology. While promising, GeTe switches require improvements in speed, reliability, and availability.

In this work, we propose depletion-mode GaN FET Q-spoil switches, extending upon our initial efforts [41], [42]. We demonstrate 1.5 T and 3 T GaN High-Electron-Mobility Transistor (HEMT) based Q-spoiling circuits for surface coil loops using microwave power HEMT devices of three different power handling capabilities. The blocking impedances of these Q-spoiling circuits are compared with conventional PIN diode Q-spoiling circuits. SNR performance of these low power Q-spoiling surface coils is also compared with conventional PIN diode and crossed diode Q-spoiling coils. In addition, the image artifacts of the unpowered coils, mimicking power faults, are explored.

II. Q-spoiling tank

In MRI, Q-spoiling activates a parallel LC resonant tank within the receive loop using a switch in series with an inductor. This combination is then placed in parallel with a capacitor (Fig. 1). The quality factor of the LC circuit determines the blocking impedance of the tank. This blocking impedance reduces the induced current at a narrowband frequency within the receive loop during transmit, preventing Q-spoiling artifacts in images while protecting the patient and the coil components. Insufficient blocking impedance may result in significant transmit B1 distortion near the receive coil, altering the intended flip angle of the pulse sequence [43], [44]. During receive mode, the switch is off and can be modelled as a capacitor and an equivalent large parallel resistance. As long as C_off is small relative to the coil capacitor (e.g. 10×), the equivalent parallel resistance adds a minor loss to the coil resulting in a small degradation in image SNR.

Fig. 1.

Q-spoiling using PIN diode and FET switch. The FET switch is voltage actuated, and the PIN diode current actuated. The inductor and switch on-resistance limit the blocking impedance of the tank. In the off state, the parasitic off-resistance contributes small losses to the resonating coil capacitor.

The switch (PIN or FET) must support a high circulating current in the tank circuit during transmit mode. This will require RF power FET devices having high drain saturation current I_dss. By Faraday’s law, the induced EMF, and therefore induced current in the receive coil, is directly proportional to the coil area A, the B₁ pulse amplitude, and the Larmor frequency ω, as

$$V=\frac{d\left(A|B_1|e^{j\omega t}\right)}{dt}=j\omega e^{j\omega t}A|B_1|$$ (1)

$$|V|=\omega A|B_1|.$$ (2)

For example, using a loop coil of area 150 cm², and B₁ magnitude of 20 μT at 1.5 T (ω = 4×10⁸ rad/s), the loop EMF reaches 120 V. If the blocking impedance reached 5 kΩ, and tank Q were 100, the current in the main coil would only be 24 mA by Ohm’s law, but the RF current circulating in the tank is Q-multiplied yielding 2.4 A! At 3 T MRI, the tank current would double to 4.8 A for similar blocking impedances, peak B₁ and Q.

Thus, if we were to insert a FET device in a Q-spoiling circuit, it must be able to handle several Amperes of RF current. Figure 2 shows an IV curve acquired for a 25 W GaN FET device. The FET “safe operating zone” of the IV curve is the high slope region, indicating a small resistance. Outside this region, the drain current begins to saturate. The switch no longer acts like a small resistance, and the device fails to perform Q-spoiling. If the current approaches saturation, the drain-to-source voltage V_ds can now swing to large values. For a negative swing, the gate to drain diode will forward bias, and the FET gate will track the drain leading to a breakdown [45], [46] between the gate-source junction in devices with low V_gs limit. Therefore, it is important to select a device of sufficient size to avoid excursions into current saturation during the induced EMF levels from the transmit field.

Fig. 2.

Top: An induced EMF causes high current to flow through the FET switch. Middle: The FET switch must operate within a designated safe zone of its IV curve to continually function as a closed switch (low resistance). Bottom: When the voltage of the drain swings negative (V_ds), the gate (V_gs) will track the drain.

III. FET switch size for power levels

FET Q-spoiling belongs to the class of low voltage control switched LC resonant tank circuits [47], [48]. We tested three depletion-mode GaN HEMT devices from Cree: a CGHV1J025D (25 W, DC-18GHz), a CGHV60040D (40 W, DC-6GHz), and a CGHV60075D (75 W, DC-6GHz), each with its stated saturated power limit and maximum operating frequency. Table I outlines select parameters according to the data-sheets and our own measurements. These devices all supported the expected peak circulating currents of several amperes in a Q-spoil tank circuit. A larger device has higher current limit and smaller on-resistance, but also larger off-capacitance that could alter the tuned frequency of the coil. FET switches are compared by the figure-of-merit (FOM) product [23]:

$$\mathit{FOM}={\mathrm{R}}_{\text{on}}\cdot {\mathrm{C}}_{\text{off}}$$ (3)

with lower FOM being superior.

TABLE I.

Different FET devices and datasheet values for select parameters.

	EPC8004 [33]	PIN −15V, 30/100mA	CGHV1J025D (25 W)	CGHV60040D (40 W)	CGHV60075D (75 W)
Vds breakdown (V)	48	−100	100	150	150
IDSS (A)	>7.5	–	3.8	4.2	8
Ron (Ω)	0.08–0.11	0.4/0.15	0.6	0.56	0.28
Coff(Vds = 0) (pF)	42	1.9	3.1	3.5	7.05
Vto (V)	1.4	–	−3.8	−3.8	−3.8
FOM = Ron · Coff (Ω · pF)	3.36–4.62	0.76/0.29	1.86	1.96	1.974

A second concern is the device off-capacitance behavior near zero drain-to-source and gate-to-source voltage. The datasheets listed C_off for amplifier conditions of V_gs = −8 V and V_ds = 50 V, as 1.2 pF, 1.6 pF, and 3.2 pF for the 25 W, 40 W, and 75 W parts respectively. However, the capacitance at 0 V_ds is more relevant for a Q-spoil switch. The off-capacitance of each device was measured as a function of applied voltage using a network analyzer. Figure 3 shows that off-capacitance values are higher with 0 V applied across the drain and source. For V_gs = −8 V, and V_ds = 0 V, the 25 W part is approximately 3.1 pF; the 40 W FET is approximately 3.5 pF; and the 75 W FET is 7.05 pF. Based on device capacitance and the R_on ·C_off figure of merit, the depletion-mode GaN HEMT devices have better performance than the enhancement mode eGaN FETs used in [32], [33].

Fig. 3.

The drain-to-source off-capacitance for the 25 W, 40 W, and 75 W FET devices at −5V (solid) and −8V (dashed) bias.

IV. Biasing Circuitry for FET switch

The depletion mode GaN FET bias for Q-spoiling (Fig. 4) can be performed in two ways: adjust the gate voltage and fix the source voltage, or fix the gate voltage and bias the FET source. With minor modifications, both schemes were implemented using the GE Signa RX coil bias which imposes −15 V during receive mode and +5 V during transmit mode. The source-biased configuration (Fig. 4c) enables coil reception with a positive voltage and disables (Q spoils) with 0 volts which is well suited for single supply (e.g. battery) operation. However, for its demonstration in-bore, an auxilliary bias supply and BJT were inserted to act as a voltage/logic inverter. A diode is placed at the base of the BJT for protection. When a positive voltage is applied to the base, the collector voltage of the BJT goes low, leaving the FET switch on and activating Q-spoiling. When a negative voltage is applied to the base of the BJT, the collector of the BJT is pulled high to the source voltage level and creates a negative gate-to-source voltage across the FET to place the coil into receive mode.

Fig. 4.

Schematics showing (a) PIN Diode Q-spoiling (b) Cross Diode Q-Spoiling (c) Source-Controlled FET Q-spoiling (d) Gate-Controlled FET Q-spoiling

The second FET bias scheme applies RX control voltage directly to the gate of the FET (Fig. 4d). Depending on the control voltage of the scanner, one can create a voltage divider such that −5 V is applied between the FET gate and source to switch it off during receive mode. When a positive voltage is applied during transmit mode, the FET is on and Q-spoiling is activated. In fact, the gate-source diode will be slightly forward biased which could further lower the switch resistance [28]. This bias scheme is ideal for scanners that apply a negative coil bias to enable receive. Importantly, for both schemes, the FET switches would be on by default during a power or cable interruption, and Q-spoiling would occur. This provides an inherent safety benefit.

V. Materials and Methods

A. Q-spoiling schematics and coil construction

We constructed identical coils on printed circuit board (PCB) for 1.5 T and 3 T with different Q-spoiling circuits for comparison. Each coil was approximately 11 cm by 14 cm including chamfered corners, with loop areas of 146 cm². For 1.5 T, we implemented the following Q-spoil circuits: conventional active PIN diode Q-spoiling (Fig. 4a), crossed diode Q-spoiling (Fig. 4b), 25 W FET Q-spoiling with the “source-controlled configuration” (Fig. 4c) and finally 25 W, 40 W and 75 W FET Q-spoiling with the “gate-controlled configuration” (Fig. 4d). For 3 T, only the PIN scheme and gate-controlled FET biases were constructed. Since all packaged parts sold by Cree were magnetic, the parts were purchased in die form and gold wire bonded in-house onto the PCB boards (Fig. 5).

Fig. 5.

Magnified picture the 25W HEMT die (left) on our PCB fabricated coil (right).

The PIN diode Q-spoiling employed the Macom MA4P7441F-1091T (max 0.5 Ω, 0.15 Ω typ. at 100 mA) (Fig. 4a). The crossed diode passive blocking (Fig. 4b) [10]–[12] employed faster switching diodes (MADP-000235-10720T) to activate the LC tank. This passive decoupling is commonly built in as a safety precaution for most receive coils but alone is known to be susceptible to certain artifacts in MRI scans if the diodes do not turn on completely [49]. For FET bias schematic (Fig. 4c), a control voltage of 0 or +5 V is applied to the source of the HEMT device. This required the additional BJT bias circuit in front. The bias schematic of Fig. 4d uses a voltage divider with resistor values of 5 kΩ and 10 kΩ to convert the +5/−15V control voltages from the MRI scanner to +1.8/−5V at the gate of the HEMT device (the gate is slightly forward biased by a diode drop in transmit mode). Since the FET is biased on during high RF power intervals, the low drain-source impedance prevents high RF voltages at the device terminals, unless Idsat is approached. A bypass capacitor was added in the resistive divider to short high frequency signals coupling indirectly to the gate, although this increases the RC switch time constant. An additional 10 kΩ resistor was placed at the FET gate for current limiting protection and to provide dc control source isolation [50].

B. Impedance blocking measurements

For the 1.5 T coil prototypes, the blocking circuit employed a nominal 43 pF capacitor in parallel with a 130 nH inductor. The 3 T prototypes used a nominal 10 pF in parallel with 140 nH inductance. We tuned and matched our loaded coils to similar impedances and |S₁₁| quantities. We matched the loaded coils to |S₁₁| ≤ −20 dB. We maintained consistency in |S₁₁| value between coils within the same SNR comparison scan test. We then performed bench top measurement to examine the blocking impedance of the PIN diode Q-spoiling circuit as a function of DC bias current to compare with our FET coils. Using analyses from previous works [43], [44], we calculated that we need 2.3 kΩ to achieve a maximum of 5% transmit B1 perturbation with our coils at 1.5 T, and at least 4.7 kΩ to achieve a maximum of 5% distortion at 3 T. In Eqn. 4, A is the area of the coil, and f₀ is the Larmor frequency.

$$\frac{|Z_{\mathit{blocking}}|}{A\left[c{m}^2\right]}\approx \frac{1}{4}{f}_0\left[\mathit{MHz}\right]$$ (4)

The impedance blocking measurements of the PIN diode 1.5 T and 3 T Q-spoiling circuit were made in a lab bench-top setting using an HP network analyzer E5071C (Keysight Technologies, Santa Clara, CA, USA) while adjusting the PIN diode bias current from a power supply. Similar blocking impedance measurements were made with the FET Q-spoil circuits.

C. Q-measurements for 1.5 T Coils

We measured the loaded and unloaded Q values for a 1.5T coil with no switch, the PIN diode coil, and the three FET (25 W, 40 W, 75 W) coils. For the unloaded Q measurement, we applied a battery control voltage to the coil to turn the switch off, and probed the coil using an overlapped sniffer loop pair connected to the HP E5071C network analyzer. This measurement gives an understanding of the off-switch resistive loss contributions for the FET devices compared with the PIN diodes. Resistive chokes (100 kΩ) were added to decouple the impedance of the battery from affecting the Q measurement for the PIN diode coil. To perform the same measurement with the FET coils without altering the control bias voltage of the resistor divider, the receive line was opened between the FET bias resistors and the input matching capacitor. The battery voltage was then directly applied to the resistor divider. For the loaded Q measurement, we continued the same procedure while loading the coils with the phantom. The unloaded-to-loaded Q ratios were also calculated.

D. SNR comparison studies

1) FET Gate versus Source biasing at 1.5 T

The source-control bias (Fig. 4c) and gate-control bias (Fig. 4d) schemes were tested for SNR differences using the 25 W GaN FET in two coils at 1.5 T. Scans were performed using a 1.5 T GE system (GE Healthcare, Waukesha, Wisconsin, USA). The experimental surface coils were placed underneath a 26.5 cm by 20 cm by 7 cm deep Copper-Sulfate doped saline gel phantom. We performed FSE scans (TR=450 ms, TE=15 ms, BW= ±15.63 kHz, FOV= 20 cm × 20 cm, 4 echoes) for comparison. Cable traps were inserted in the BJT supply path for the source scheme to insure common mode RF did not impact SNR and tuning. These schemes ultimately yielded similar SNR, hence subsequent tests employed only the “gate-controlled” configurations.

2) FET versus Diode Q-spoiling at 1.5 T

The FET coils, built with the “gate-controlled” bias (Fig. 4d) for the 25 W, 40 W, and 75 W devices were compared to the diode Q-spoiled coils. Here we examined the impact of different blocking impedances and parasitic capacitances on the coil performance. Two different pulse sequences were performed: a gradient echo sequence (GRE) scan for 60° flip angles (TR=50 ms, TE=3.2 ms, BW= ±31.25 kHz, FOV=20 cm × 20 cm) and a fast spin echo (FSE) scan (TR=500 ms, TE=12 ms, BW= ±15.63 kHz, FOV=20 cm × 20 cm, 4 echoes) to compare SNR and artifacts. A GRE 60° demonstrates an average imaging sequence while the high-power FSE sequence tests the robustness of the FET devices in the Q-spoiled circuit and their current handling capability. We ensured that the coils and phantom were placed in identical positions.

3) Comparing FET coils at 3 T

As a final test, the FET based Q-spoiling circuits were tested on surface coils tuned to 127.7 MHz for use in a GE 3 T Scanner (GE Healthcare, Wakesha, Wisconsin, USA). This determined whether the parasitic off-capacitance of the GaN FETs degrade the performance of the coils relative to conventional Q-spoiling methods at higher fields. In addition, the larger static magnetic field will double the EMF compared to 1.5 T for similar peak B₁. A set of coils were constructed: a conventional PIN diode coil, and FET based coils with gate-controlled bias (25 W, 40 W, and 75 W) and identical coil dimensions (140 mm by 110 mm) as with the 1.5 T case. These coils were then tuned and matched to have similar loaded coil |S₁₁| return loss.

The phantom used for the scans was doped with both Nickel Chloride and Sodium Chloride and had dimensions of 15.5 cm × 15.9 cm × 37.5 cm. The single loop coils were placed underneath the phantom for SNR comparisons. We performed a GRE sequence of 60° flip angle (TR=70 ms, TE=4.0 ms, BW=±15.63 kHz, FOV=24 cm × 24 cm) and a FSE sequence (TR=500 ms, TE=10 ms, BW=±15.63 kHz, FOV=24 cm × 24 cm, 4 echoes). With each of the scan experiments, we aimed to maximize consistency in the hardware receive gain settings and phantom position between the different coils of that experiment.

E. Q-spoil Power Fault Performance

A final experiment was performed to demonstrate Q-spoiling performance in case of a power fault. A scan was performed at 1.5 T with the conventional PIN coil connected to the scanner receive port. A second unpowered coil overlapped the PIN diode coil and the coil artifacts were observed in the scan. The coil conductor and saline were separated by only 5 mm to enhance any possible artifacts. For the unpowered coil, five different coils were substituted: a coil with no Q-spoiling, a coil with conventional PIN diode Q-spoiling, a coil with cross diode Q-spoiling, and 25 W source-controlled and gate-controlled FET coils. GRE images of 60° flip angle (TR=50 ms, TE=3.2 ms, BW=±31.25 kHz, FOV=26 cm × 26 cm) were acquired.

VI. Results

A. Impedance blocking measurements

As expected, for the 1.5 T coils, higher blocking impedance was achieved with higher-power parts since larger devices have smaller on-resistance. The measured blocking impedances of the 1.5 T Q-spoiling circuits were 3.44 kΩ, 3.57 kΩ, and 4.9 kΩ for the 25 W, 40 W and 75 W FET parts respectively. These values were above the required 2.3 kΩ blocking impedance target, but are small signal values. To achieve equivalent blocking impedances of the 25 W, 40 W and 75 W parts using the PIN diode, we needed to supply 26 mA, 28 mA, and 70 mA respectively. At 100 mA, which matches the scanner coil bias, the blocking impedance reached 5.4 kΩ on the bench. At this bias, the MAP7441F-1091 PIN diode is rated at 0.5 Ω worst-case (0.15 Ω typical), and inductor Q likely limits the impedance.

For the 3 T Q-spoiling circuits, the measured blocking impedances were 5.8 kΩ, 5.9 kΩ, and 6.5 kΩ for the 25 W, 40 W, and 75 W circuits respectively, which were above the required 4.7 kΩ target. To achieve this with the PIN diode, we required 34 mA, 40 mA, and 76 mA respectively. With 100 mA bias current, the PIN diode blocking impedance reached 6.7 kΩ.

B. 1.5 T Loaded and Unloaded Coil Q measurements

The unloaded Q of the coil with no switch had the highest Q of 319. The PIN diode coil and 40 W FET switch coil had almost identical Q values greater than 290. The remaining FET switch coils had Q values greater than 260. The unloaded-to-loaded Q ratios of the different coils are all higher than 14 indicating large coupling between the coil and the samples (Table II).

TABLE II.

Unloaded and loaded Q values and ratio for a coil with no switch, the PIN diode coil, and the three FET coils.

	No Sw	PIN	25W FET	40W FET	75W FET
Qu	319	298	260	292	276
Ql	18.2	17.8	17.7	17.9	18.1
$\frac{Q_u}{Q_l}$	17.5	16.7	14.7	16.3	15.2

C. 1.5 T Scan Tests: Impedance matching and SNR

For the five different coils tested, we measured an |S₁₁| ≤ −20 dB. We ensured that the coils were placed at the same consistent location between the experiments. SNR comparisons are provided in Fig. 8 using box regions of Fig. 7. SNR quantities are averaged across two trials. In the GRE 60° sequence scans, the lower power 25 W FET, 40 W FET, and 75 W FET coils had a 0.2–0.4 dB SNR improvement over the PIN diode coil. The crossed diode coil had the same performance as the 25 W FET coil. During the FSE exams, the PIN diode and crossed diode coils had the same SNR performance and had a 0.4 dB improvement over the 25 W FET coil. The 40 W FET and 75 W FET coils had a 0.2–0.3 dB improvement over the PIN diode and crossed diode coils.

Fig. 8.

SNR results from three different scan tests. The first two scan tests are at 1.5 T, and the third scan test is at 3 T.

Fig. 7.

Top: FSE images at 1.5 T. GRE sequence images look very similar. Middle: 1.5 T FSE Images between gate-controlled and source-controlled FET coil configurations. Both bias schemes yield similar performance in image quality and quantitative SNR. Bottom: FSE images at 3 T.

D. 1.5 T Scan Tests: FET coil bias comparison

A similar SNR test compared the 25 W FET devices implementing the gate or source controlled bias. This examined whether the biasing circuit in the front of the source-controlled FET coil caused degradation in SNR performance. The coils were tuned and matched before measuring |S₁₁| = −22.2 dB and |S₁₁| = −23.4 dB for the gate-controlled and source-controlled FET configurations respectively (Fig. 7 middle row). The two trials yielded similar SNR performance to within 0.1dB, indicating both FET bias schemes provide comparable SNR performance.

E. SNR comparison tests at 3 T

The SNR results for the 3 T coils using PIN diode and 25, 40, and 75 W FETs are tabulated in Fig. 8c. The loaded coil impedances achieved |S₁₁| ≤ −20 dB in all cases. Since the field strength was now doubled, the induced EMF will be double the 1.5 T value for the same pulse width and B₁ peak. The SNR was comparable for both GRE and FSE sequences. For the GRE 60°, the PIN diode and 25 W FET coil had the same SNR performance while the 40 W FET and 75 W FET coil were 0.2–0.4 dB higher. In the FSE scans, the 25 W part, 40 W part and 75 W part had at least 0.2 dB SNR improvement over the PIN diode coil. The FET coils themselves perform similarly and only slightly better than PIN diode coil. Overall, we conclude that that there is no noticeable degradation in SNR performance when using FET switches compared with the PIN diode switching in Q-spoiling.

F. Q-spoil Power Fault Artifacts

Figure 9 shows the power fault overlay tests. When an unpowered coil overlaps a connected PIN diode coil, dark bands are generated by both the coil lacking Q-spoiling and the second disconnected PIN diode coil. On the other hand, these dark band artifacts are not present for the passive cross diode coils nor for the FET-based coils. One distinction between the passive cross diodes and the FET-based coils is that there is an inductively coupled bright sensitivity region above the cross diode coil while there is little sensitivity in the region above the FET-based coils.

Fig. 9.

A conventional PIN diode coil at 1.5 T is overlapped with an unpowered coil, chosen between a coil lacking blocking circuits, a second PIN coil, crossed-diode coil, or FET coils. Q-spoil artifacts are generated in both the coil lacking Q-spoiling and the PIN diode coil. The cross diode coil and FET coils exhibit no Q-spoiling artifacts but the cross-diode leaves the element active during receive, and the FET coils disable reception.

VII. Discussions

The results demonstrate that depletion mode GaN FET HEMT devices are comparable to PIN diode Q-spoiling methods, yielding similar SNR values while consuming almost no power. The unloaded Q of the FET coils and PIN diode coils are comparable suggesting similar off-resistance switch values and low impact on SNR. In addition, the proximity between unloaded-to-loaded Q ratios of the PIN diode and FET coils indicate similar noise floor levels. Slight variations in SNR may be due to small mismatch differences and coil placement. Differences in SNR may also arise from the finite blocking impedances and slight tuning differences of the blocking networks. The latter can cause the phase of the residual coil current to differ with potential additive or subtractive effects, altering the scan profile. Lastly, local B1 changes can have a different impact on the SNR yields of GRE and FSE sequences.

PIN diode Q-spoil circuits still achieve somewhat larger blocking impedances at 100 mA bias, but in high channel count arrays, this can lead to substantial current drive, power consumption, and parasitic B₀ distortion near the diode DC bias chokes during transmit [30]. In contrast, depletion mode HEMT devices consume negligible power and current, and avoid bias chokes for resistors, which can greatly simplify bias distribution. Crossed diodes, while passive, leave all array elements active in receive but with the potential for unreliable isolation at low flip angles [49], whereas the FET biasing is robust over a wide range of flip angles and allows individual array elements to be selectively disabled during receive.

The FET switch operates much faster than PIN diodes which may benefit receiver recovery in ultra-short TE sequences. Typical PIN diode drive circuits allow switching times of 5–20 μs in most scanners though custom modifications can switch within 350 ns [51]. GaN HEMTs have switching speeds limited by the bias network resistors and gate input capacitance. In our case, we had included an RF bypass capacitor which slowed the RC switch time constant. If eliminated, FETs can theoretically switch at speeds of hundreds of nanoseconds without much optimization. Thus, FET switches show promise in applications that require imaging samples with short signal life times.

Q-spoiled blocking impedance measurements show that the series resistance of the inductor contributes along with the switch to determine blocking impedance of our Q-spoiling circuit. For example, with the 1.5 T tank circuit, an inductor Q of 160 was measured, corresponding to a series resistance of 0.4 Ω. With the tank circuit including the 25 W FET, the tank Q of 53 was observed, which corresponds to a blocking impedance of 3.37 kΩ. This value corresponded well with our measured blocking impedance.

An inherent advantage of the depletion-mode GaN HEMT device is its passive safety and bias flexibility. Without power, the device is fully conducting leaving the coil in it’s Q-spoil state - a feature not possible with enhancement devices. Prostate coils are one example that would benefit from this function in the case of connector faults. The overlay experiments demonstrated the typical Q-spoiling artifacts of alternating flip angles near the coil conductors when the PIN diode bias is cutoff, and the complete absence of such artifacts using the cross-diode and FET blocking circuits.

The GaN HEMT devices, upon failure, typically remain in a short circuit state, leaving the coil in a detuned state. Faults would then be immediately detectable by low SNR during prescans. We observed this during initial studies when the lower power Cree CGH60015D 15 W devices underwent catastrophic failure. This further supports the appeal of GaN HEMT devices from a safety aspect.

For the FET circuit, the receive mode is activated only by applying a negative gate-to-source voltage beyond the threshold cutoff. We tested two bias variants: applying a negative control voltage to the gate or a positive control voltage to the source. Both bias schemes yielded similar SNR performance. The negative gate bias is most amenable as a drop-in replacement for PIN diodes where dual polarity bias is typically employed in scanners. The source control scheme is better suited for single polarity control and could be used to simultaneously supply power to a preamp and enable receive mode. This would be useful if battery operated arrays become feasible as a step toward wireless systems.

Microwave RF FET switches are traditionally depletion mode devices with gate equidistant between source and drain. This is required for high voltage stand-off in the off state if the FET is a shunt element. In Q-spoiling, the switch need only support the high circulating currents within the blocking circuit in its on state while the off-state (receive mode) signals are miniscule. Consequently, GaN FETs intended for microwave amplification (asymmetric gate) were usable. Twieg et al [32], [33] took the alternate approach of enhancement eGaN power-conversion devices, demonstrating functionality at 1.5 T with 10° flip angles, but their performance deteriorated at 3 T. The devices were likely too large resulting in an unnecessarily low on-resistance and high off-capacitance. Consequently a more complex switch design entailing device stacking and inductor cancellation of switch capacitance was needed. The GaN HEMT devices had about 2× better FOM, and performed well in FSE sequences at 3 T with a very simple single transistor switch arrangement. Further testing will be needed to determine if the off-capacitance is low enough for 7 T operation.

Selection of the device power/current capability is very important. Initial studies had used the Cree CGH60015D 15 W device which worked for a 60° GRE sequence but was destroyed in a FSE pulse sequence at 1.5 T. We suspect the tank circuit current had approached saturation I_dss, at which point large drain-source voltage swings began. A possible breakdown occurred on a negative swing with the gate tracking the drain voltage (Fig. 2) leading to gate-source breakdown. A corrective option is a hybrid of FET and diode, or cross diode much like a PIN-schottky limiter combination [52], [53] between drain and source to prevent these excursions, but at a cost of higher C_off. In our case, the higher power 25 – 75 W devices supported much higher saturation currents and were less likely to have a similar breakdown effect.

The cost of the FET devices approximately ranged from 40–50 USD while the PIN diode is less than 10 USD. However, we expect this to change overtime with technological advances.

A future goal is to simulate the nonlinear effects of induced voltages on the HEMT switches and assess the impact of intermodulation distortion on slice profiles near the coil. The ADS models for our specific devices provided by Cree were intended only for standard amplifier biasing and not switching applications. For instance, the p-n junction behavior between the gate and drain under the polarity reversal conditions was not taken into account. While the p-n junction of the drain and gate should result in the gate voltage being pulled down when drain voltage goes down, the model exhibited no such behavior. However, Cree has recently provided a generic FET switch model, whose parameters can be tuned to emulate any device for simulation studies. Another alternative solution would be to create a custom model (ie. based off the Curtice model [54], [55]) to more correctly mimic device behavior.

VIII. Conclusion

In this work, we prototyped, demonstrated, and compared a lower power Q-spoiling method using depletion-mode GaN HEMT devices at both 1.5 T and 3 T. The depletion-mode devices allow Q-spoiling by default, providing a useful safety feature. In addition, this method can yield large current savings and can be useful with growing interest in low-power wearable or even wireless arrays coils. These parts are easily accessible, require low control voltages, and have low off-capacitance and sufficiently low on-resistances to achieve acceptable blocking impedances.

Fig. 6.

Measured blocking impedances for the 1.5 T Q-spoiling circuits. The peaks of these plots are our measured blocking impedances. 3 T blocking impedances were measured by similar method, but their peaks shifted to 127.7 MHz.