Theoretical investigation of the noise performance of active pixel imaging arrays based on polycrystalline silicon thin film transistors

Abstract

Purpose

Active matrix flat‐panel imagers, which typically incorporate a pixelated array with one a‐Si:H thin‐film transistor (TFT) per pixel, have become ubiquitous by virtue of many advantages, including large monolithic construction, radiation tolerance, and high DQE. However, at low exposures such as those encountered in fluoroscopy, digital breast tomosynthesis and breast computed tomography, DQE is degraded due to the modest average signal generated per interacting x‐ray relative to electronic additive noise levels of ~1000 e, or greater. A promising strategy for overcoming this limitation is to introduce an amplifier into each pixel, referred to as the active pixel (AP) concept. Such circuits provide in‐pixel amplification prior to readout as well as facilitate correlated multiple sampling, enhancing signal‐to‐noise and restoring DQE at low exposures. In this study, a methodology for theoretically investigating the signal and noise performance of imaging array designs is introduced and applied to the case of AP circuits based on low‐temperature polycrystalline silicon (poly‐Si), a semiconductor suited to manufacture of large area, radiation tolerant arrays.

Methods

Computer simulations employing an analog circuit simulator and performed in the temporal domain were used to investigate signal characteristics and major sources of electronic additive noise for various pixel amplifier designs. The noise sources include photodiode shot noise and resistor thermal noise, as well as TFT thermal and flicker noise. TFT signal behavior and flicker noise were parameterized from fits to measurements performed on individual poly‐Si test TFTs. The performance of three single‐stage and three two‐stage pixel amplifier designs were investigated under conditions relevant to fluoroscopy. The study assumes a 20 × 20 cm², 150 μm pitch array operated at 30 fps and coupled to a CsI:Tl x‐ray converter. Noise simulations were performed as a function of operating conditions, including sampling mode, of the designs. The total electronic additive noise included noise contributions from each circuit component.

Results

The total noise results were found to exhibit a strong dependence on circuit design and operating conditions, with TFT flicker noise generally found to be the dominant noise contributor. For the single‐stage designs, significantly increasing the size of the source‐follower TFT substantially reduced flicker noise – with the lowest total noise found to be ~574 e [rms]. For the two‐stage designs, in addition to tuning TFT sizes and introducing a low‐pass filter, replacing a p‐type TFT with a resistor (under the assumption in the study that resistors make no flicker noise contribution) resulted in significant noise reduction – with the lowest total noise found to be ~336 e [rms].

Conclusions

A methodology based on circuit simulations which facilitates comprehensive explorations of signal and noise characteristics has been developed and applied to the case of poly‐Si AP arrays. The encouraging results suggest that the electronic additive noise of such devices can be substantially reduced through judicious circuit design, signal amplification, and multiple sampling. This methodology could be extended to explore the noise performance of arrays employing other pixel circuitry such as that for photon counting as well as other semiconductor materials such as a‐Si:H and a‐IGZO.

1. Introduction

In recent years, diagnostic and interventional x‐ray imaging has benefited from the adoption of active matrix, flat‐panel imagers (AMFPIs) by virtue of advantages such as digital, real‐time image capture and large‐area monolithic construction, as well as higher detective quantum efficiency (DQE) and improved image quality. These devices, which have become ubiquitous in many medical applications, incorporate an array of pixels typically consisting of a single amorphous silicon (a‐Si:H) thin‐film transistor (TFT) coupled to some form of pixel storage capacitor.^{1, 2} The single‐TFT‐per‐pixel architecture of these arrays allows signal generated by an overlying x‐ray converter (e.g., thallium‐activated cesium iodide [CsI:Tl] for indirect detection or amorphous selenium [a‐Se] for direct detection) to be stored in the pixel capacitor prior to readout by an external electronic acquisition system. While AMFPIs have proven to be of significant benefit to medicine, their DQE at low exposures, such as those encountered in fluoroscopy, digital breast tomosynthesis and breast computed tomography, is degraded due to the modest average signal generated per interacting x‐ray relative to electronic additive noise levels of ~1000 e, or greater.^{3, 4, 5}

To overcome this limitation, a number of strategies are being pursued, aimed mainly at enhancing signal – since significant reduction in the electronic additive noise of AMFPIs is unlikely. One strategy involves the introduction of new direct detection x‐ray converters in the form of high‐gain photoconductors offering sensitivities up to a factor of ten greater than that of a‐Se – the photoconductor of choice for current commercial AMFPI systems. Such photoconductors include HgI₂, PbI₂, and PbO.^{6, 7, 8, 9, 10, 11, 12, 13} Another strategy involves the introduction of a thin a‐Se layer between a scintillating x‐ray converter (i.e., CsI:Tl) and the pixelated array, providing avalanche multiplication for the light signal emerging from the scintillator.^{14, 15, 16}

An alternative approach for improving the ratio of signal to electronic additive noise that can be applied to both indirect and direct detection involves the introduction of an amplification circuit within each pixel, referred to as the active pixel (AP) concept. An early implementation of such in‐pixel amplification was demonstrated in image sensors based on crystalline silicon (c‐Si) CMOS technology.¹⁷ These devices, referred to as active pixel sensors (APSs), are widely used in consumer products (e.g., cameras, cell phones, and tablets) and, more recently, are being introduced into medical imaging applications.^{18, 19, 20, 21, 22, 23, 24, 25} The pixels in these devices generally incorporate a three‐transistor design which provides amplification through a source‐follower circuit and offers the advantage of multiple‐sampling readout for noise reduction²⁶ – since, unlike for AMFPI pixel designs, readout does not reset the pixel signal. Interest in this technology for medical imaging has resulted in a multitude of designs with pixel pitches ranging from 25 to 135 μm and electronic additive noise levels (referred to the input of the pixel amplifier) ranging from ~50 to 360 e [rms].^{18, 19, 20, 21, 22, 23, 24, 25} However, unlike AMFPI arrays based on a‐Si:H TFTs, c‐Si devices do not provide the very large monolithic areas or high resistance to radiation that are required for many medical applications.

In response to these constraints, exploration of in‐pixel amplification with various thin‐film semiconductor materials that support manufacture of large‐area arrays of TFT circuits has been reported. For example, investigations of three‐TFT designs based on a‐Si:H (a material that provides carrier mobilities on the order of 1 cm²/V s for electrons and 10⁻³ cm²/V s for holes – a factor of ~10³ and 10⁶ lower than those of c‐Si) have been reported.^{27, 28} Another material, amorphous indium gallium zinc oxide (a‐IGZO) which has an electron mobility on the order of 5 to 20 cm²/V s, has recently been investigated for in‐pixel amplification in the context of digital breast tomosynthesis.²⁹

Our group has been exploring a different thin‐film semiconductor for creating pixel amplifier circuits: low‐temperature polycrystalline silicon (poly‐Si) – a material that is currently used for a broad range of consumer electronics. Poly‐Si offers the advantage of relatively high carrier mobilities – on the order of 100 cm²/V s for electrons and generally half of that for holes, facilitating the design of CMOS‐type circuits with both n‐type and p‐type TFTs that are capable of faster switching speeds and higher currents than a‐Si:H or a‐IGZO TFTs. In addition, poly‐Si offers the advantage of large‐area processing as well as a relatively high level of radiation damage resistance.³⁰ A number of prototype arrays based on poly‐Si have been previously developed, fabricated, and investigated under diagnostic imaging conditions.^{31, 32} The prototypes, referred to as PSI‐1, PSI‐2, and PSI‐3, incorporate pixel designs comprising one, three, and five TFTs respectively. In particular, PSI‐2 and PSI‐3 offer single‐stage amplification (with a source‐follower circuit similar to that of APS designs) and two‐stage amplification respectively. Both prototypes empirically demonstrated signal gain and, in the case of PSI‐3, an electronic additive noise level of ~560 e [rms], referred to the input.³¹ While this represents an encouraging result, it is of interest to explore the sources of additive noise for such arrays and to what extent they can be reduced through alternative pixel amplifier designs as well as through tuning of operational conditions. Toward this goal, a methodology for theoretically investigating poly‐Si circuit performance through simulation has been developed, employing parameterizations of empirically‐determined signal and noise characteristics from individual poly‐Si TFTs. (The use of theoretical modeling to explore optimization of noise performance of CMOS and a‐Si:H AP circuits through simulation has previously been reported.^{33, 34}) The methodology can be used to obtain signal and noise estimates for large‐area imagers, taking into account the noise contributions from flicker, thermal and shot noise in the array circuits. In this article, this methodology is introduced and employed to investigate the signal and noise performance of a number of AP array designs currently under development, which build upon the experience gained from the earlier PSI‐2 and PSI‐3 prototypes.

2. Methods

2.A. Description of simulated array circuits

In this study, the signal and noise performance of array circuits corresponding to hypothetical AP imagers employing indirect detection and operated fluoroscopically was investigated through detailed circuit simulations. The simulations focused on the operation of a single pixel in a manner so as to make the results representative of the performance of a large‐area imager – by incorporating assumptions about array size, readout geometry, and data line capacitance discussed below, along with timing considerations discussed in Section 2.B. For each simulation, the value of the pixel input signal, Q_RAD, was set based on the assumption of 2.24 × 10⁸ e per mm² of detector area per mR of x‐ray exposure. This value was derived from empirical measurements performed on a Hamamatsu 600 HL CsI:Tl converter with carbon backing (Hamamatsu, Japan) using a 72 kVp x‐ray spectrum (RQA5 in IEC 1267).

For each imager, the array was assumed to comprise a matrix of 1334 × 1334 pixels with a pixel‐to‐pixel pitch of 150 μm, resulting in a 20 × 20 cm² detection area. The pixel was assumed to incorporate a continuous a‐Si:H photodiode structure³² with a 100% optical fill factor, resulting in an input signal (Q_RAD) of 5.04 × 10⁶ e per pixel per mR of x‐ray exposure. Moreover, dual‐sided readout of the arrays was assumed by virtue of each data line being divided in two – so that the external acquisition electronics at each end of each data line only need to read out 667 pixels per frame.

In the study, three single‐stage pixel amplifier designs (referred to as SSPA‐1, SSPA‐2, and SSPA‐3) and three two‐stage pixel amplifier designs (referred to as TSPA‐1, TSPA‐2, and TSPA‐3) were investigated – all compatible with a pitch of 150 μm. The general form of the array circuits simulated in the study for imagers incorporating arrays with single‐stage and with two‐stage pixel amplifier designs is illustrated in Figs. 1(a) and 1(b) respectively. The single‐stage designs all consist of a source‐follower amplifier (formed by the TFT_SF transistor) that is connected to the data line by means of an addressing switch (TFT_ADDR). The effect of the continuous photodiode on a pixel is represented by a pixel storage capacitor (C_PD) with an assumed capacitance of 1.5 pF. The capacitor is reset by the TFT_RST transistor. In addition to those circuit elements, the two‐stage designs also include a common source amplifier stage. For TSPA‐1 and TSPA‐2, the common source amplifier stage is formed by the TFT_CSA transistor, an active load transistor TFT_AL and a feedback capacitor C_FB. In addition, TSPA‐2 incorporates a low‐pass filter in the form of R_LP and C_LP . TSPA‐3 is the same as TSPA‐2, other than TFT_AL being replaced by a resistor, R_LOAD (not shown in the figure). For both the single‐stage and two‐stage designs, each half data line has a readout transistor TFT_RO and a data line capacitance, represented by C_DATA, of 29 pF (assuming a capacitance per unit length of 0.29 pF/mm ³⁵). Table 1 contains a summary of the specifications of the transistors, capacitors, and resistors present in the investigated designs. Finally, the various current sources, voltages, and control signals shown in the figure are described in Sections 2.B and 2.C.

Figure 1.

Schematic diagram for the array circuits simulated in this study, including both the general form of the pixel amplifier designs considered (within the dotted region), as well as circuitry located outside the pixel but on the array substrate (between the dotted and dashed regions) and external acquisition electronics located beyond the substrate (outside the dashed region). Circuits corresponding to (a) a single‐stage pixel amplifier and (b) a two‐stage pixel amplifier. In the case of the two‐stage amplifier, the part of the circuit drawn in gray differs among the designs. The circle symbols represent various current sources in the simulation model and the probe symbols indicate nodes of particular interest. See text for further details.

Table 1.

Specifications of the components of the various array circuits simulated in this study. The types and names of the pixel amplifier designs in those circuits are indicated at the top of the table. For the transistors, the dimensions of the width and length (W/L) are given, while for the capacitors and resistors, the values of capacitance and resistance are given. All the TFTs in the table are n‐type, with the exception of the p‐type transistors used for TFT_AL. Note that, while the component specifications for the single‐stage SSPA‐1 design and two‐stage TSPA‐1 design correspond to those of the pixels of the PSI‐2 and PSI‐3 arrays, respectively,³¹ the simulated circuitry on the array substrate outside of the pixel is different

		Single‐stage			Two‐stage
		SSPA‐1	SSPA‐2	SSPA‐3	TSPA‐1	TSPA‐2	TSPA‐3
TFTRST	(μm/μm)	8/10	6/15	6/15	8/10	6/15	6/15
TFTAL	(μm/μm)				10/30	20/60
RLOAD	(MΩ)						0.3 to 104
TFTCSA	(μm/μm)				437/10	259/9	259/9
CFB	(fF)				350	100	100
RLP	(MΩ)					300	300
CLP	(fF)					400	400
TFTSF	(μm/μm)	30/10	60/5	400/10	30/10	30/10	60/10
TFTADDR	(μm/μm)	8/10	30/10	30/10	8/10	30/10	30/10
TFTRO	(μm/μm)	50/10	50/10	50/10	50/10	50/10	50/10

2.B. Operating conditions, timing, and sampling in the simulations

For a given array circuit, a number of signals and voltages are input to the simulations, as indicated in Fig. 1: (i) input signal current generated in the photodiode corresponding to the x‐ray exposure, I_RAD; (ii) external control signals RESET, ADDRESS, and READ applied to the gate of each of the TFT_RST, TFT_ADDR, and TFT_RO transistors, respectively, switching between −2.5 V in the off state and 15 V in the on state; (iii) a pixel supply voltage, V_CC, set to 8 V; and (iv) an external operational amplifier reference voltage, V_REF, set to 0.5 V. In addition, a reset voltage, V_RST (for single‐stage designs), or an active load bias voltage or load resistance, V_AL or R_LOAD (for two‐stage designs), were varied simulation‐by‐simulation so as to identify optimum settings for every array circuit.

During a given simulation run, voltages calculated at various nodes (which appear next to the probe symbols in Fig. 1) include: V_PIX – the voltage representing the signal currently residing in the pixel; V_DATA – the voltage at the data line which “follows” the value of V_PIX after turning on the addressing signal ADDRESS; and V_OPOUT – the voltage at the output of the external preamplifier. The product of the feedback capacitance of the external preamplifier and the value of V_OPOUT (at the moment immediately after turning off READ) represents the amplified pixel signal in units of charge – hereafter referred to as a sample. Note that the external preamplifier is reset after each sample.

In each simulation, x‐ray exposure was modeled as a 1 ms long current pulse of I_RAD (where I_RAD = Q_RAD/1 ms). The effect of correlated multiple‐sampling readout of the pixel signal before and after each x‐ray pulse was examined for sampling modes of 1‐1, 2‐2, 4‐4, and 8‐8 before‐after samples. The average of the before samples subtracted from the average of the after samples is referred to as Q_CMS and represents the pixel signal after application of correlated, multiple‐sampling. The array circuits were operated at 30 frames per second (fps) – with ~0.33 ms reserved for pixel reset and 33 ms reserved for irradiation and readout per frame.

The timing diagram for selected signals generated during the simulations (i.e., I_RAD, RESET, V_PIX, ADDRESS, V_DATA, READ, and V_OPOUT) are illustrated in Fig. 2 for the case of the 2‐2 sampling mode. For V_PIX, V_DATA, and V_OPOUT, the dashed and solid waveforms correspond to operation of single‐stage and two‐stage designs respectively. The figure illustrates the ~0.33 ms pixel reset time and the 33 ms irradiation + multiple‐sampling readout time. These 33 milliseconds are comprised of the 16 ms available for acquiring all before‐exposure samples, the 1 ms exclusively reserved for the x‐ray exposure and the 16 ms for all after‐exposure samples. For the 2‐2 sampling mode, this provides 8 ms for acquisition of each sample for all 667 pixels per half data line, corresponding to ~12 μs for the simulated pixel. These 12 microseconds are comprised of an 11 μs ADDRESS on‐time and ~1 μs for charge integration on the external preamplifier. The general shape of the waveforms and most of the timing shown in Fig. 2 also apply to the other three sampling modes (i.e., 1‐1, 4‐4, 8‐8), except for the following. For modes 1‐1, 4‐4, and 8‐8, the time available for acquisition of each sample is 16, 4, and 2 ms, resulting in ADDRESS on‐times of 23, 5, and 2 μs respectively.

Figure 2.

Timing diagram of selected signal waveforms associated with the single‐stage and two‐stage pixel amplifier designs considered in this study. The vertical dashed and dotted lines delineate various operational phases, brief descriptions of which appear along the top of the figure. In addition, the vertical dashed lines denote the start and finish of one complete image frame – with part of the next frame also visible in the drawing. See Fig. 1 for the position of the corresponding signals in the circuit and see text for definitional and timing information for each signal.

2.C. Methodology for simulation of signal and noise

The array circuit simulations employed the Eldo SPICE circuit simulator (Release AMS11.2, Mentor Graphics, Wilsonville, OR, USA) in combination with version 2 of the RPI poly‐Si thin‐film transistor device model.³⁶ The model employs parameters to characterize the behavior of poly‐Si TFTs, with default values provided in the published model. In this study, in order to allow the simulations to reflect the signal performance of actual poly‐Si prototype devices under development by our group, the model was adjusted by replacing a subset of the default parameter values with values derived from output and transfer characteristics measured from individual, isolated poly‐Si test TFTs. These measurements were performed with source‐meter units (Keithley model 2636A).

Noise associated with each TFT, resistor and photodiode in a simulated circuit was accounted for through use of expressions for current noise power spectral density, S _i . For TFTs, the following Equations for spectral density were used to account for: (1) flicker noise, S _if; (2) thermal noise in strong and weak inversion (i.e., white noise associated with all operating regimes of the TFT), S _iw ; and (3) thermal noise in strong inversion (i.e., white noise associated with only the “on‐state” of the TFT), S _iw‐on . Note that Eqs. (2) and (3) allow estimation of the contribution of what is commonly referred to as TFT shot noise³⁵ by virtue of the fact that the former equation includes that contribution while the latter does not.

$$S_{if}(f)={\left(\frac{I_{ds}}{1\mathit{\mu }\mathrm{A}}\right)}^{{\mathit{\beta }}_f}{K}_f\frac{g_m^2}{C_{OX}^{2}WLf}$$ (1)

$$S_{iw}(f)=4k_{b}T\times (g_m+g_{ds})\times \frac{1}{1+{\mathit{\psi }}_F}\times \left(\frac{1+a}{2}+{\mathit{\psi }}_F\times \frac{2}{3}\times \frac{1+\sqrt{a}+a}{1+\sqrt{a}}\right)$$ (2)

$$\begin{array}{cc}\hfill \text{where}:& {\mathit{\psi }}_F={\left[\text{ln}\left(1+e^{\frac{V_{dsat}}{2{\mathit{\varphi }}_t}}\right)\right]}^2,a=\frac{{\mathit{\psi }}_R}{{\mathit{\psi }}_F},\hfill \\ & {\mathit{\psi }}_R={\left[\text{ln}\left(1+e^{\frac{V_{dsat}-V_{ds}}{2{\mathit{\varphi }}_t}}\right)\right]}^2,{\mathit{\varphi }}_t=\frac{k_{b}T}{q}\hfill \end{array}$$

$$S_{iw-on}\left(f\right)=4k_{b}T\times (g_m+g_{ds})\times \frac{2}{3}\times \frac{1+\mathit{\eta }+{\mathit{\eta }}^2}{1+\mathit{\eta }}$$ (3)

$$\begin{array}{cc}\hfill \text{where}:\mathit{\eta }& =1-\frac{V_{ds}}{V_{dsat}}for{V}_{ds}\le V_{dsat}\hfill \\ & \mathit{\eta }=0for{V}_{ds}>V_{dsat}\hfill \end{array}$$

In these equations, I_ds is the drain‐source current of the transistor, g _m and g _ds are the transconductance and output conductance of the TFT, respectively, C_OX is the gate capacitance per unit area (set to 0.345 fF/μm²), W and L are the TFT width and length, f is frequency, k _b is the Boltzmann constant, T is temperature (set to 300 K), V_dsat is the saturation voltage of the TFT, V_ds is the drain‐source voltage applied to the transistor, q is the elementary charge of an electron, and β _f and K _f are parameters obtained empirically from TFT measurements. Note that the values used for I_ds, g _m , g _ds , V_dsat, and V_ds vary during the simulations, depending upon the operating conditions of the TFT. Equation (1) corresponds to the McWhorter formula for carrier number fluctuations (Eq. 7.5.30 of reference ³⁷) – modified by inclusion of the factor ${\left(\frac{I_{ds}}{1\mathit{\mu }A}\right)}^{{\mathit{\beta }}_f}$ to help account for the observed behavior of spectral densities measured from the test TFTs. Equation (2) corresponds to Eq. 7.5.28 of reference ³⁷ – adapted to match the noise model in weak and strong inversion implemented as “THMLEV=2” in the Eldo simulator. Equation (3) corresponds to Eq. 7.5.21 of reference ³⁷ – adapted to match the noise model in strong inversion implemented as “THMLEV=1” in the Eldo simulator.

For each resistor and photodiode, the following expressions for spectral density were used to account for thermal noise associated with the current through the resistor, and shot noise associated with the leakage current of the photodiode, respectively:

$$S_{ires}\left(f\right)=\frac{4k_{b}T}{R}$$ (4)

$$S_{ileak}\left(f\right)=2q{I}_{leak}$$ (5)

where R is the resistance of the resistor and I_leak is the photodiode leakage current based on the assumption of 1 pA/mm².^{32, 38} Equations (4) and (5) correspond to Eqs. 7.5.3b and 7.5.4, respectively, of reference ³⁷. In the study, Eq. (1) through Eq. (5) were implemented as SPICE code to run in the Eldo simulator.

In the simulations, the flicker and thermal noise for each TFT are modeled as current sources between the drain and source of the transistor, as indicated in Fig. 1. Similarly, the shot noise associated with photodiode leakage, as well as resistor thermal noise, are modeled as current sources, as also indicated in Fig. 1. Each current source produces a noise current with a spectral density, modeled up to 10 MHz, given by the corresponding equation.

In order to determine β _f and K _f , I_ds was measured from poly‐Si test TFTs under different gate‐source and drain‐source voltages (V_gs and V_ds respectively). For each TFT and each value of V_gs and V_ds, the measurements were performed for ~1 h at 4 Hz – a frequency chosen to allow adequate signal integration time for each sample to ensure sufficient accuracy at low currents. The data were detrended over an ~6 min wide sliding window to remove the influence of external effects such as slow changes in ambient temperature during the measurements. The data were also corrected for the known intrinsic voltage fluctuations of the source‐meter units used in the measurements. A Fourier transform of the corrected data was performed to calculate the current noise power spectral density, S _i . The resulting spectral densities that were well above the noise floor of the measurement setup for all frequencies (as determined by resistor‐based calibration measurements) were referred to the gate by dividing by $g_m^2$ – resulting in the equivalent gate voltage noise power spectral density, S_Vgs. For each voltage noise power spectral density, the value at 1 Hz was determined by fitting the data with a simple function of the form k/f. Finally, these values of S_Vgs at 1 Hz were plotted as a function of I_ds, and a fit of these results with an expression of the form of Eq. (1) was used to determine β _f and K _f .

In the modeling, the noise of a given array circuit was obtained by performing multiple simulations of the circuit in the time domain with different seeds for the random number generators driving the noise sources. Noise for a circuit was derived based on the standard deviation of the values of Q_CMS (defined in Section 2.B) obtained from those multiple simulations. The resulting value of noise, referred to the input signal charge from the photodiode, is denoted σ. Note that while the reported values of σ are rounded to the nearest electron, the statistical uncertainty in these results is ~8.8% – due to the limited number of simulation runs (n = 128) used to produce each reported noise value.

3. Results

3.A. Empirical determination of parameters for simulations

Empirical information used to adjust parameters in the RPI device model employed for the signal and noise simulations in the study was obtained through measurements performed on poly‐Si test TFTs. These TFTs originated from substrates containing active pixel and single photon counting prototype circuits and arrays being developed by our group in collaboration with PARC.³⁹ The performance of these transistors was representative of the good behavior exhibited by TFTs fabricated on PARC's poly‐Si fabrication line.

The measured transfer and output characteristics used to derive a subset of the parameter values in the RPI model were obtained from one n‐type TFT and one p‐type TFT. The transfer characteristics were measured at three values of V_ds (0.1, 1, and 5 V) and for V_gs values ranging from −6 to 17 V for the n‐type TFT, and at the corresponding mirrored values for the p‐type TFT. Similarly, the output characteristics were measured at three values of V_gs (4, 6, and 10 V) and for V_ds values ranging from 0 to 13 V for the n‐type TFT, and at the corresponding mirrored values for the p‐type TFT. Through an iterative process involving modification of 27 of the parameter values, a parameter set that provides the best overall fit to all the measured transfer and output characteristics was determined and the resulting model cards that were used in the study appear in Appendix I. The measured transfer characteristics, along with the corresponding simulation results obtained from the adjusted RPI model, are shown in Fig. 3(a), where only a fraction of the data points are illustrated for purposes of clarity. In general, the simulations are seen to be in reasonably good agreement with the measurements.

Figure 3.

Results obtained for an n‐type and a p‐type poly‐Si transistor, both having W/L dimensions in μm of 10/50. (a) Measurements of drain‐source current as a function of gate‐source voltage for three drain‐source voltages. The curves superimposed over the data correspond to simulation results obtained from the adjusted RPI model. (b) Empirical equivalent gate voltage noise power spectral densities obtained from the same n‐type TFT for which transfer characteristic data are shown on the left. Results are shown (after averaging, for purposes of presentation)⁴⁰ for a drain‐source voltage of 5 V at four gate‐source voltages. The straight lines are fits to the data. See text for further details.

In order to determine the parameters required for calculation of flicker noise for the TFTs [i.e., β _f and K _f in Eq. (1)], the equivalent gate voltage noise power spectral densities, S_Vgs, were extracted from I_ds measurements performed on 37 n‐type and 37 p‐type TFTs (having W/L dimensions, in μm, of: 200/15, 50/50, 50/30, 50/20, 50/15, 50/10, 50/5, 30/10, 10/50, 10/15, 10/10, and 10/5). I_ds was measured at four values of V_gs (1, 3, 5, and 10 V) and three values of V_ds (0.1, 1, and 5 V) for the n‐type TFTs, and at the corresponding mirrored values for the p‐type TFTs. Figure 3(b) shows some of the results for S_Vgs obtained from the same n‐type TFT for which transfer characteristic data are shown in Fig. 3(a). The straight lines in this plot correspond to fits of the function k/f to each spectral density and, from those fits, values for S_Vgs at 1 Hz of 3.58 × 10⁻¹⁰, 2.71 × 10⁻⁹, 4.68 × 10⁻⁹, and 1.62 × 10⁻⁸ V²/Hz were obtained for V_gs values of 1, 3, 5, and 10 V respectively.

For each of the 74 TFTs examined, the value for S_Vgs at 1 Hz was determined for the various V_gs and V_ds voltages in the same way as described above. The results, after normalizing for transistor area and compatibility with Eq. (1) (through multiplication by ${\mathrm{C}}_{\mathrm{ox}}^2\mathrm{WL}$), are shown in Fig. 4 as a function of I_ds. Normalization is seen to largely separate the n‐type and p‐type TFT results toward the bottom and top of the graph respectively. The two thick dashed lines superimposed on the figure correspond to separate fits of the n‐type and p‐type data, yielding values of 0.24 and −0.05 for β _f , and 1.38 × 10⁻²⁵ and 1.63 × 10⁻²⁴ C²/m² for K _f respectively. These parameter values were used in the noise simulations.

Figure 4.

Empirically determined results for normalized, equivalent gate voltage noise power spectral density (S_{V gs}) at 1 Hz as a function of I_ds for n‐type and p‐type TFTs (triangle and circle symbols respectively). Each point in the figure was determined from a single TFT at a particular V_gs and V_ds and, to guide the eye, each dotted line connects results obtained from the same transistor at the same V_ds. The lower and upper thick dashed lines correspond to fits of all the n‐type and all the p‐type data respectively. Finally, the sets of results connected by the thick solid lines correspond to the same TFTs for which transfer characteristic results are shown in Fig. 3(a). See text for further details.

3.B. Determination of noise for the pixel amplifier designs

Simulations were performed using the adjusted RPI model to determine the most favorable operating conditions for each of the pixel amplifier designs. These operating conditions include the value of V_RST for each single‐stage pixel amplifier design, the value of current (I_LOAD) through the load component (i.e., TFT_AL or R_LOAD) during pixel reset for each two‐stage pixel amplifier design, and the sampling mode for each design. While these determinations were performed so as to optimize the noise performance of each design, they were also constrained by the following requirements. The signal gain (defined as the ratio of the pixel signal output, Q_CMS, to the signal input to the pixel, Q_RAD) must be at least 10 – so as to ensure that external preamplifier noise, which dominates the electronic additive noise of AMFPI systems, is made negligible. In addition, the degree of linearity of the pixel response (defined as output signal as a function of incident x‐ray exposure) must be good – i.e., deviation from linearity of less than 1% up to at least the upper exposure limit of fluoroscopic operation,³ ~10 μR.

Simulation results for pixel response as a function of exposure from 0.1 to 10⁴ μR are shown in Fig. 5. Figure 5(a) shows response curves for SSPA‐1 in the case of the 2‐2 sampling mode for V_RST values ranging from 1.6 V (which is ~0.5 V above TFT threshold) up to 8.0 V (the value of the supply voltage, V_CC, assumed for this study). For each curve, the pixel initially exhibits linear behavior at lower exposures (resulting in a slope of unity in this log‐log plot) before asymptotically approaching a level of saturation that increases with increasing V_RST. (Note that the data at V_RST of 8 V starts to exhibit saturation at the highest exposure considered.) As V_RST increases, the dynamic range of the pixel response increases, allowing a wider range of exposures. From Table 2, good linearity is seen to be maintained over the exposure range of interest (i.e., up to 10 μR) for V_RST values of 1.8 V and above. The increasing height of the response curves in Fig. 5(a) is a manifestation of the fact that signal gain increases with V_RST, though at a diminishing rate – with the requirement of a minimum gain of 10 satisfied for V_RST values of 2.5 V and above, as also shown in Table 2. (Note that the reported values for signal gain approach, but do not reach, the first order approximation of 19.3 given by the ratio of C_DATA to C_PD ³¹ – mainly as a result of the complexity of the source‐follower behavior under the broad range of operating conditions explored. This observation also applies to the other single‐stage designs, as well as to the two‐stage designs for which the first order approximation for signal gain is given by the ratio of C_DATA to C_FB.³¹) These trends in the response curves are also generally observed for SSPA‐2 and SSPA‐3 as well as for the other sampling modes. From the complete set of simulations performed for the single‐stage designs, the range of values for V_RST found to satisfy the requirements on linearity and gain are summarized in Table 3.

Figure 5.

Simulation results for pixel response as a function of exposure from 0.1 to 10⁴ μR for the 2‐2 sampling mode, plotted on a log‐log scale. (a) Results for the single‐stage pixel amplifier design SSPA‐1 for various V_RST values. (b) Results for the two‐stage pixel amplifier design TSPA‐1 for various I_LOAD values. In both graphs, the dashed line superimposed on the results corresponds to a hypothetical design exhibiting a signal gain of 10. See text for details.

Table 2.

Summary of results for the degree of linearity and the signal gain for SSPA‐1 as a function of V_RST, and for TSPA‐1 as a function of I_LOAD. The results shown are for the case of the 2‐2 sampling mode and include the deviation from linearity at an exposure of 10 μR as well as the maximum exposure up to which the deviation from linearity is no greater than 1%

SSPA‐1				TSPA‐1
VRST (V)	Dev. from linearity at 10 μR (%)	Maximum exposure (μR)	Signal gain	ILOAD (nA)	Dev. from linearity at 10 μR (%)	Maximum exposure (μR)	Signal gain
1.6	1.7	6	1.2	0.3	1.8	6	25.7
1.8	1.0	10	3.6	1	1.3	8	32.9
2.0	0.6	17	6.8	3	0.8	12	40.4
2.2	0.3	29	9.7	10	0.6	17	45.8
2.5	0.1	68	12.7	30	0.4	25	50.8
3.0	0.0	215	14.8	100	0.2	43	55.0
3.5	0.0	470	15.6	300	0.1	85	56.6
4.0	0.0	711	16.1	1000	0.1	292	56.8
6.0	0.0	860	17.7	3000	0.1	265	55.8
8.0	0.0	5765	17.9	10000	0.0	276	51.1
–	–	–	–	30000	0.0	378	39.9

Table 3.

Summary of the range of V_RST (for the single‐stage designs) and I_LOAD (for the two‐stage designs) values for which good linearity and sufficient gain are maintained, as a function of sampling mode

Sampling mode	VRST (V)			ILOAD (nA)
	SSPA‐1	SSPA‐2	SSPA‐3	TSPA‐1	TSPA‐2	TSPA‐3
1‐1	2.0 – 8.0	1.6 – 8.0	1.6 – 8.0	1 – 30000	1 – 100	0.25 – 16200
2‐2	2.5 – 8.0	1.8 – 8.0	1.6 – 8.0	3 – 30000	1 – 100	0.25 – 16200
4‐4	3.0 – 8.0	1.8 – 8.0	1.8 – 8.0	10 – 30000	3 – 100	0.25 – 16200
8‐8	6.0 – 8.0	2.0 – 8.0	2.0 – 8.0	100 – 30000	3 – 300	0.25 – 16200

Pixel response as a function of exposure was simulated for TSPA‐1 for the same sampling mode and exposure range as for the SSPA‐1 results shown in Fig. 5(a). In these simulations, the I_LOAD values ranged from 0.3 nA (corresponding to sufficient current for proper operation of the circuits) up to 30000 nA (the maximum current that the common source amplifier stage can reasonably support). The resulting response curves for some of the I_LOAD values (which are representative of the entire set of results) are shown in Fig. 5(b). Compared to the saturation behavior exhibited by the single‐stage designs, most of the curves asymptotically approach a common saturation level. From Table 2, good linearity is seen to be maintained over the exposure range of interest for I_LOAD values of 3 nA and above. In addition, the signal gain is well above the requirement of 10 for all values of I_LOAD, as is apparent in both the graph and the table. More complex behaviors are observed among the other two‐stage designs and modes. From the complete set of simulations performed for the two‐stage designs, the range of values for I_LOAD found to satisfy the requirements on linearity and gain are summarized in Table 3.

For each of the single‐stage and two‐stage designs, the combination of operating conditions (i.e., the value of V_RST, the value of I_LOAD, and the sampling mode) that provided the lowest total noise was determined. (Total noise, σ _TOTAL, is defined as the quadratic sum of the flicker, thermal, and photodiode shot noise contributions.) This was accomplished by performing simulations of flicker, thermal, and photodiode shot noise using Eqs. (1), (2), and (5) respectively. For TSPA‐2 and TSPA‐3, thermal noise also includes simulation of resistor thermal noise using Eq. (4). For each of the single‐stage and two‐stage designs, these simulations were performed for each of the sampling modes as a function of V_RST and I_LOAD, respectively, over the same ranges as used to determine pixel response (see above).

The results of these simulations for the case of the 2‐2 sampling mode are shown in Fig. 6. In Fig. 6(a), for each of the three single‐stage designs, flicker and thermal noise are generally seen to increase and decrease, respectively, with increasing V_RST. In addition, flicker noise is found to be the dominant noise component throughout – with the exception of SSPA‐1 at a V_RST of 1.6 V (which is a consequence of the very low gain, ~1.2, at that operating condition). The smallest values of total noise are generally found at the lowest value of V_RST, again with the exception of SSPA‐1 at 1.6 V. However, with the requirements of good linearity and a gain of at least 10, total noise for SSPA‐1, SSPA‐2, and SSPA‐3 is found to have minimums of ~1865, 1672, and 574 e [rms] at V_RST values of 2.5, 1.8, and 1.6 V respectively.

Figure 6.

Simulation results for flicker and thermal noise contributions, as well as total noise (indicated by solid symbols, open symbols, and solid lines, respectively), for the 2‐2 sampling mode for the pixel amplifier designs simulated in this study. The photodiode shot noise contribution is relatively small (i.e., less than 72 e [rms]) and is not shown separately in this figure or in Fig. 7 for reasons of clarity. Note that the dashed lines in the figure are included to guide the eye. (a) Results for the three single‐stage designs as a function of V_RST . (b) Results for the three two‐stage designs as a function of the current through the load component (I_LOAD ) in the circuit – corresponding to TFT_AL for TSPA‐1 and TSPA‐2 and to R_LOAD for TSPA‐3.

In Fig. 6(b), for each of the three two‐stage designs, thermal noise is seen to generally decrease with increasing I_LOAD. However, flicker noise shows a more complicated behavior: decreasing then increasing with increasing I_LOAD for TSPA‐1 and TSPA‐2, while only increasing with I_LOAD for TSPA‐3. Moreover, while flicker noise is found to be the dominant noise contribution for TSPA‐1 and TSPA‐2, it becomes the dominant contribution for TSPA‐3 only at higher currents, above ~3 nA. These strongly differing behaviors lead to significant differences in the value of I_LOAD (10000, 100, and 0.74 nA) at which the total noise (~1724, 1004, and 443 e [rms]) is minimized for TSPA‐1, TSPA‐2, and TSPA‐3, respectively – after accounting for the requirements of good linearity and a gain of at least 10.

From the simulations performed as described above, the minimum total noise for each of the pixel amplifier designs was determined for each sampling mode. (For each minimum, the requirements on gain and linearity were satisfied by restricting the choice of V_RST or I_LOAD to the ranges shown in Table 3.) These minimums, along with the corresponding flicker and thermal noise contributions, are shown in Fig. 7. For the single‐stage designs (Fig. 7(a)), thermal noise decreases with increasing numbers of samples while flicker noise generally remains relatively constant or increases. For the two‐stage designs, while thermal noise remains relatively constant with increasing numbers of samples, flicker noise decreases for TSPA‐1 and TSPA‐2 (and remains almost constant for TSPA‐3).

Figure 7.

Minimum total noise, as determined through simulation, as a function of sampling mode for (a) the three single‐stage designs and (b) the three two‐stage designs. The corresponding flicker and thermal noise contributions are also shown.

Interestingly, while increasing the number of samples is generally expected to progressively decrease total noise, as is indeed observed for the two‐stage designs by virtue of averaging the signal of multiple samples,³¹ this is clearly not the case for the single‐stage designs. This is a direct consequence of the fact that increasing the number of samples necessitates decreasing the ADDRESS on‐time per sample (see Fig. 2 and associated text) – which truncates charge integration on C_DATA progressively earlier in time, well before the signal would otherwise settle. This generally increases the noise generated per sample by a source‐follower circuit operated as a large‐signal voltage amplifier.⁴¹ In the case of the single‐stage designs, this unfortunately leads to little or no net benefit from increasing the number of samples. However, for the two‐stage designs, the additional in‐pixel gain provided by the first‐stage common source amplifier reduces the effect of noise originating from the subsequent, second‐stage source‐follower circuit on the total noise.

A summary of those values in Fig. 7 that correspond to the lowest total noise for each of the pixel amplifier designs, along with the corresponding sampling mode and V_RST (or I_LOAD) value, is presented in Table 4. The table includes the values of the various noise contributions (i.e., flicker noise, thermal noise, and photodiode shot noise) whose sum in quadrature make up these lowest total noise values. The table also includes an estimate of the contribution of what is commonly referred to as TFT shot noise – obtained through comparison of simulation results performed using Eqs. (2) and (3). (Note that the total and thermal noise reported in this study include the contribution of TFT shot noise – see Section 2.C.) From the numerical information provided by the table, it is apparent that for each of the pixel amplifier designs, the lowest total noise is dominated by flicker noise, that thermal noise is (in most cases) significant, and that photodiode shot noise is negligible. Moreover, TFT shot noise is seen to represent a small, though non‐negligible, contribution to TFT thermal noise.

Table 4.

Summary of information associated with the lowest total noise values obtained in this study for each of the single‐stage and two‐stage designs. For each design, the sampling mode and values of V_RST/I_LOAD that provided these noise levels (along with the corresponding signal gain) are given. In each case, the contributions from flicker noise (σ _FLICKER), thermal noise (σ _THERMAL), and photodiode shot noise (σ _PD‐SHOT), along with their sum (σ _TOTAL), are given in units of electrons [rms]. Finally, for purposes of comparison, an estimate of the shot noise contribution from the TFTs (σ _TFT‐SHOT, which is accounted for in σ _THERMAL) is shown separately. See text for details

	Single‐stage			Two‐stage
	SSPA‐1	SSPA‐2	SSPA‐3	TSPA‐1	TSPA‐2	TSPA‐3
Sampling mode	1‐1	4‐4	2‐2	8‐8	8‐8	8‐8
VRST/ILOAD	2.0 V	1.8 V	1.6 V	10000 nA	100 nA	2.4 nA
Signal gain	10.4	10.9	11.3	28.4	70.8	98.0
σ FLICKER	1770	1526	499	1262	811	276
σ THERMAL	426	185	276	161	83	183
σ PD‐SHOT	71	62	64	60	59	60
σ TOTAL	1822	1538	574	1273	817	336
σ TFT‐SHOT	246	107	160	89	62	72

To provide further understanding of the relative performance of the various pixel amplifier designs under conditions providing the lowest total noise values shown in Table 4, the combined flicker and thermal noise contribution from each transistor and the thermal noise of each resistor is presented in Fig. 8. For the single‐stage designs, the dominance of the noise from the source‐follower TFT is apparent. In addition, the progressive reduction of the noise contribution of this component from SSPA‐1 to SSPA‐2 to SSPA‐3 is due to the increasing size of the source‐follower TFT along with the nonlinear effects of operating conditions.

Figure 8.

Combined thermal and flicker noise contributions for each TFT, or thermal noise contribution for each resistor, for (a) the three single‐stage designs and (b) the three two‐stage designs. The labels RST, CSA, SF, ADDR, and RO refer to the reset, common‐source‐amplifier, source‐follower, addressing, and readout TFTs respectively. The label LP refers to the low‐pass filter resistor (R_LP ) in TSPA‐2 and TSPA‐3 designs. While the label AL refers to the active load TFT for TSPA‐1 and TSPA‐2, it refers to the load resistor (R_LOAD ) for TSPA‐3. Results are reported for the operating conditions that provide the lowest total noise (as summarized in Table IV). Note that the symbol “×” is used to indicate that there is no R_LP component in the TSPA‐1 design.

In the case of the two‐stage designs, the situation is more complex – with significant noise contributions originating from three components (i.e., the active‐load TFT for TSPA‐1 and TSPA‐2, the common‐source‐amplifier TFT, and the source‐follower TFT), rather than just the source‐follower TFT. For TSPA‐2, significant reduction in noise compared to TSPA‐1 is observed for: (a) the common source amplifier stage comprised of TFT_AL and TFT_CSA – mainly due to the introduction of the low‐pass filter; and (b) the source‐follower stage comprised of TFT_SF and TFT_ADDR – due to increased gain provided by the common source amplifier stage which is primarily a result of the decreased size of the feedback capacitor, C_FB.³¹ For TSPA‐3, further significant reduction in noise compared to TSPA‐2 is observed for the common source amplifier stage (now comprised of R_LOAD and TFT_CSA) for the following reasons. The replacement of the p‐type active load transistor TFT_AL by the load resistor R_LOAD eliminates the large contribution of flicker noise from that transistor under the assumption employed in this study that resistors make no flicker noise contribution. (This assumption is made in the spirit of exploring lower limits on noise for two‐stage designs – as explained in the Discussion section.) This also allows operation at lower values of I_LOAD (which is the drain‐source current, I_ds) for the n‐type common source amplifier transistor, TFT_CSA, which, unlike p‐type transistors, exhibits lower flicker noise as I_ds decreases (see Fig. 4). Finally, note that reset noise, which along with external preamplifier noise is a major noise source in AMFPIs, is eliminated in both the single‐stage and two‐stage designs due to the inherent effectiveness of correlated multiple sampling. The small, remaining contribution from the reset TFT is due to thermal noise in weak inversion – associated with transistor leakage current.

4. Discussion

Analog electronic circuit simulators, such as the Eldo package used in this paper, allow modeling of circuits in either the time or frequency domain. For the methodology used in the current study, the time domain, which accounts for the dynamic behavior of a circuit including the effect of signal “history”, was chosen. This approach provides the means to examine any form of noise that affects the analog behavior of the circuit – as long as an equation that realistically describes each type of noise is provided. For active pixel circuits, the use of time domain simulations is particularly appropriate since it properly accounts for effects associated with the switching of transistors – a characteristic inherent to the operation of such circuits. The price of accurately modeling the effects of noise in the time domain is that it can be computationally expensive due to the burden of calculating the effect of noise at each time point evaluated during a given simulation run, magnified by the need to perform a sufficient number of runs to provide statistically meaningful results. In addition, the computational cost also rises as the number of components (particularly the number of transistors and resistors) increases. (In the study, the number of CPU core hours on AMD FX‐8350 cores required to perform simulations of all noise components for a given design and a given set of operating conditions ranged from ~1000 to 2000.) By comparison, frequency domain simulations are appropriate for circuits that do not generally involve the switching of transistors, since they facilitate examination of key metrics such as bandwidth and allow very computationally efficient determination of noise – such as has recently been reported in a study of amplifier circuits in photon counting array (PCA) circuits.⁴² However, even for such circuits, time domain simulations provide a means to obtain complementary signal information – such as count rate for PCA circuits.⁴³

The examination of the contribution of each type of noise from each transistor and resistor in the context of a dynamic functioning circuit provides greater insight than noise estimates obtained from equations corresponding to a static circuit.³³ Moreover, beyond helping to identify promising circuit designs (using signal and noise parameters derived from measurements performed on devices produced from a representative fabrication process), a key feature of the methodology described in this article is the ability to facilitate identification of those operating conditions that provide the best performance. In addition, while the methodology was applied to AP circuit designs based on poly‐Si and employing indirect detection of the incident radiation, it could also be extended to apply to other types of circuits (including PCA circuits) and other semiconductors (such as a‐Si:H or a‐IGZO) as well as to designs employing direct detection of the incident radiation.

The present methodology takes into account the noise contributions from flicker and thermal noise for TFTs, and shot noise for photodiodes, while considering only thermal noise for resistors. For resistors, flicker noise was not considered since its magnitude is expected to strongly depend on the resistive material, geometry, and processing details used to form such resistors.^{44, 45, 46} For that reason, the noise results for TSPA‐3 represent a lower limit. Guided by insights gained from the present study, future work will focus on identifying and characterizing the noise behavior of candidate resistors that provide the required resistance and which are compatible with the process used to fabricate poly‐Si TFT circuits – as well as extending the present formalism to account for resistor flicker noise. The methodology also considers noise from all circuit elements present in an array substrate, such as the data line capacitance and the readout TFT. Other noise sources generated by circuits outside the array substrate have not been included in the study. These include external preamplifier noise, digitization noise, and line noise – the combined effect of which can be on the order of ~1000 e. Given that the amplification gain for the various circuit designs was required to be larger than 10 in the study, such noise contributions are reduced by at least a factor of 10 and thus made negligible. For that reason, the inclusion of such noise contributions to the total noise results of Table 4 would not make a significant difference.

As indicated in Section 2.A, the pixel circuits of the SSPA‐1 and TSPA‐1 designs are based on those of arrays PSI‐2 and PSI‐3, respectively, for which empirical signal and noise characterizations have been previously reported.³¹ Unfortunately, a meaningful comparison of the present simulation results with those for PSI‐2 and PSI‐3 is not possible for a number of reasons. In particular, the processing equipment used to fabricate PSI‐2 and PSI‐3 produced poly‐Si material with very different properties from those of the poly‐Si material making up the test TFTs used in this study. In addition, individual isolated test TFTs fabricated from poly‐Si material representative of that in PSI‐2 and PSI‐3 (that would allow extraction of the signal and noise parameters required to model those arrays) were not available. Nevertheless, proper validation of the model is desirable and requires characterization of prototype arrays as well as poly‐Si test TFTs from material of comparable quality (ideally, from the same wafer), and such studies are planned.

By quantifying the noise performance of every component in the circuit design, the methodology used in this study allows identification of the noisiest components. Such information was used to demonstrate that judicious choice of TFT dimensions can significantly improve the noise performance of pixel amplifier designs. These results are encouraging and, from the insights gained in the study, it is anticipated that further tuning of these dimensions may lead to further noise reductions. The results also indicate that TFT flicker noise is generally the dominant contributor to noise. Flicker noise can be reduced by means of faster readout schemes where the time between the first sample before and the last sample after each x‐ray exposure is reduced – allowing a shorter timescale for the correlated double sampling, while maintaining 30 fps or providing even faster frame rates. (In fact, since two‐stage pixel amplifier designs are well suited for even faster readout than considered in the study, the assumption of dual‐sided array readout to relax timing constraints, which was made particularly for the single‐stage designs, is not expected to be necessary to achieve good noise performance for the two‐stage designs.) Faster readout can be achieved by means of improved poly‐Si TFT performance (most importantly, higher mobility) and/or the use of circuit configurations that allow reading more pixels during a given time interval – for example, by employing pipelined or more parallel readout schemes. Finally, flicker noise can be reduced by means of better fabrication techniques resulting in more favorable K _f and β _f values. These various strategies for noise reduction could help poly‐Si AP arrays to more closely approach the levels of noise offered by CMOS AP arrays based on c‐Si.

Conflicts of interest

The authors have no relevant conflicts of interest to disclose.

Appendix I.

I.1.

The SPICE code describing the model cards, for n‐type and p‐type TFTs, used with Eldo release AMS11.2 in this study is as follows.

n‐type	p‐type
.model n685v2e113 nmos level=62	.model p687v2e116 pmos level=62
+ version=2	+ version=2
+ asat=1.145803e+00	+ asat=7.831568e‐01
+ lasat=0	+ lasat=0
+ blk=1.746138e‐03	+ blk=1.519866e‐03
+ eb=6.529151e‐01	+ eb=6.716178e‐01
+ i0=5.098643e+01	+ i0=2.294874e+01
+ i00=1.207142e+02	+ i00=2.028552e+02
+ vfb=−1.000000e‐01	+ vfb=1.000000e‐01
+ dd=3.116488e‐07	+ dd=4.012360e‐07
+ dg=1.749308e‐07	+ dg=4.707729e‐07
+ delta=1.310906e+00	+ delta=1.394802e+00
+ eta=3.319917e+00	+ eta=4.227007e+00
+ lkink=1.645300e‐05	+ lkink=2.368401e‐06
+ mkink=1.520549e‐01	+ mkink=1.198810e+00
+ vkink=1.327739e+01	+ vkink=3.242171e+01
+ mmu=2.287253e+00	+ mmu=2.030025e+00
+ muo=1.622004e+02	+ muo=4.825824e+01
+ mu1=5.297256e‐03	+ mu1=3.154612e‐03
+ mus=7.762906e‐01	+ mus=7.607475e‐02
+ at=2.576384e‐09	+ at=3.746170e‐08
+ bt=1.030922e‐06	+ bt=1.358687e‐07
+ von=8.691350e‐01	+ von=−1.172512e‐01
+ dvt=5.379885e‐02	+ dvt=−1.080477e‐01
+ rd=5.468899e+02	+ rd=3.410033e+02
+ rs=5.468899e+02	+ rs=3.410033e+02
+ tox=1.000000e‐07	+ tox=1.000000e‐07
+ vtmod=0	+ vtmod=0
+ standmod=1	+ standmod=1
+ capmod=0	+ capmod=0
+ me=2.171500e+00	+ me=3.058928e+00
+ meta=2.618868e+00	+ meta=1.437641e‐01
+ mss=3.045161e+00	+ mss=3.213066e+00
+ vmax=1.504136e+04	+ vmax=1.212517e+05
+ theta=0	+ theta=0
+ isubmod=0	+ isubmod=0
+ lambda=1.320306e‐02	+ lambda=1.873584e‐02