Optimal Design of a Resonance-Based Voltage Boosting Rectifier for Wireless Power Transmission

Abstract

This paper presents the design procedure for a new multi-cycle resonance-based voltage boosting rectifier (MCRR) capable of delivering a desired amount of power to the load (PDL) at a designated high voltage (HV) through a loosely-coupled inductive link. This is achieved by shorting the receiver (Rx) LC-tank for several cycles to harvest and accumulate the wireless energy in the RX inductor before boosting the voltage by breaking the loop and transferring the energy to the load in a quarter cycle. By optimizing the geometries of the transmitter (Tx) and Rx coils and the number of cycles, N, for energy harvesting, through an iterative design procedure, the MCRR can achieve the highest PDL under a given set of design constraints. Governing equations in the MCRR operation are derived to identify key specifications and the design guidelines. Using an exemplary set of specs, the optimized MCRR was able to generate 20.9 V_DC across a 100 kΩ load from a 1.8 V_p, 6.78 MHz sinusoid input in the ISM-band at a Tx/Rx coil separation of 1.3 cm, power transfer efficiency (PTE) of 2.2%, and N = 9 cycles. At the same coil distance and loading, coils optimized for a conventional half-wave rectifier (CHWR) were able to reach only 13.6 V_DC from the same source.

I. Introduction

Wireless power transmission (WPT) has been utilized in a wide variety of applications from charging electric vehicles to implantable microelectronic devices (IMDs), which are currently the leading applications for WPT [1]–[4]. In WPT, high power transfer efficiency (PTE) is a key factor to reduce heat dissipation in the coils, exposure to the electromagnetic field, the size of the external energy source, and interference with nearby electronics. Several techniques have been developed to enhance the PTE, such as geometrical optimization of the coupled coils [5], implementation of closed-loop WPT systems, which control the transmitter (Tx) power or compensate for the environmental variations for better efficiency [6], [7], and resonant regulating rectifier (3R), which eliminates the need for a separate regulator by adjusting rectifier configuration [7], [8]. More recently, quality factor (Q) modulation is introduced to provide dynamic load matching in the inductive link and compensate for distance or load variations during operation [9], [10].

There are certain applications that in addition to wireless readout, are in need of high voltage (HV) for operation [11], [12]. Electrostatic microelectromechanical (MEMS) sensors and actuators, for instance, constitute an important group of devices that often require HV supplies to achieve the sensitivity or precision that they need, even though their power consumption can be quite low [13], [14]. In WPT for these cases, sufficient power delivered to the load (PDL) on the receiver (Rx) side to reach the desired supply voltage is as essential as the PTE in the design of the inductive link, if not more. In the case of energy harvesting or medical devices, sometimes increasing the Tx output power is not an option for practical, regulatory, or safety reasons because of strict limitations on the specific absorption rate (SAR) [15], [16]. If the ratio between Rx coil parasitic resistance (R₃) and the load resistance (R_L) is large, a considerable amount of the power would be dissipated in the Rx coil as opposed to being delivered to the load, and the desired voltage cannot be achieved without significantly increasing the Tx source voltage. Although several power management integrated circuit (PMIC) solutions have been proposed to achieve higher power conversion efficiency (PCE) [17]–[19] in the WPT, these systems cannot improve the PDL. Boost converters [20], [21], charge pumps [22], [23], and voltage-doubler rectifiers [18] have been implemented in the WPT system to boost the Rx received voltage by reducing the effective load resistance. These techniques can increase the output voltage on the Rx side at the cost of system complexity and large number of off-chip components, resulting in increased Rx size.

We recently introduced the multi-cycle Q-modulation technique, in which electromagnetic energy is stored in the Rx LC-tank over multiple cycles before being transferred to the load [10]. Although the presented prototype was designed to achieve high PTE using Q-modulation, the same approach can be applied to increase the PDL with a different coil optimization procedure. Multi-cycle Q-modulation in [10] was mainly focused on matching the reflected load at the Tx side to achieve the maximum PTE, while the passive full-wave rectifier simply charges the load capacitance based on the L₃C₃-tank voltage. In the proposed MCRR, however, we can control the onset of the charging time by breaking the L₃C₃-tank, and a considerably higher V_C3 can be achieved compared to the steady state amplitude of L₃C₃-tank voltage, V_C3,Peak, using the inherent voltage boosting L(di/dt) capability of L₃.

The current-mode wireless power receivers in [24] and [25] also utilize the concept of storing energy in multiple resonant cycles to achieve high voltage conversion efficiency (VCE) for extending the range of WPT and energy harvesting, respectively. Although these prototypes consider optimizing, N, the number of resonant cycles for accumulating energy, they have not optimized the inductive link for this purpose. While there have been several procedures that focus on the inductive link optimization for the PDL and/or PTE, such as [26]–[28], these procedures are applicable to conventional WPT systems, in which the coils are not switched. In this paper, we demonstrate the operating principle and design procedure for a multi-cycle resonance rectifier (MCRR) with the purpose of maximizing the PDL in a WPT system while considering the Tx/Rx coil design and optimization. We have derived the governing equations and practical limitations for MCRR, which build upon and extend the multi-cycle Q-modulation technique in [10]. In section II, the lumped model and analysis of the proposed MCRR are introduced in a 2-coil inductive link. The design considerations for the choice of diode, switch, Tx/Rx coils, and a number of resonance cycles are described in section III. The theoretical, simulation, and measurement results for a proof-of-concept MCRR with optimized coils are presented and compared in section IV, followed by concluding remarks.

II. Operating Principle of Multi-Cycle Resonance Rectifiers

Fig. 1a shows a lumped model of the proposed MCRR in a 2-coil WPT link, meant to power an electrostatic MEMS sensor-actuator system in need of high output voltage, V_out, along with its switching waveforms in Fig. 1b. It is assumed that both series Tx/Rx LC-tanks are tuned at the carrier frequency, f_p. The power amplifier (PA) on the Tx side can be modeled by a sinusoidal voltage source, V_S, and its source impedance, R_S, while the Rx loading is considered resistive and presented by a rather large R_L. Operation of the MCRR can be divided into two periods; the accumulation, T_A, and charging, T_C. During accumulation, the switch, SW, is closed to increase the Rx Q-factor and wirelessly build up/harvest energy in the L₃C₃-tank during T_A = N − ¼ cycles, which value mainly depends on the Tx/Rx LC-tank specifications and R_L. SW is opened at the onset of the charging period, T_C = ¼ cycle, when all the energy is stored in L₃, i.e. when i_L3 is at its peak and v_C3 = 0 A, causing a sharp drop in i_L3 and resulting in a large voltage appearing across L₃ due to v_L3 = L₃(di_L3/dt). This in turn results in the transfer of the stored energy in L₃C₃-tank to R_L by the L₃C₃-tank current rushing into R_L through diode D₁. After the stored energy in the L₃C₃-tank is transferred to R_L, SW closes and a new accumulation period begins.

Fig. 1.

(a) Lumped model of the proposed multi-cycle resonance rectifier for inductively-powered MEMS system and (b) its switching waveforms

Fig. 2 shows the MCRR equivalent circuits for the accumulation (Fig. 2a), onset of charging (Fig. 2b), and the rest of charging (Fig. 2c) periods. The simplified circuit for the accumulation period is shown in Fig. 3, divided into Tx and Rx equivalent circuits. To simplify the circuit analysis, we have assumed that during T_C, all the stored energy in L₃C₃-tank is transferred to R_L and the remaining energy in the L₃C₃-tank after charging periods is zero, which means the initial condition for i_L3(0) = 0 A. This is a reasonable assumption because during T_C, i_L3(t) drops much faster than typical LC-tank oscillation. Thus, D₁ is turned off when i_L3(t) drops very close to zero at the end of the charging period. Since T_C ≪ T_A, the effect of load resistance, R_L, on the reflected impedance onto the Tx side, Z_REF is negligible [10]. Therefore, Z_REF can be derived from,

$$Z_{\mathit{\text{REF}}}=\frac{{\left(w{M}_{23}\right)}^2}{R_3+R_{SW}+jw{L}_3+\frac{1}{jw{C}_3}},$$ (1)

where R_SW is the on resistance of the SW switch, M₂₃ is the mutual coupling between Tx and Rx coils, and R₃ is the parasitic resistance of L₃. The reflected voltage, V₃₂, across L₃ in the steady-state condition can be calculated from,

$$V_{32}=\frac{jw{M}_{23}{V}_S}{(R_S+\frac{1}{jw{C}_2}+R_2+jw{L}_2+Z_{\mathit{\text{REF}}})},$$ (2)

where R₂ is the parasitic resistance of L₂. Therefore, the steadystate current in the Rx loop, i_L3(t), can be derived from,

$$V_{32}\left(t\right)=L_3\frac{{\text{di}}_{\mathrm{L}3}\left(t\right)}{dt}+\frac{1}{{\mathrm{C}}_3}\int i_{L3}\left(t\right)dt+\left(R_3+R_{SW}\right)i_{L3}\left(t\right).$$ (3)

Considering that both L₂C₂ and L₃C₃ tanks are tuned at f_p, the solution for (3) in Fig. 2a can be derived as,

$$i_{L3,ac}\left(t\right)=\frac{\left|V_{32}\right|}{R_3+R_{SW}}\left(1-e^{-\frac{R_3+R_{SW}}{2L_3}t}\right)\mathit{\text{sin}}(wt+\frac{\pi }{2}).$$ (4)

At the end of T_A, t = (N−0.25)/f_p, current in L₃ reaches its peak value, i_PEAK, as shown in Fig. 1b, which can be found from (3),

$$i_{\mathit{\text{PEAK}}}=i_{L3,ac}\left(t\right){|}_{t=T_A}=\frac{\left|V_{32}\right|}{R_3+R_{SW}}\left(1-e^{-\frac{R_3+R_{SW}}{2L_3}\frac{N-0.25}{f_p}}\right),$$ (5)

where N = T_A ×f_p+0.25 is number of cycles in the accumulation period to be decided by the optimization procedure. At this time, SW opens and the charging period begins, as shown in Fig. 2b. Since one terminal of C₃ opens at the charging period, C₃ does not resonate with L₃. Since i_L3 cannot change abruptly, it decreases linearly, proportional to the voltage across L₃, while turning on D1 and charging C_L, as long as i_L3 > 0 A. The capacitor voltage, V_C3, also increases until V_C3 = V_D + V_out, where V_D is the voltage drop across D1, and i_L3(t) during the charging phase follows this linear equation,

$$i_{L3,ch}\left(t\right)=i_{\mathit{\text{PEAK}}}-\frac{\left(V_{\mathit{\text{out}}}+V_D\right)}{L_3}t.$$ (6)

When i_L3,ch(t) crosses zero, the charging stops automatically due to D₁ turning off. Hence, the charging time can be found from,

$$t_{ch}=\frac{L_3{i}_{\mathit{\text{PEAK}}}}{V_{\mathit{\text{out}}}+V_D}.$$ (7)

where V_D is the voltage drop across D1. Since in typical application V_out ≫ V_D, we can assume V_out + V_D ≈ V_out. As shown in (7), charging time is inversely proportional to V_out. Therefore, the lowest V_out requires the longest charging time. In MCRR, the minimum V_out happens when V_out is less then steady state amplitude of V_C3. When V_out is lower than V_C3,Peak, D1 in Fig. 1a is turned on regardless of SW status, resulting in V_out,min = V_C3,Peak. Since we are assuming that L₃C₃-tank is resonating, V_C3,Peak = v(L/C) × i_PEAK. Accordingly, t_ch,max = T/2π, which is less than the charging period (T_C), chosen as a quarter cycle.

Fig. 2.

Equivalent circuits of various MCRR periods in a 2-coil inductive link, (a) accumulation period, (b) the onset of charging period, and (c) the rest of charging period.

Fig. 3.

Simplified equivalent circuit for accumulation period, seen from the Tx side at resonance. The Rx side is also considered because of its effect on the transient mode calculations.

The stored energy in L₃ at the beginning of the charging period is,

$$E_{L3}=\frac{L_3}{2}{i}_{\mathit{\text{PEAK}}}^2,$$ (8)

while the energy loss due to the parasitic resistance of L₃ and D₁ during T_C can be calculated as,

$$E_{\mathit{\text{loss}}}={\displaystyle {\int }_0^{t_{ch}}{i}_{L3,ch}{\left(\mathrm{t}\right)}^2\left(R_{D1}+R_3\right)dt}=\left(R_{D1}+R_3\right){\displaystyle {\int }_0^{t_{ch}}\left(i_{\mathit{\text{PEAK}}}^2+\frac{V_{\mathit{\text{out}}}^2}{{L_3}^2}{t}^2+2i_{\mathit{\text{PEAK}}}\frac{V_{\mathit{\text{out}}}}{L_3}t\right)}dt=\left(R_{D1}+R_3\right)\frac{{i_{\mathit{\text{PEAK}}}}^3{L}_3}{3V_{\mathit{\text{out}}}},$$ (9)

where R_D1 is the ON-resistance of D₁. Since the load capacitor, C_L, is often selected large enough to minimize the ripple across the load resistance, R_L, output voltage variations, ΔV_out, during one cycle of T_A + T_C can be ignored in comparison with the rectifier output voltage, V_out. With this assumption, the energy delivered to R_L in N carrier cycles can be derived as,

$$E_{\mathit{\text{Load}}}=\frac{V_{\mathit{\text{out}}}^2}{R_L}\frac{N}{f}.$$ (10)

To turn on D₁, V_C3 should reach V_out+i_PEAKR_D1, and i_L3 should charge the parasitic capacitances of D₁ and SW, which are represented by C_PD and C_PM, respectively. When SW opens, C_PM is connected in series with C₃, and because C₃ is much larger than C_PM, the total capacitance of the series C₃-C_PM is almost equal to C_PM. The energy needed for charging C_PD and C_PM can be found from,

$$E_{CP}=\frac{C_P{\left(V_{\mathit{\text{out}}}+i_{\mathit{\text{PEAK}}}{R}_{D1}\right)}^2}{2}$$ (11)

where C_P = C_PD + C_PM. As shown in Fig. 1b, V_C3 is remained at V_out, and it drops when SW is closed. Therefore, E_CP is dissipated through SW. At the steady state, the stored energy, E_L3, should be equal to the sum of E_Load, E_loss, and E_CP,

$$E_{L3}=E_{\mathit{\text{Load}}}+E_{\mathit{\text{loss}}}+E_{CP},$$ (12)

$$\frac{L_3{i}_{\mathit{\text{PEAK}}}^2}{2}=\frac{V_{\mathit{\text{out}}}^2}{R_L}\frac{N}{f_p}+\frac{\left(R_{D1}+R_3\right)({i_{\mathit{\text{PEAK}}}}^3{L}_3)}{3V_{\mathit{\text{out}}}}+\frac{C_P\left(V_{\mathit{\text{out}}}+i_{\mathit{\text{PEAK}}}{R}_{D1}\right)2}{2}.$$ (13)

Therefore,

$$V_{\mathit{\text{out}}}^3\left(\frac{N}{R_{L}f}+\frac{C_P}{2}\right)+i_{\mathit{\text{PEAK}}}{R}_{D1}{C}_P{V}_{\mathit{\text{out}}}^2+\left({\mathrm{R}}_{D1}+R_3\right)\left(\frac{{i_{\mathit{\text{PEAK}}}}^3{L}_3}{3}\right)+\left(\frac{C_P{i}_{\mathit{\text{PEAK}}}^2{R}_{D1}^2}{2}-\frac{L_3{i_{\mathit{\text{PEAK}}}}^2}{2}\right)V_{\mathit{\text{out}}}=0,$$ (14)

and V_out can be calculated by solving (14). Consequently, P_Load = PDL can be found from ${V_{\mathit{\text{out}}}}^2/R_L$.

III. Design and Optimization of the MCRR

A. Diode and switch specs

As we mentioned in section II, parasitic capacitors of the diode and switch should be charged (E_CP) before charging of C_L, and (11) shows how much energy is dissipated when charging them. Typically, minimizing the diode or switch parasitic capacitance to reduce E_CP means using smaller device size. However, this can result in increased E_loss due to higher turn-on voltage and parasitic on-resistance for D₁ and SW, respectively. In addition, the higher on-resistance of SW, reduces E_L3 following (5) and (8). Thus, the diode and switch specs should be carefully selected considering the trade-offs between E_loss and E_CP, as well as the carrier frequency, f_p. Since the prototype MCRR in this article is designed to provide a high output voltage, V_out, in a low power application, such as electrostatic MEMS sensors and actuators, E_Load is small and can be dominated by E_CP from (11). Accordingly, the system does not require a very high i_PEAK, which leads to small E_loss, in a way that it can be dwarfed by E_CP. Therefore, we can conclude that a small-sized switch and diode with minimum C_P are more beneficial for this MCRR prototype. BAT42 (Vishay, CT) and DMN5L06K (Diodes Inc., Tx), which have relatively higher turn-on resistance and smaller parasitic capacitance, were chosen as D₁ and SW, respectively in the discrete MCRR prototype.

In an integrated circuit (IC) implementation, there are two choices for implementing D₁; a passive Schottky diode or an active diode [18]. The conduction time of D₁ is much smaller than 1/f_p, which indicates a need for rapid on/off operation of the active diode. If the active diode turns on slowly, the parasitic capacitance of D₁ and SW will be charged higher than V_out, and further increase E_CP. When the active diode turns off slowly, i_L3 will discharge C_L when it changes its direction. Therefore, strong driver circuitry for the active diode becomes an issue, considering its additional power consumption for fast operation.

B. Number of resonant cycles

E_CP and E_L3 should be considered when finding the optimal number of carrier cycles, N, that would provide the highest PDL, and consequently the highest V_out, in the proposed MCRR. As shown in Fig. 4a, the stored energy in L₃ increases according to (5) and (8) in a nonlinear fashion with respect to T_A. Fig. 4b shows the same variables in Fig. 4a, which are divided by the elapsed time, represented by the number of cycles up to that point, to show the delivered and dissipated power levels in the MCRR. If the energy accumulation period, T_A, is too short, not only the stored energy in L₃ would not be enough but also most of the harvested energy will be spent on charging the parasitic capacitors, C_PD and C_PM, resulting in low PDL. On the other hand, if T_A is too long, stored energy in L₃C₃-tank is saturated, and leads to reduction in PDL for longer periods of T_A + T_C. Therefore, optimization of N is critical for the proposed MCRR technique, and it can be found in Fig. 4a at the point where E_Load overcomes E_CP, or in Fig. 4b where P_Load reaches its peak. One can also derive V_out from (14) and differentiate it with respect to N to find its optimal value mathematically, which is highlighted in Fig. 4 by a vertical red line.

Fig. 4.

(a) Various stored or dissipated energies in the MCRR: E_L3, E_Load, E_loss, and E_CP vs. the number of resonance cycles, N. (b) Delivered and dissipated powers in the MCRR: P_L3, P_Load, P_loss, and P_CP vs. N. The optimal number of cycles, highlighted by a vetical red line, is determined by the peak of P_Load.

Although the proposed MCRR in this paper is focused on the PDL optimization, the maximum PTE is also acquired by the PDL optimization procedure when the weak coil coupling [8]. As discussed in MCRR analysis, the variation of the reflected load (Z_REF) is negligible relative to N when N has a large number. Accordingly, the input power is independent on N in this situation, and achieving the maximum PDL means the maximum PTE in the proposed MCRR.

C. Inductive link optimization

According to (14), in addition to N, the Tx and Rx coil specifications clearly affect V_out. Therefore, the inductive link can be optimized specifically based on the aforementioned MCRR operating principles to further improve the PDL. The Tx and Rx coils in this paper are considered printed spiral coil (PSC) with rounded square shape because it has 1.1 times larger mutual inductance with the same diameter [26]. Self-inductance of the rounded square shape PSC can be calculation from [29],

$$L=\frac{1.27{\mu }_0{n}^2{d}_{\mathit{\text{avg}}}}{2}\left[ln\left(\frac{2.07}{\phi }\right)+0.18\phi +0.13{\phi }^2\right]$$ (15)

$$d_{\mathit{\text{avg}}}=\frac{D_o+D_i}{2},\phi =\frac{D_o-D_i}{D_o+D_i},$$ (16)

where D_o and D_i are the outer and inner diameters of the coil. To calculate parasitic resistance of the PSC,

$$l_c=4n{D}_o-4nw-{\left(2n+1\right)}^2\left(s+w\right),$$ (17)

$$R_{dc}=\frac{{\rho }_c{l}_c}{w{t}_c},$$ (18)

$$R_{LS}=\frac{R_{dc}{t}_c}{\delta \left(1-e^{-\frac{t_c}{\delta }}\right)},\delta =\sqrt{\frac{{\rho }_c}{\pi {\mu }_0{\mu }_{r}f}},$$ (19)

where l_c is length, ρ is resistivity, t_c is thickness, w is width, s is spacing of the conductive line, δ is the skin depth μ_r is the relative permeability, and μ₀ is the permeability of space [26]. The mutual inductance, M, between two single-turn Tx and Rx coils can be found from,

$$M_{ij}=\frac{2{\mu }_0{\mu }_r}{\alpha }\sqrt{r_i{r}_j}\left[\left(1-\frac{{\alpha }^2}{2}\right)K\left(\alpha \right)-E\left(\alpha \right)\right]$$

$$\alpha =2\sqrt{\frac{r_i{r}_j}{({(r_i+r_j)}^2+D^2}}$$ (20)

where D is coils relative distance, and K and E are the complete elliptic integrals of 1^st and 2^nd kind [26]. Total mutual inductance between Tx and Rx coils can be calculated by adding every pair of single turns in the Tx and Rx coil,

$$M=g{\displaystyle {\sum }_{i=1}^{n_T}{\displaystyle {\sum }_{j=1}^{n_R}{M}_{ij}(r_i,r_j,D)}}$$ (21)

where g is a coefficient dependent on the shape. For rounded square shaped coils, g = 1.21 [26].

To optimize the coils for MCRR, an iterative design procedure is proposed in Fig. 5 with the purpose of achieving the target output voltage (V_Target) with the highest possible PDL when R_L is given. The source voltage (V_S) on the Tx side is also given an initial value and the proposed procedure finds the optimal Tx and Rx coil geometries and the N, which can achieve V_Target with the lowest possible V_S. Once V_S(min) for V_Target is determined, increasing V_S further obviously yields higher V_out and PDL, if those are desired. With respect to coil design, in most WPT applications, particularly the wirelessly-powered implantable medical devices (IMD), the Rx side is heavily size-constrained, resulting in limitation of the outer diameter of the Rx coil (D_ORx). Hence, the other coil geometrical parameters, such as the outer diameter of Tx coil (D_OTx), and inner diameters of Tx (D_iTx) and Rx coils (D_iRx) can be optimized accordingly. The number of turns for Tx and Rx coils, n_Tx and n_Rx, are calculated considering these parameters and the optimal width of the conductive traces of the Tx and Rx coils, D_wR and D_wT, respectively. Based on the coil specifications in each outer loop iteration, there is an inner loop that finds the optimal N and V_out(max) for R_L based on (14). By comparing V_out(max) and V_Target, the algorithm eventually finds the optimal geometries of the Tx and Rx coils along with their associated optimal N. The initial values; D_iTx,init, D_iRx,init, D_OTx,init, D_wT,init, and D_wR,init are determined by the fabrication limits, such as minimum design rules for PSC lithography and fabrication, and the boundaries; D_wR,lim, D_wT,lim, D_wT,lim, D_wR,lim and D_OT,lim are empirically determined to include the optimal point.

Fig. 5.

Optimization flowchart for the MCRR. D_wR,init, D_wT,init, D_iRx,init, D_iTx,init, and D_OTx,init are initial value of D_wR, D_wT, D_iRx, D_iTx, and D_OTx, respectively. D_wR,lim, D_wT,lim, and D_OTx,lim are the upper boundaries of Rx and Tx PSC line width, and Tx outer diameter, respectively.

D. MCRR-Based optimization example

Here we demonstrate an example MCRR-based optimization procedure for a target application in wirelessly powering small ultrasound transducers that can perform ultrasound imaging from inside the body [30]. Based on other electrostatic MEMS sensor specifications, we have targeted PDL of 4 mW at V_Target = 20 V, which are the equivalent of R_L = 100 kΩ, with 1.3 cm nominal Tx-Rx coil separation [14], at f_p = 6.78 MHz, in the industrial-scientific-medical (ISM) band. Running the optimization procedure in Fig. 5 with a set of design constraints and initial values that are summarized in the upper half of Table I, yields the optimized MCRR specifications that are listed in the lower half of that table. Fig. 6a shows how the Tx coil was optimized at D_oTx = 8 cm with a line width of 3.4 mm to achieve V_out = 20.6 V and PDL = 4.24 mW.

TABLE I.

Prototype MCRR Design Constraints and Specifications

Design Constraints
Outer diameter of Rx coil (DoRx)	1 cm
L2-L3 nominal distance (d23)	1.3 cm
Target load (RL)	100 kΩ
Target output voltage (VTarget)	20 V
PDL $({V_{\mathit{\text{Target}}}}^2/R_L)$	4 mW
Switch Resistance (RSW)	2 Ω
PA output resistance (RS)	3.5 Ω
Carrier frequency (fp)	6.78 MHz
Source voltage (VS)	1.8 V
Initial value of DwR and DwT	0.15 mm
Initial value of DiRx and DiTx	1 mm
Initial value of DOTx	5 mm
Optimized Rounded Square PSC Specifications
	Rx (L3)	Tx (L2) MCRR	Tx (L2) CHWR
Inductance, L (μH)	1.17	3.49	1.91
Parasitic res, R (Ω)	2.3	2.02	1
Outer diameter, DO (cm)	1	8	8
Inner diameter, Di (mm)	2	1.1	0.5
Line width, Dw (mm)	0.15	3.35	4.7
Line spacing, S (mm)	0.15	0.3	0.33
Thickness, T (μm)	35	14	14
Number of turns, n	13	9	7
Quality factor, Q	21.6	73.6	81.36
Mutual inductance (nH)	–	68.02	51.58

Fig. 6.

(a) MCRR output voltage vs. outer diameter and conductive trace width of the Tx rounded square PSC from optimization process. N and inner diameter of Tx/Rx coils were optimized for each point, V_S = 1.8 V, and R_L = 100 kΩ. Max (V_out, PDL) = (20.6 V, 4.24 mW). (b) An ideal half-wave rectifier output voltage with Tx-Rx PSCs that are optimized in a conventional fashion as in [28] with the same V_S and R_L. Max (V_out, PDL) = (13.6 V, 1.8 mW).

For the sake of comparison, we have run the conventional PSC optimization algorithm in [28] for a 2-coil inductive link, followed by a conventional half-wave rectifier (CHWR) in Fig. 7, consisting of the same Schottky diode, D1, that was used in the MCRR with turn-on voltage of V_D. The PDL was calculated in the same conditions as the MCRR (V_S = 1.8 V, and R_L = 100-kΩ) [28],

$$\mathit{\text{PDL}}=\frac{V_S^2}{2\left(R_S+R_2\right)}\frac{k_{23}^2{Q}_2{Q}_{3L}}{1+k_{23}^2{Q}_2{Q}_{3L}}\frac{Q_{3L}}{Q_L},$$ (22)

where Q₂ and Q₃ are quality factors of Tx and Rx PSCs, respectively, and Q_3L is the loaded quality factor of Rx. Considering the equivalent loading through the rectifier [31],

$$R_{\mathit{\text{Leq}}}=\frac{1}{2}{R}_L\left(\frac{V_2}{V_2-V_D}\right)$$ (23)

where V₂ is the peak voltage across C₃. Consequently, Q_3L is calculated from [28],

$$Q_{3L}=\frac{{\omega }_p{L}_3{R}_{\mathit{\text{Leq}}}}{{\omega }_p^2{L}_3^2+R_{\mathit{\text{Leq}}}{R}_3}.$$ (24)

where ω_p = 2πf_p. The output voltage can be calculated from the PDL in (22),

$$V_{\mathit{\text{out}}}=\sqrt{\mathit{\text{PDL}}\times R_L}-V_D.$$ (25)

Fig. 7.

Schematic diagram of a conventional half-wave rectifier (CHWR) with parallel LC-tank on the Rx side, which is more suitable for large R_L.

Fig. 6b shows that the output voltage in this case reaches a maximum of 13.6 V with PDL = 1.8 mW, which is far lower than that of the MCRR. It should also be noted that, as reflected in Table I, the PSCs optimized through the conventional WPT method have the same geometry on the Rx side, but different geometries on the Tx side compared to the PSCs optimized for the MCRR through Fig. 5 algorithm.

Once optimized geometries of the Tx-Rx coils are found, they are used in Fig. 8 to give further insight on how V_out varies in MCRR with respect to the changes in coil separation (d₂₃), optimal N, and R_L. As mentioned in Section III.C, N is mostly a function of the ratio between PDL and power dissipated in coils, diode, and switch parasitics. Therefore, the white curve in Fig. 8a, which indicate optimal N at every d₂₃, shows that changing the coils’ distance does not change N. On the other hand, when the load is changed from 1 kΩ to 1 MΩ in Fig. 8b, the optimal N varies significantly, from 5 cycles to 16 cycles.

Fig. 8.

Output voltage variations in the MCRR vs. (a) N and coil separation, d₂₃. (b) N and R_L. The white curves over these 3D surfaces show the optimal N.

IV. Simulation and Measurement Results

Tx and Rx PSCs were fabricated on 0.5 oz. and 1 oz. PSCs, respectively, following the optimized geometries in Table I. The MCRR prototype in Fig. 9 consists of BAT42 (Vishay, Malvern, PA) as D1 and DMN5L06K (Diodes Inc., Plano, TX) as a SW in Fig. 1a, driven by a function generator (AFG3102, Tektronix). We also used the same function generator for V_S to provide a precise constant voltage for the carrier signal regardless of the Tx coil input resistance, with an emulated source resistance of R_S = 3.5 Ω. The Tx-Rx coils were held in parallel at d₂₃ = 1.3 cm, using insulating materials. Fig. 8b shows measured waveforms from key nodes (V_C3, V_SW, and V_out) in Fig. 1a circuit when the MCRR operates at 6.78 MHz. In this case, at N = 10, SW is closed for 9¾ cycles (V_SW is high), during which period oscillating amplitude of V_C3 increases up to 6.8 V.

Fig. 9.

(a) Discrete MCRR prototype and experimental setup. (b) Measured waveforms from key nodes of the MCRR circuit in Fig. 1.

Then, SW is opened for ¼ cycles, and V_C3 is boosted up to 25 V because of rapid drop in i_L3 and V_L3 = L₃(di_L3/dt). Fig. 10 compares calculation, simulation, and measurement of V_out vs. N using (14), Fig. 1a simulation in Cadence, and measurements on MCRR prototype in Fig. 9 and Tx-Rx coils in Table I, respectively. We achieved rectified output voltage of 20.9 V across the 100 kΩ load when d₂₃ = 1.3 cm. In Fig. 10, at low N, calculation has a small difference with measurement because of the nonlinearity of parasitic capacitances of D1 and SW, which depend on the voltage across them, and have not been considered in our model. Since at low N, the energy loss, E_CP, is dominant and proportional to these parasitic capacitors, this difference is more obvious than at higher N values. In Fig. 11a, the measured and calculated output voltages in the MCRR is compared with the CHWR while changing the distance between their respective optimized coils, when V_S and R_L are the same. Even though the coils are optimized for the nominal d₂₃ = 1.3 cm, it is clear that MCRR maintains its superiority over the conventional WPT link by boosting V_out up to 65.2% across this range. The MCRR curve also shows that the optimal N does not change with distance, in agreement with the white curve in Fig. 8a.

Fig. 10.

Output voltage vs. N. The results were calculated based on (14), simulated in Cadence, and measured using the setup in Fig. 8a.

Fig. 11.

Output voltage of MCRR and CHWR vs. (a) d₂₃ when R_L = 100 kΩ, and (b) R_L when d₂₃ = 1.3 cm. N is the optimal number of cycles to accumulate energy in the MCRR. (c) Comparing PDL vs. N in the MCRR and CHWR at R_L = 5 kΩ, 12 kΩ, and 100 kΩ. (d) Comparing PDL vs. R_L at RS = 1 Ω, 3.5 Ω, and 10 Ω. d₂₃ = 1.3 cm.

Fig. 11b compares the MCRR and CHWR in terms of V_out at the nominal coil distance, when R_L is changed over two orders of magnitude. In this case, MCRR generates higher V_out and consequently delivers more power to the load than CHWR for lighter loads, which means R_L > 12 kΩ in this prototype. For heavier loading, i.e. lower R_L, which according to Fig. 8b correspond to smaller optimal N, however, CHWR provides higher V_out and PDL. In order to explain this observation, in Fig. 11c we have compared the PDL in MCRR and CHWR for R_L = 5 kΩ (heavy), 12 kΩ (moderate), and 100 kΩ (light) loading vs. N. It can be seen that by decreasing R_L, PDL(max) in both MCRR and CHWR increase. However, the increment in the CHWR is considerably faster than MCRR. The PDL in CHWR is independent of N because in this WPT mechanism, the L₃C₃-tank maintains its induced voltage amplitude and a small but steady amount of power (energy) is delivered to the load in each carrier cycle. MCRR, however, builds up the induced voltage by accumulating energy in the L₃C₃-tank over T_A and suddenly delivering it to the load during T_C. Thus it is very much dependent on N, as shown in Fig. 10.

Because of this fundamental difference in operation, CHWR is always loaded by R_Leq in (23) and operates under Q_3L in (24) on the Rx side, which are heavily dependent on R_L and reflect onto the Tx side as Z_REF in Fig. 3 [31]. For large R_L, V_out is large, and CHWR is at a disadvantage because Q_3L/Q_L is low, and Z_REF > R₂ + RS on the Tx side, resulting in poor impedance matching and low PDL. On the other hand, according to (1), Z_REF in the MCRR is almost independent of R_L, and instead heavily depends on R_SW and R₃. Moreover, unlike CHWR, MCRR is capable of maximizing PDL and V_out by adjusting N, as an additional degree of freedom. For small R_L, V_out and R_Leq are low, and Q_3L in CHWR is considerably higher, resulting in Z_REF that is much closer to R₂ + R_S, thus improving the impedance matching on the Tx side and increasing PDL. The MCRR, however, suffers from the additional R_SW in the L₃C₃ resonance loop, and has only modest increment in the PDL due to reduced E_CP on the Rx side, according to Fig. 11c and (11).

To demonstrate the effect of impedance matching on the Tx side, we have changed the source output resistance in Fig. 11d, which compares PDL in MCRR and CHWR vs. R_L at R_S = 1 Ω, 3.5 Ω, and 10 Ω. It can be seen that for MCRR, the R_L which generates PDL(max) does not change with R_S, supporting the notion that in MCRR, Z_REF is almost independent of R_L. In CHWR, however, increasing R_S moves the peak of PDL towards higher R_L. Since in both MCRR and CHWR less power dissipation in R_S means increased PDL, when these two effects are considered together, increasing R_S shifts the crossing point, at which PDL(MCRR) = PDL(CHWR) to lower R_L.

It is worth noting that at very low R_L < 1 kΩ, because, as discussed in Chapter II, when V_out < V_C3,Peak, D₁ is turned on regardless of SW status the resulting in significantly reduced energy accumulation in L₃C₃ (E_L3). As a result, the MCRR operating mechanism falls apart, and the abovementioned circuit model in Fig. 2 and associated equations are no longer valid.

In Fig. 12 we have compared MCRR and CHWR in terms the overall efficiency (efficiency from the source voltage to output, η), which follows a similar trend as the PDL and V_out in Fig. 10. As shown in Fig. 12a, at the nominal conditions of V_S = 1.8V, R_L = 100 kΩ, and d₂₃ = 1.3 cm, the MCRR achieves η = 2.2%, which is about 3 times larger than that of the CHWR at η = 0.75%. It can be seen that unlike [24] and [25], which consider the applicability of a mechanism like MCRR only in loosely coupled coils, the MCRR maintains its advantage over CHWR in a wide range of coil separations, i.e. various coupling coefficients, and the η improvement, in fact, grows with stronger coupling between the coils. Fig. 12b compares the MCRR and CHWR in terms of PTE at the nominal coil distance, when R_L is changed over two orders of magnitude. These graphs, similar to Fig. 11b, show the true areas of MCRR superiority where R_L is large and high V_out is needed, depending on the WPT application, and 2-coil CHWR fails to create the optimal matching conditions on the Tx or Rx side. One should, however, note that the multi-coil inductive links [28] and multi-cycle Q-modulation technique [10] are also capable of creating optimal matching conditions, and should be considered depending on WPT circuit parameters and the application.

Fig. 12.

Overall efficiency of MCRR and CHWR vs. (a) d₂₃ when R_L = 100 kΩ, and (b) R_L when d₂₃ = 1.3 cm. N is the optimal number of cycles in the MCRR.

Calculation and measurement of the optimal N may show ±1 cycle discrepancy, as can be seen in Figs. 11 and 12. This can be explained by the non-linearity of the parasitic capacitance of the switch and diode, which are not considered in calculations as mentioned earlier. Although the capacitance variation is not large, V_out variations around the optimal N is also very small, as can be seen in Fig. 10. Therefore, the output voltage at the calculated optimal N is almost the same as the maximum measured voltage despite this discrepancy.

In the MCRR, we assume charging time is well controlled, and we can open the switch at the exact point when i_L3 is at its peak, θ = 3/2π. Since the MCRR uses L₃ as a current source over T_C, and the amount of current is determined by i_L3 at the beginning of T_C, the output of the MCRR is heavily dependent on when the T_C starts. In Fig. 13, we have shown the MCRR output with phase error, Δθ, which is the phase difference between the starting point of T_C and optimal θ = 3/2π. Since the MCRR opens SW for a quarter cycle, the output decreases for |Δθ| < 90°. For |Δθ| > 90°, although we open the SW, the direction of i_L3 is against the direction of the D1, and load is not charged during T_C. On the other hand, during T_A, the MCRR works like the CHWR with decreased Q (because of R_SW), and load is charged during T_A. Therefore, the output voltage of the MCRR is constant when |Δθ| > 90°.

Fig. 13.

Output of the MCRR v.s. phase error (Δθ) when d₂₃ = 1.3 cm, R_L = 100 kΩ, and N=9.

V. Conclusions

We have presented detailed optimization procedure for the multi-cycle resonance rectifier (MCRR), which can achieve considerably higher PDL and efficiency, while boosting the output voltage in wireless powering of high voltage, low power applications, such as electrostatic MEMS sensors compared to conventional methods. The MCRR can be easily implemented with a diode, a switch, and a fast control signal that is synchronized with the power carrier. The MCRR harvests energy from the resonant magnetic field and accumulates it in a series Rx L₃C₃-tank over a certain number of carrier cycles, then suddenly opens the switch at the peak of the coil current to transfer that energy to the load through the diode in a quarter of a carrier period. Key parameters and the design guideline for optimizing the MCRR components, number of cycles for accumulating energy, and specific coil geometries are provided with governing equations. Through an example WPT link, we have compared various aspects of the MCRR operation against that of a conventional half-wave rectifier (CHWR) and clearly identified their pros and cons, and where one method might be preferred over the other. Measurement results have verified the derived equations for calculating the desired output voltage and the optimal N.

Biographies

Jaemyung Lim (S’13) earned a bachelor’s degree in electrical and computer engineering from Hanyang University in Seoul and a master’s degree in electrical and computer engineering from Georgia Tech. He is currently working on his doctoral degree in electrical and computer engineering, conducting research on developing an wireless read-out system-on-a-chip for intravascular ultrasound imaging with capacitive micromachined ultrasonic transducers (CMUTs). His research interests include MEMS interface IC, analog and mixed circuit design, wireless data communication, power management IC, and wireless power transmission.

Byunghun Lee (S’11) received the B.S. degree from Korea University, Seoul, South Korea, and the M.S. degree from Korea Advanced Institute of Technology (KAIST), Daejeon, South Korea, in 2008 and 2010, respectively.

From 2010 to 2011, he worked on wireless power transfer systems at KAIST as a design engineer. He received his Ph.D. degree in Electrical and Computer Engineering at Georgia Institute of Technology. His research interests include analog/mixed-signal IC design and wireless power/data transfer systems for biomedical applications.

Maysam Ghovanloo S’00–M’04–SM’10) received the B.S. degree in electrical engineering from the University of Tehran, Tehran, Iran, in 1994, the M.S. degree in biomedical engineering from the Amirkabir University of Technology, Tehran, Iran, in 1997, and the M.S. and Ph.D. degrees in electrical engineering from the University of Michigan, Ann Arbor, in 2003 and 2004, respectively. From 2004 to 2007, he was an Assistant Professor at the Department of Electrical and Computer Engineering, NC-State University, Raleigh, NC. He joined the faculty of Georgia Institute of Technology, Atlanta, GA in 2007 where he is currently an Associate Professor and the Founding Director of the GT-Bionics Lab in the School of Electrical and Computer Engineering. He has authored or coauthored more than 200 peer-reviewed publications.

Dr. Ghovanloo was the general chair of the IEEE Biomedical Circuits and Systems (BioCAS 2015) in Atlanta, GA. He is an Associate Editor of the IEEE Transactions on Biomedical Engineering and IEEE Transactions on Biomedical Circuits and Systems. He served as an Associate Editor of IEEE Transactions on Circuits and Systems, Part II (2008–2011), as well as a Guest Editor for the IEEE Journal of Solid-State Circuits and IEEE Transactions on Neural Systems and Rehabilitation Engineering. He has also served on the Imagers, MEMS, Medical and Displays subcommittee of the International Solid-State Circuits Conference (ISSCC) from 2009–2014. He has received the National Science Foundation CAREER Award, the Tommy Nobis Barrier Breaker Award for Innovation, and Distinguished Young Scholar Award from the Association of Professors and Scholars of Iranian Heritage.