Electric-field-controlled interface dipole modulation for Si-based memory devices

Abstract

Various nonvolatile memory devices have been investigated to replace Si-based flash memories or emulate synaptic plasticity for next-generation neuromorphic computing. A crucial criterion to achieve low-cost high-density memory chips is material compatibility with conventional Si technologies. In this paper, we propose and demonstrate a new memory concept, interface dipole modulation (IDM) memory. IDM can be integrated as a Si field-effect transistor (FET) based memory device. The first demonstration of this concept employed a HfO₂/Si MOS capacitor where the interface monolayer (ML) TiO₂ functions as a dipole modulator. However, this configuration is unsuitable for Si-FET-based devices due to its large interface state density (D_it). Consequently, we propose, a multi-stacked amorphous HfO₂/1-ML TiO₂/SiO₂ IDM structure to realize a low D_it and a wide memory window. Herein we describe the quasi-static and pulse response characteristics of multi-stacked IDM MOS capacitors and demonstrate flash-type and analog memory operations of an IDM FET device.

Introduction

Emerging memory devices with various mechanisms have been investigated in an effort to replace Si-based NAND flash memories, which are the most common type of digital storage device, e.g., resistive random access memories (ReRAMs), phase change memories (PCMs), ferroelectric tunnel junctions (FTJs), and ferroelectric field-effect transistors (FeFETs)^1–8. The advantages of these new devices are a faster operation speed and a higher endurance than a conventional flash memory. Material compatibility with conventional Si device technologies provides a competitive advantage to realize mass production. In particular, Si metal-oxide semiconductor (MOS) FETs used for flash memories are promising building blocks as they provide a high-density three-dimensional memory-cell platform, which can reduce the development cost.

In a flash memory, the electric charge accumulated in the gate stack structure of the MOSFET is read out as the channel current. Similarly, FeFETs utilize the spontaneous polarization of a ferroelectric material integrated in the MOS structure. In particular, ferroelectric HfO₂ is a promising material in terms of Si material compatibility because Hf-based gate oxides are employed in advanced Si complementary MOS devices^7,8. Various elaborate methods have been proposed to fabricate orthorhombic HfO₂ that acts as a ferroelectric, including doping with Zr, Si, Al, Y, Gd, La, or Sr, and controlling the thermal budget of pure HfO₂ films^9–12. Indeed, a flash-type memory operation of HfO₂-based FeFET arrays fabricated with an advanced Si-CMOS platform has been demonstrated⁸. Therefore, it is worthwhile to explore HfO₂-based memory materials that are compatible with Si CMOS technology.

Many recent studies have focused on the continuous conductance changes of memory devices because such a change should realize high-efficiency low-power neuromorphic computing^13–17. The spike-timing-dependent plasticity (STDP) is the most common biological synaptic learning rule. In STDP, the synaptic weight varies with the time difference between presynaptic and postsynaptic neuron spikes. In electronic memory-based synapse devices, electrical pulses (e.g., pulse number, voltage amplitude, width, and polarity) control the conductance change and are utilized to emulate the STDP behavior. As examples, the electric-field-controlled conductive filament in a ReRAM device, the thermally controlled amorphous/crystalline phase change in a PCM device, and the field-controlled ferroelectric domain growth in the FTJ and FeFET devices have been utilized for the STDP operation^13–17. From the viewpoint of Si-MOS compatibility, HfO₂-FeFET devices are advantageous¹⁷, and the new memory device proposed in this paper has similar advantages.

Herein firstly, a new memory concept, interfacial dipole modulation (IDM) occurring at HfO₂/Si and HfO₂/SiO₂ interfaces, is explained and demonstrated. Then the flash-type memory operation and pulse-induced gradual current change of Si-FET-based IDM device are reported.

Controlling interfacial dipoles affects the interface band alignment and is indispensable in the development of semiconductor devices. Thus, dipole formation at a solid/solid interface is well researched. Numerous dipole formation mechanisms have been proposed for metal/semiconductor, semiconductor/semiconductor, and oxide/semiconductor interfaces. These mechanisms are roughly classified into two models: charge transfer due to the interface states and electric polarization of the interface chemical bonds^18–22. Recently, the interface dipoles formed in HfO₂-based stack structures are well studied because they are related to threshold voltage control of the HfO₂/Si MOSFETs^23–27. However, the dipole formation in the gate stack structures including the oxide/oxide interfaces is complicated compared to the above interfaces. As the simplest structure, we previously reported that a large dipole (>0.5 V) is formed at the HfO₂/Si interface²⁸, and proposed a bond polarity mechanism in which positive and negative alternating charged atoms produce a large potential difference between the HfO₂ and Si sides, as shown in Fig. 1a ^29,30. In this model, the polarizations of the interfacial Si-O and O-Hf bonds largely affect the total potential difference because these interface regions have small predicted local dielectric constants compared to Si and HfO₂. This is easily predicted from microscopic dielectric responses based on the chemical gradient³¹. Thus, interface chemical bonding largely influences MOSFETs operations, depending on the strength of interface dipole³².

Figure 1.

Interface dipole modulation (IDM) concept and experimental demonstration at the HfO₂/Si interface. (a) Schematic illustration of dipole formation and IDM operation at the HfO₂/Si interface. Large interface dipoles are observed from the HfO₂/Si structures, which are reasonably explained by the bond polarity mechanism, from ref.²⁹. The IDM operation utilizes this mechanism. Dipole strength changes due to the atomic displacement induced by the electric field. (b) Effect of the interface TiO₂ layer on the high-frequency capacitance-voltage (C-V) curves of the 5.5-nm-thick HfO₂/Si MOS capacitors fabricated on n-type Si substrates. Double sweep measurements were performed in the voltage ranges between −1.0 V and the positive voltages shown in this figure. Counterclockwise hysteresis suggests that the IDM behavior appears for the HfO₂/1-monolayer (ML) TiO₂/Si structure. (c) Cyclic operation of the HfO₂/1-ML TiO₂/Si IDM device under various voltage sweep conditions. (d) Retention characteristics of the HfO₂/1-ML TiO₂/Si IDM device. Large and small capacitance states measured at +1.0 V are plotted as a function of time after applying a stress voltage.

The IDM concept originates from the above dipole formation mechanism at the HfO₂/Si interface. If the electric field induced by the gate voltage changes the position of the interface atoms, the interface dipole is supposed to be modulated (Fig. 1a). Since similar switchable interfacial metal-oxygen bonds have been predicted for metal/ferroelectric oxide interfaces using first principles calculations³³, we expect that the IDM operation occurs at the HfO₂/Si interface if an appropriate interface bonding is constructed. The IDM-integrated FET (IDM FET) is expected to behave like FeFET. However, the operation mechanism is completely different. Although switching of spontaneous polarization in a ferroelectric film is utilized in FeFETs, modulation of the dipoles induced in the atomic-scale interface region dominates IDM operation.

The double swept capacitance-voltage (C-V) trace of the conventional HfO₂/Si MOS capacitor in Fig. 1b does not show any evidence of the IDM operation. A small clockwise hysteresis takes place, indicating charge trapping around the HfO₂/Si interface³⁴. Meanwhile, a counterclockwise hysteresis appears when a monolayer-thick TiO₂ is inserted at the HfO₂/Si interface. A particularly large hysteresis (>0.5 V) occurs at the 1-ML TiO₂ interface. A counterclockwise hysteresis indicates charge movement inside the gate stack structure, that is, ferroelectric polarization inversion⁶ or an IDM operation. Since the HfO₂ layer is amorphous (Supplementary Fig. S1a), the ferroelectric effect can be excluded.

The hysteresis width strongly depends on the insertion of monolayer TiO₂. It may be reasonable to consider that some structural change of the interface TiO₂ produces a large potential change between the Si and HfO₂ sides. In this manuscript, we call the interface 1-ML TiO₂ a dipole modulator. The fundamental memory function, cyclic modulation, and two-states retention are obtained (Fig. 1c and d). The modulation width strongly depends on the sweep voltage range, and reaches about 0.7 V. This value is comparable to the intrinsic interface dipole observed for the HfO₂/Si interface^28–30. The long retention can exclude the effect of electron and/or hole trapping around the interface because the typical interfacial-charge trapping shows a much shorter response^34,35. On the other hand, the C-V curve for the 1-ML TiO₂ sample is stretched towards a positive bias, indicating that the interface state density (D_it) is larger than that of non-TiO₂ interface. Actually, D_it of the HfO₂/TiO₂/Si IDM structure is estimated to be about 2 × 10¹³ cm⁻² eV⁻¹ around the mid-gap energy (Supplementary Fig. S2). This is easily predictable since an electrically switchable TiO₂ layer likely includes large amounts of unstable bonds. Thus, the HfO₂/Si IDM structure is not suitable for FET-based memory devices.

We then explored HfO₂/SiO₂-based IDM structures to solve the interface state problem since inserting a SiO₂ layer should separate the charge traps created around the TiO₂ modulator from the Si surface. Experimental and theoretical studies have been conducted on dipole formation at HfO₂/SiO₂ interfaces. The proposed mechanisms are somewhat complicated compared to those for metal/semiconductor, oxide/semiconductor interfaces, etc. However, most mechanisms for dipole formation at HfO₂/SiO₂ interfaces are based on charge transfer occurring at the HfO₂/SiO₂ interface such as an electronegativity effect around interfacial Hf-O-Si bonding and the movement of oxygen atoms^24–27. Therefore, we expect an IDM operation in the HfO₂/SiO₂ stack structure when some of the charged atoms around the HfO₂/SiO₂ interface are moved by the gate bias. The HfO₂/1-ML TiO₂/SiO₂ IDM structure (Fig. 2a) exhibits a hysteresis C-V curve without displaying stretched-out characteristics (Fig. 2c). Actually, D_it estimated for this MOS structure is comparable to that of conventional SiO₂/Si interface (D_it < 1 × 10¹¹ cm⁻² eV⁻¹ around the mid-gap energy, Supplementary Fig. S2c). The C-V curve shows a counterclockwise hysteresis as well as the features of the above HfO₂/Si IDM structure. It is obvious that carrier injection from the Si substrate is not the origin of hysteresis. Meanwhile, carrier injection from the gate electrode, that is, carrier trapping by interface TiO₂ potentially results in a counterclockwise hysteresis. However, this mechanism should also be excluded because the hysteresis characteristic is independent of the thickness of the top HfO₂ layer, as explained below. On the other hand, the hysteresis window is obviously small (<0.2 V) and insufficient for memory applications. This probably originates with the difference in the intrinsic dipole strength; that is, the dipole of the HfO₂/SiO₂ interface is reported to be smaller than that of the HfO₂/Si interface^26,28. One reason for this smaller dipole may be due to disordered chemical bonding at amorphous HfO₂/SiO₂ interfaces.

Figure 2.

HfO₂/SiO₂-based IDM structures and C-V hysteresis curves. (a and b) Schematic illustration of single and multi-stacked HfO₂/1-ML TiO₂/SiO₂ MOS structures. According to the IDM mechanism, the modulation by the TiO₂ modulators at two facing interfaces are superimposed and enhanced. (c) C-V curves observed from single and six-stacked IDM MOS capacitors fabricated on n-type Si substrates. The former consists of 3-nm-thick top HfO₂ and 10-nm-thick bottom SiO₂ layer, while the latter consists of 3.5-nm-thick top HfO₂, 1.8-nm-thick inner SiO₂, 1.8-nm-thick inner HfO₂, and 10-nm-thick bottom SiO₂ layers. Small counterclockwise hysteresis appears in a single IDM structure and an obviously large hysteresis appears in the six-stacked IDM structure. (d) Transmission electron microscopy (TEM) image and electron diffraction (ED) pattern of the six-stacked IDM structure. These results indicate that all oxide layers are amorphous. Note that it is difficult to distinguish between SiO₂ and TiO₂ in the TEM image.

Amorphous materials can be easily stacked (Fig. 2b). Thus, multi-TiO₂ modulators can be integrated in the same MOS structure. Here, we consider two types of IDM behavior: the upper-HfO₂/lower-SiO₂ and the upper-SiO₂/lower-HfO₂ interfaces. Under an electric field induced by a positive gate bias, the former and the latter dipoles are predicted to increase and decrease, respectively. Under the opposite electric field, the opposite dipole modulations occur. This means that the TiO₂ modulations occurring at two facing interfaces are superimposed and contribute to the enhanced memory window. In fact, a larger hysteresis is observed from the six-stacked HfO₂/1-ML TiO₂/SiO₂ IDM structure (Fig. 2c). Thus, the multi-stacked IDM structure is preferable for memory application.

The transmission electron microscopy (TEM) image and electron diffraction pattern (Fig. 2d) exhibit that the HfO₂ layers are amorphous. Therefore, the effect of ferroelectric HfO₂ can also be eliminated, even for a multi-stack HfO₂/SiO₂ IDM structure. In general, the formation of a ferroelectric HfO₂ film requires annealing at a temperature above 450 °C and the thinnest HfO₂ film employed in their experiments is 5 nm^{7–12,17,36,37}. The annealing temperature of the six-stacked IDM structure shown in Fig. 2d is 350 °C, and the thickness of internal HfO₂ layer is 1.8 nm. It was reported that HfO₂ crystallization hardly occurs when the film thickness becomes thin³⁸. Thus, we can reasonably conclude that our IDM structure does not include crystalline HfO₂. In addition, the memory window of the single HfO₂/1-ML TiO₂/SiO₂ IDM structure is independent of the HfO₂ film thickness, as mentioned below. This means that, rather than bulk HfO₂ (i.e., a ferroelectric effect), the interface is a major component in the IDM operation. On the other hand, the HfO₂/SiO₂ interface shown in the TEM image has atomic-scale roughness, indicating that various bonding configurations probably exist at this interface. In the IDM operation, the charge displacement component perpendicular to the interface is considered to contribute to the potential change. The atomically rough interface is probably disadvantageous for the IDM operation. Consequently, if an atomically abrupt interface is formed, the memory window should be further enhanced.

The hysteresis C-V curves show that the voltage shift in the forward sweep is smaller than that in the backward sweep (Fig. 2c). This tendency is mainly due to the depletion of minority carriers in the negative voltage range. That is, the Si depletion layer prevents the generation of a sufficient electric field in the oxide layers. To investigate the IDM behavior in both polarity ranges, lower-frequency C-V curves were measured under a weak light illumination, which generates sufficient minority carriers. Approximately symmetric shifts of the flat-band voltage (V_fb) are observed for both polarities (Fig. 3a and b).

Figure 3.

Hysteresis C-V characteristics of HfO₂/SiO₂ IDM MOS capacitors. (a) C-V curves of the four-stacked IDM MOS capacitor consisting of 3.5-nm-thick top HfO₂, 1.8-nm-thick inner SiO₂, 1.8-nm-thick inner HfO₂, and 10-nm-thick bottom SiO₂ layers. Double sweep measurements are performed at 5 kHz under weak light illumination. Sufficient electric fields for both positive and negative bias ranges are produced in the oxide layers. (b) Bias dependence of the flat-band voltage (V_fb) observed from the four-stacked IDM MOS capacitor. Sample with a thin bottom SiO₂ layer (5.2 nm) exhibits a V_fb shift in the lower voltage range compared to a thick bottom SiO₂ layer (10 nm). This difference is almost canceled out in the electric field dependence (Supplementary Fig. 3a), suggesting that the IDM operation is a field driven process. (c) Dependence of the modulation width on electric field. Modulation width (ΔV) is the difference between the V_fb values of the forward and backward voltage sweeps. (d) Dependence of the saturation modulation width, ΔV_sat, on the number of IDM layers. The TiO₂ modulator has an ability to modulate the interface dipole by 0.32 V. (e) Dipole modulation width of a single IDM structure as a function of HfO₂ thickness. Initial V_fb, maximum V_fb, and minimum V_fb values are not affected by the top HfO₂ thickness (t_HfO2). This result suggests that the change in the interface dipole dominates the observed voltage shifts.

In the case of backward sweeping (i.e., after positive bias stress), the turn-back behavior is recognized for the thinner bottom SiO₂ sample, suggesting that electron injection from Si into the IDM structure through the bottom SiO₂ layer occurs similar to a flash memory³⁹. The V_fb shift of the thinner bottom SiO₂ sample occurs in the lower voltage region compared to the thicker bottom SiO₂ sample. However, the plot as a function of the electric field agrees well with the observations (Supplementary Fig. S3a). Various IDM structures with different bottom SiO₂ layers (5–10 nm) show consistent electric-field dependences (Fig. 3c). This result suggests that the dipole modulation is an electric field driven phenomenon. The saturated hysteresis in the high electric field region (i.e., the maximum modulation width) is roughly proportional to the number of IDM layers, assuming the average estimated modulation capability of a single IDM layer is 0.32 V.

It is worth describing the behavior of a single IDM structure to understand the observed hysteresis characteristics. The initial V_fb values, which were measured before applying a high electric field, are almost independent of the top HfO₂ thickness (Fig. 3e). Compared to the ideal V_fb value estimated from the work function difference between Si and the Ir gate metal [Φ_MS (V)], a negative voltage shift takes place. Here we ignore the fixed charges and dipoles in the bottom SiO₂/Si structure according to the previous studies^28–30. For simplicity, we assume two types of charges at the HfO₂/1ML-TiO₂/SiO₂ interfaces: a positive sheet charge [S_I (cm⁻²)] and a dipole layer with a negative sheet charge on the HfO₂ side and positive on the SiO₂ side [Φ_D (V)]. The dependence of V_fb on HfO₂ thickness $t_{{\mathrm{Hfo}}_2}$ (nm)] is expressed as^28,40

$$V_{FB}={\Phi }_{MS}-\frac{q{S}_I{t}_{HfO2}}{{\epsilon }_{HfO2}}-{\Phi }_D,$$ 1

where ε_HfO2 is the dielectric constant of the HfO₂ layer. Equation (1) indicates that V_fb should be proportional to the HfO₂ thickness when the unipolar charges dominate the voltage shifts, as shown by the dashed line in Fig. 3e. The observed t_HfO2 dependence implies that the initial voltage shift is dominated by the interface dipole. The estimated initial dipole strength is about 0.47 V, which is slightly larger than that of the HfO₂/SiO₂ interface^26,28. The maximum and minimum V_fb shifts after applying a high electric field are independent of the HfO₂ thickness, suggesting that the observed field-induced voltage shift is due to the change in dipole strength. It is concluded that the interface dipole in the HfO₂/1-ML TiO₂/SiO₂ IDM system of 0.47 V is modulated by about ± 0.16 V.

The pulse response is an important characteristic when discussing the modulation mechanism as well as when applying it to memory and synaptic devices. In this study, we examined the pulse-induced V_fb shift using a repetitive sequence of the C-V measurement and pulse application (Fig. 4a, inset). Since the six-stacked IDM structure shows a slightly larger charge trapping effect under a high electric field (Fig. 3c), the four-stacked IDM structure was investigated to examine the IDM pulse response. Figure 4a and b exhibit the strong dependence of the voltage shift on the pulse width [t_pulse (sec)] and the pulse voltage [V_pulse (V)].

Figure 4.

Pulse response characteristics of the four-stacked HfO₂/SiO₂ IDM MOS capacitor. IDM MOS capacitor consists of 3.5-nm-thick top HfO₂, 1.8-nm-thick inner SiO₂, 1.8-nm-thick inner HfO₂, and 5-nm-thick bottom SiO₂ layers. (a) V_fb shift with various pulse widths and pulse voltage of +4.0 V. The plotted δV_fb values show the voltage shifts from the initial V_fb. (b) V_fb shifts with various pulse voltages and a pulse width of 200 nsec. Dotted lines in Fig. 4a,b show the fitting curves based on the random bond breakage/repair model. (c) Reaction rate (k) as functions of electric field and pulse width.

A promising IDM mechanism is the electric-field-induced breakage/repair of the interfacial Ti-O bonds. More simplistically, the bistable switchable state between the broken Ti-O and the repaired Ti-O bonds can be assumed. In other words, the Ti coordination number changes due to the electric field (e.g., between the five-fold and four-fold Ti atom). The thermochemical theory proposed for the breakage of Si-O bonds^41,42 is a sophisticated expression to explain the electric-field-induced bond breakage. The reaction rate, k (s⁻¹), under the electric field, E (V/cm), is given by

$$k=v_{0}exp\left(-\frac{\mathrm{\Delta }{H}_0^{⁎}-p_{eff}E}{k_{B}T}\right),$$ 2

where v₀ is the molecular vibrational frequency, which is generally on the order of ~10¹³ (s⁻¹). T and k_B are the temperature (K) and Boltzmann’s constant, respectively. Zero-field activation energy [ΔH₀ (eV)] exponentially decreases the reaction rate, while the effective dipole moment [p_eff (eÅ)] dominates the electric-field dependence. Hence, these two parameters can be separately deduced from the field dependence of the reaction rate, as described below.

At an actual IDM interface, the large amount of Ti-O bonds (~10¹⁴ cm⁻²) contributes to the modulation. In this discussion, we assume the simplest kinetics where the bond breakage/repair process proceeds randomly. This means that the nucleation and domain growth, which are general polarization switching kinetics in ferroelectric films, are neglected^43–45. The total amount of bonds, θ (cm⁻²), which suffer from the breakage/repair process from 0 seconds to the specific time, t (sec), follows the rate equation: dθ/d t = (1 − θ) · k. Thus, the amount of switched bonds can be given by θ(t) = 1 − exp(−k · t). After applying a suitable electric field for a sufficient time, δV_fb reaches the saturated voltage [δV_sat (V)]. The measured time dependence should be expressed as δV_fb (t) = δV_sat · [1 − exp(−k · t)]. This equation has a good consistency with the measured data, and the reaction rate can be deduced as shown by Fig. 4c.

Significant change is not recognized from the pulse-width dependence shown in Fig. 4c, which suggests that the effect of different time-dependent phenomena such as trap and dipole loss responses^34,35 are not significant in this pulse-width range. From the field dependence shown in Fig. 4c, ΔH₀ and p_eff are estimated to be 0.72 eV and 4.6 eÅ, respectively. These parameters are within an acceptable range. For example, the reported bond breakage of O−Si≡O₃ tetragonal molecules in silica is ΔH₀ = 1–2 eV and p_eff = 7–13 eÅ, depending on the charge trapping, bond distortion, and the defective structure^41,42. It has also been reported that Hf-O bond breakage in HfO₂ shows ΔH₀ = 4.6 eV⁴⁶. Obviously, ΔH₀ of the IDM operation is smaller than those of Si-O and Hf-O bond breakages. In addition, the reported breakdown field (Ε_bd) of TiO₂ is 1–2.5 MV/cm, which is smaller than either SiO₂ (15 MV/cm) and HfO₂ (6.7 MV/cm)^42,46,47. Therefore, we can reasonably consider that the Ti-O bond in the IDM layer is easily broken compared to the Si-O and Hf-O bonds. The displacement of the charged Ti and O atoms associated with the Ti-O bond breakage likely alters the interface dipole of the HfO₂/1-ML TiO₂/SiO₂ structure, as described for HfO₂/1-ML TiO₂/Si structure in Fig. 1a. In the amorphous HfO₂/1-ML TiO₂/SiO₂ structure, various Ti-O bonding configurations may contribute to the IDM operation because such an operation occurs at the amorphous atomically rough interface. However, more elaborate studies are necessary to assign detailed structural changes.

An appropriate hysteresis is observed in the I_d − V_g curve of the FET device with six-stacked HfO₂/SiO₂ IDM structure (Fig. 5a), demonstrating that the IDM phenomena can be read as the channel current. The endurance characteristics observed by alternately applying positive and negative bias pulses show good cyclic switching of 10⁵ and a large current difference of about 10⁵. However, this memory performance has yet to reach a level to be competitive with advanced HfO₂ FeFET and two-terminal resistance change devices^3–8,48,49. In particular, the large operation voltage is a serious issue.

Figure 5.

Operation of six-stacked HfO₂/SiO₂ IDM FET. IDM FET consists of 3.5-nm-thick top HfO₂, 1.8-nm-thick inner SiO₂, 1.8-nm-thick inner HfO₂, and 5-nm-thick bottom SiO₂ layers. (a) Drain current vs. gate voltage (I_d − V_g).  The drain current of the IDM FET were measured at V_ds = 0.3 V in various gate voltage ranges: −1 V $\rightleftarrows$ +2 V, −2 V$\rightleftarrows$ +3 V, −3 V $\rightleftarrows$ +4 V, and −4 V $\rightleftarrows$ +5 V. (b) Cyclic switching characteristics. Small and large I_d states are switched by alternatively applying 100-μsec pulses at +5.2 V and −4.6 V. (c) Pulse-induced continuous current change. Drain current is monitored at V_ds = +0.3 V and V_g = +0.3 V by applying 1-μsec pulses with various gate voltages. Interface dipoles hardly respond to low absolute voltage pulses (−2.5 V < V_pulse < +3.5 V) and become sensitive to the increase in the absolute voltage outside this range.

We consider that scaling of the equivalent oxide thickness (EOT) is indispensable to suppress the operating voltage because the current multi-stack IDM gate is not optimized in terms of the EOT scaling. Below are prospective ideas for the EOT scaling. (1) Bottom dielectric layer: the 5–10-nm thick SiO₂ bottom layer is employed in the current IDM structures. A thin HfO₂ layer should be effective, provided that a low D_it can be maintained. (2) Scaling of inner dielectric layers: the current multi-stack IDM structure employs 1.8-nm thick HfO₂ and SiO₂ layers. Thinning these layers is possible and effective, but the interface abruptness should be simultaneously improved. (3) Material selection of IDM dielectrics: the IDM structure using dipoles induced at high-k/high-k interfaces is advantageous compared to the current low-dielectric-constant SiO₂/HfO₂ interface. We expect to realize low-voltage IDM operations using (1)–(3).

Furthermore, we would like to mention an issue with the multi-stack IDM structure, which is shown in Fig. S3c. The retention characteristics are degraded more than the HfO₂/Si IDM structure (Fig. 1d). The depolarization field and the carrier traps are considered to be the major causes^50,51. For the latter, further studies on the oxide material selection and formation method to eliminate the defects in multi-stack oxide structure are necessary.

The pulse-induced current change was investigated as an application to synaptic devices (Fig. 5c). The current is approximately constant at pulse voltages between −2.5 V and +3.5 V. Outside this range the current change becomes large as the absolute pulse voltage increases. This behavior can be easily understood by the above thermochemical mechanism represented by Eq. (2). An important feature of this mechanism is the threshold voltage, which is an important function in the STDP operation^16,52. Furthermore, these current changes can be roughly predicted by the above random bond breakage/repair model, which is advantageous in designing synaptic device. STDP operations based on a similar three-terminal FeFET devices have been reported, where the current can be controlled gradually by rectangular or triangular pulses^17,53. We expect that the STDP operation of IDM FET device can be realized in a similar manner.

In conclusion, the concept of an IDM memory is proposed and demonstrated using HfO₂-based gate stacks of Si MOS devices. In this demonstration, the 1-ML TiO₂ modulator inserted at HfO₂/Si and HfO₂/SiO₂ interfaces plays a major role. The electrical characteristics of multi-stacked HfO₂/1-ML TiO₂/SiO₂ IDM MOS capacitors are investigated in detail because this IDM structure is preferable for Si-FET-based flash memory devices. After fabricating the multi-stacked IDM FET device, its switching operation and pulse-induced current change are presented.

Methods

Oxide deposition

HfO₂, SiO₂, and TiO₂ films were deposited via an ultra-high vacuum evaporation system³⁰. Metallic Hf, Si, and Ti were evaporated in oxygen pressure without heating Si substrate. After the formation of HfO₂/TiO₂/Si and HfO₂/TiO₂/SiO₂/Si IDM structures, post-deposition annealing was performed at 350–400 °C for 1 min. The x-ray photoelectron spectroscopy confirmed that almost stoichiometric amounts of HfO₂, SiO₂, and TiO₂ were deposited on the substrates by this method. In particular, this evaporation method allows the HfO₂/Si interface with a monolayer thickness to be controlled^28–30,32 and is indispensable to prepare the HfO₂/1-ML TiO₂/Si structure, which was employed in the first demonstration of the IDM concept.

MOS and FET fabrication

The MOS capacitors were prepared on n-type or p-type Si(100) substrates. The bottom SiO₂ layers were grown by thermal oxidation of Si substrates. SiO₂ layers with thicknesses between 5–10 nm were fabricated by hydrofluoric acid etching. For the single IDM structures, top HfO₂ layers of varying thicknesses between 2–6 nm were deposited. For the multi-stack IDM structures, 1.8-nm-thick inner HfO₂, 1.8-nm-thick inner SiO₂, and 3.5-nm-thick top HfO₂ layers were deposited. Ir films were deposited on the oxide layers, and the Ir electrodes (100 × 100 μm) were fabricated by a lithography technique. The MOS FET devices (L_g = 1 μm and W = 100 μm) were fabricated by the so-called gate last processes³². First, the source/drain regions were fabricated on p-type Si(100) substrates. Second, multi-stack IDM structures with the same thick layers as the above MOS capacitors were fabricated. Finally, the Ir gate electrodes were fabricated by the same method used to prepare the MOS capacitors.

C-V measurements and analyses

The high-frequency C-V curves were measured at 1 MHz with a gate voltage sweep from a negative to a positive bias, and then immediately swept in the opposite direction. The lower-frequency C-V curves were measured at 5 kHz under weak light irradiation. The flat-band voltage (V_fb) was determined by fitting with the ideal C-V curve (Fig. 3a). It is difficult to adopt the same method to the C-V curves of HfO₂/Si IDM MOS capacitors due to the large stretched characteristics. Figure 1c plots the relative voltage shifts determined by the flat-band capacitor^34,35. The maximum and minimum electric fields were estimated from the measured maximum capacitances in the accumulation and inversion ranges, respectively.

Pulse response measurements

First, a gate voltage of −4 V was applied as an initialization, shifting V_fb to the positive bias direction. Second, 100-times cyclic C-V measurements were performed at 1 MHz in the range from −0.4 V to +0.7 V. After this process, V_fb was stabilized between 0.35–0.45 V, which is the stable state under these C-V measurement conditions, and is defined as the initial V_fb (t = 0). Finally, the cyclic sequence of the C-V measurement under the same conditions and pulse application was performed (Fig. 4a, inset). The pulse electric field was determined for the initial state by using an ideal MOS C-V curve.

Author Contributions

N.M. carried out the experiment and wrote the paper.

Competing Interests

The author declares no competing interests.