Design and characterization of a package-less hybrid PDMS-CMOS-FR4 contact-imaging system for microfluidic integration

Abstract

We demonstrate a hybrid “package-less” polydimethylsiloxane (PDMS)-complementary-metal-oxide-semiconductor (CMOS)-FR4 system for contact imaging. The system embeds the CMOS image sensor directly in a PDMS layer instead of the standard chip package to support microfluidic structures much larger and more complex than those in prior art. The CMOS/PDMS layer is self-aligned to form a continuous, flat surface to provide structural support for upper microfluidic layers. The system consists of five layers of PDMS implementing fluid channels, valves, chambers, and inlets/outlets. A custom CMOS image sensor with integrated signal conditioning circuits directly captures light from sample fluid for high optical collection efficiency. Owing to the flexibility afforded by the integration process, the system demonstrates, for the first time, integrated valves in contact imaging. Moreover, we present the first direct comparison of the optical performance of a CMOS image sensor and a photomultiplier tube (PMT) in identical contact-imaging conditions. Measurements show that our CMOS sensor achieves 17 dB better signal-to-noise ratio (SNR) compared to a commercial PMT across a broad range of integration times, with a maximum SNR of 47 dB. Chemiluminescent testing successfully shows signal detection for different analyte concentrations and integration times. The contact-imaging system demonstrates a detection limit of 25 μM of a 9,10-diphenylanthracene-based solution.

1. Introduction

Hybrid microsystems promise sensing solutions for biomedical applications with lower cost, more portability, higher throughput, lower reagent consumption, and more accurate results than conventional techniques.^1,2,3 Such systems are especially attractive for affordable point-of-care diagnostics,^4,5 real-time biological warfare agent detection,⁶ automated large-scale genomic and proteomic studies,^7,8 and pathogen identification.⁹ Optical detection is one common sensing technique to identify and measure materials of interest, but it usually involves bulky lenses, mirrors, fixtures, and a sensor such as a photomultiplier tube (PMT).^10,11,12 “Contact imaging” promises to eliminate the cumbersome macroscale optics by using a complementary-metal-oxide-semiconductor (CMOS) image sensor in direct proximity to the object being imaged.^{13,14,15,16,17,18} Due to this proximity, contact imaging maximizes the optical collection efficiency to eliminate the need for bulky intermediary optics. Existing contact-imaging implementations commonly consists of a CMOS image sensor wire-bonded to an open-cavity package with a microfluidic device placed on top, as illustrated in FIG. 1(a).^13,14,15,18 However, attaching the microfluidic device to the sensor is nontrivial due to the sensor’s small dimensions, fragile bond wires, and irregular cavity shapes. The microfluidic devices by Singh et al.¹³ and Huang et al.¹⁸ are necessarily smaller than the area of the sensor so as to fit entirely on the sensor surface for structural support. Making the microfluidic device smaller than the image sensor significantly limits the microfluidic device’s design freedom and the amount of functionality that can be integrated. Other work face similar restrictions and assembly complexities.^14,15 In short, the existing integration techniques for contact imaging are highly complex, incompatible with large microfluidic designs, and difficult to adopt for mass production,

FIG. 1.

(a) Cross-sectional view of a conventional contact-imaging system using a chip package with limited area for the microfluidic device and (b) our contact-imaging system using a PDMS base which can be arbitrarily scaled to support any microfluidic device size.

Another deficiency among current contact-imaging work is that, despite the intended replacement of conventional macroscale instruments such as PMTs, a rigorous comparative study of sensor performance in the contact-imaging environment has not yet been reported. Specifically, while several prior contact-imaging papers have characterized the optical performance of the CMOS sensor, none has reported both CMOS and PMT measurements under the same conditions. ^{13,14, 17,19} Since sensor performance heavily depends on numerous variables such as the light source, sensor size, integration time, electrical bandwidth, acquisition instruments, etc., direct comparisons without identical setups are problematic.

In this paper, we present a “package-less” contact-imaging system that is simple, robust, and scalable to virtually any microfluidic design size. Foregoing the typical semiconductor package, the system utilizes a polydimethylsiloxane (PDMS) layer as a base structure to embed the CMOS sensor, as shown in FIG. 1(b). A self-aligning step forms a flat, continuous CMOS/PDMS surface to accommodate an upper microfluidic device. The base layer and the microfluidic device can be easily expanded to support sophisticated microfluidic structures of practically any size. The sensor is directly wire-bonded to an FR4 printed circuit board (PCB) and upper microfluidic layers are added without the need of complex epoxy encapsulation. Leveraging the flexibility and scalability afforded by the integration process, we demonstrate, for the first time, a contact-imaging system with integrated valves. In addition, we present the details of the electrical, optical, and fluidic characterization results and the first direct comparison of the optical performance of a CMOS image sensor and a PMT in the same contact-imaging environment.

Section 2 discusses the overall system, Sections 3 and 4 describe the details of the microfluidic and CMOS devices prior to presenting measurement results in Section 5.

2. System Description

The microfluidic system employs five PDMS layers to create a network of channels, valves, actuation chambers, and inlets/outlets. As shown in the breakout diagram in FIG. 2, the CMOS image sensor is embedded in a PDMS base layer, with four upper layers forming the microfluidic system. The sensor is electrically connected via bond wires to a two-layer FR4 PCB that houses passive electrical components. Contact imaging takes place in fluid channels in the imaging layer. The upper layers contain integrated valves and additional microfluidic structures to manipulate samples. Not shown in the figure, an external syringe pump dispenses test samples into the microfluidic chip and a pressure source actuates the integrated valves. A computer with an acquisition system collects the sensor output for analysis.

FIG. 2.

Our contact-imaging microfluidic system employing five PDMS layers, a CMOS image sensor, and an FR4 PCB (bond wires come out-of-plane, not shown).

3. Microfluidic Device

3.1. Description

The microfluidic device delivers luminescent samples to the surface of a CMOS image sensor for contact imaging. The device is comprised of five PDMS layers individually fabricated using soft lithography and bonded together to form a microfluidic network. FIG. 3(a) shows the layout design of the microfluidic device, which measures 13 mm × 9 mm. Two parallel imaging channels (535 μm long, 350 μm wide, and 70 μm tall) in the upper part of the figure are separated from the CMOS sensor by a thin, 30 μm, PDMS layer such that sample fluid can be brought into close proximity with the CMOS sensor for imaging. Each imaging channel has independent valves controlling the fluid inflow/outflow, thus offering the flexibility to simultaneously test two different samples. The imaging channels are separated by 900 μm to precisely align to the pixels of the CMOS sensor (described in Section 4) to maximize the optical collection efficiency. Sample fluid is delivered to the imaging channels via fluid channels (120 μm wide and 20 μm tall) that connect to the inlets and outlets. Fluid flow in the channels can be controlled by five integrated valves actuated using compression chambers.²⁰ FIG. 3(b) shows the cross-section of the stacked PDMS layers. The CMOS sensor is embedded in the base layer (which is 1 mm thick) and slightly extends beyond the edge of the upper PDMS layers to allow for electrical connections to a PCB via bond wires. The seal layer (30 μm) acts as a seal between the microfluidic chip and the CMOS chip to prevent fluid leakage. The imaging layer (2.5 mm thick) transports sample fluid from the upper layers to the CMOS sensor for imaging. The fluid layer (30 μm) connects the inlets/outlets to the imaging channels, and has collapsible roofs as part of the integrated valves. Finally, the control layer (2.5 mm thick) contains the pressure chambers to actuate the valves. FIG. 3(c) shows the cross-section of the valve. When pressure is applied to the actuation chamber above, the channel’s roof collapses, thus sealing the fluid flow. We note that it would be difficult to integrate this amount of microfluidic functionality in a contact-imaging system using prior art because of the small size of the CMOS sensor (3 mm × 3 mm in our case).

FIG. 3.

(a) Layout of microfluidic device showing channels, valves, and inlets/outlets. (b) Cross-section views of the microfluidic device. (c) Microfluidic valve before and after closing.

3.1. Fabrication

We fabricate the fine features of the PDMS device using a series of lithographic steps in a cleanroom as illustrated in FIG. 4. First, the photoresist (SU8–2025) is patterned lithographically on a silicon wafer to create a mold. We then deposit PDMS over the mold to pattern the microfluidic layers. The rounded microfluidic channels in the fluid layer are formed using a reflow process in which the positive photoresist AZ4620 is photolithographically patterned followed by heating on a hot plate at 125C for 3 minutes to cause the rectangular photoresist cross section shape to become semicircular.²¹ This results in rounded channels in the molded PDMS, which is necessary to create pneumatically actuated valves to completely close a microchannel.²² To create the base PDMS layer, we embed the CMOS sensor in PDMS by placing it upside-down on a silicon wafer before pouring the PDMS mixture. To prevent PDMS leakage under the sensor, we use a 23-gauge blunt needle to apply a 5-psi force on the sensor as shown in FIG. 4(b). The PDMS with the sensor is then baked on a hot plate to cure. Because the CMOS sensor is placed upside-down when the PDMS is poured, a self-aligned flat surface forms on the backside of the layer. This surface is key to provide stable structural support for the upper layers. To assemble the PDMS layers, we use the curing agent as an adhesive. First, we detach a PDMS layer from the mold, punch any necessary vertical channels using a 21-guage blunt needle, and stamp it onto a wafer coated with the curing agent. Next, we align the PDMS layer using a microscope and an XYZ stage on which the next PDMS layer is mounted above the previous PDMS layer, and bring them in contact to assemble the two together once their relative alignment has been adjusted as observed visually in the microscope. While this alignment process is performed manually for our prototype, it can be easily automated with a pick-and-place system for high-volume production. We wire-bond the embedded CMOS sensor to the PCB before placing the PDMS layer stack on top. Since the upper PDMS layers are added after the CMOS sensor is wire bonded to the PCB, our fabrication flow offers unobstructed bond wire access to the CMOS sensor. The same process for automated semiconductor packaging can be used for the wire bonding. Finally, the entire assembly is baked to cure the adhesive. FIG. 5 shows the assembled device with the fluid channels filled with dyed water for contrast. Note that the upper PDMS layers are offset slightly to expose the edge of the sensor for wire bonding. We remark that, unlike the prior art, no physical structure is placed on top of the bond wires, thus avoiding complex encapsulation procedures and issues with uneven surfaces after encapsulation. In addition, the integration process can easily accommodate different microfluidic device sizes by scaling the size of the base layer, in contrast to the prior art where the microfluidic device size is limited by the size of the sensor. Lastly, the integration process leverages the standard planar lithographic processes, which are highly amenable to volume production. For example, multiple PDMS layer units can be created on the same substrate, and separated after fabrication with an automated cutter, followed by assembly using automated pick-and-place machines.

FIG. 4.

(a) PDMS device fabrication steps beginning with 1. photoresist patterning, 2. mold development, 3. PDMS deposition, 4. PDMS detachment, and 5. PDMS layers bonding. (b) CMOS image sensor held by a needle to a wafer before PDMS is poured into the PVC ring to form the base layer.

FIG. 5.

(a) Assembled microfluidic device on the PCB. Channels have been filled with dyed water for contrast. (b) Another view of the microfluidic device showing the electrical connections from the embedded CMOS sensor to the PCB via bond wires.

4. CMOS Image Sensor

The CMOS image sensor is designed with Cadence and fabricated in a 0.18-μm CMOS process [FIG. 6(a)]. The sensor employs two rows of photosensitive pixels to convert luminescent signals into a readout voltage. Each row contains 10 pixels and the rows are separated by 900 μm to align to the microfluidic imaging channels. Each pixel is implemented as a 25 μm × 25 μm pn-junction diode in the bulk silicon. We had the custom silicon chip fabricated using an ON Semiconductor process. The custom sensor design allows easy integration with the microfluidic structure by having all of the wire bond pads on one side of the chip. It also has the same pitch between the pixel rows as that of the imaging channels for contact imaging alignment. The sensor’s circuit schematic is shown in FIG. 6(b). To generate an output signal, the pixel diode converts incident photons to a photocurrent, which is then integrated by the pixel capacitance to produce a voltage. The voltage is sensed by a buffer (M₁) and amplified by an on-chip op amp. The op amp gain can be set to either 1× or 10× by controlling the feedback switches S₁ and S₂. Finally, an off-chip analog-to-digital converter (ADC) digitizes the amplified voltage.

FIG. 6.

(a) Micrograph of the fabricated CMOS sensor. (b) CMOS sensor circuit schematic.

The op amp is implemented using a folded-cascode topology²³ to accommodate large voltage swings from the pixel (FIG. 7). FIG. 7 shows the op amp’s measured closed-loop gain as a function of frequency. The DC gains are −0.6 dB and 19.3 dB for the 1× and 10× modes, respectively. We employ correlated double sampling (CDS) to remove the reset noise and fixed-pattern noise (FPN) from the sensor output.²⁴

FIG. 7.

(a) Circuit schematic of the folded-cascode op amp. (b) Measured op amp gain.

5. Measurement Results

5.1. Microfluidic Control

To validate the functionality of the microfluidic device, we inject test samples into the channels and observe the fluid flow as the valves are actuated. FIG. 8(a) illustrates the test setup. A syringe pump dispenses dyed deionized water through polytetrafluoroethylene (PTFE) microbore tubing and 24-gauge fittings into the PDMS device. A compressed air source controlled by solenoid valves applies 20 psi pressure to actuate the valves. Because PDMS is gas permeable, direct pressurization of actuation chambers using air will result in valve malfunction. To avoid this problem, we fill the actuation chambers with deionized water prior to actuating with compressed air. Both the solenoid valves and the CMOS chip are controlled by an electronic pattern generator connected to a PC. FIG. 8(b) shows a close-up view of the contact-imaging system with installed tubing and electrical connections.

FIG. 8.

(a) Contact-imaging system test setup diagram. (b) Close-up view of the test setup.

We inject sample fluid through inlet IN1 and open valves V1, V2, and V3 while closing V4 to direct the fluid to imaging channel IC1 and then to outlet OUT1 [FIG. 9(a)]. The fluid is prevented from flowing to imaging channel IC2 by the closed valve V4, as visible in the image. Next, we open V4 by releasing its chamber pressure to permit the fluid to flow through imaging channel IC2 to OUT2 [FIG. 9(b)]. Note that the fluid is confined to within the channels thus verifying successful seal between the layers. The remaining valves are similarly tested and all confirmed to perform properly.

FIG. 9.

(a) Valve testing by injecting fluid through inlet IN1 with valve V4 closed and (b) with V4 open.

5.2. Optical Measurement

To directly compare the sensitivity of the CMOS image sensor to that of a PMT, we carefully set up identical test conditions for both and analyze their outputs while varying several test variables to observe trends. In addition, we validate the functionality of the contact-imaging system with actual luminescent samples. We describe the details of the experiments next.

First, we illuminate the CMOS image sensor with a 454-nm wavelength LED placed 11 mm away from the pixel surface. Only one pixel is read from the sensor. The power of the LED is adjusted to yield a sufficiently strong but unsaturated op amp output. Next, we use a power meter to measure the incident optical power, which is found to be 1.82 pW/μm². To filter out the high-frequency noise, we place a low-pass filter with a corner frequency of 500 Hz at the op amp output. FIG. 10(a) shows the measured output. The output resets to 0.98 V during the reset phase and ramps down to 0.35 V during the integration phase which lasts 200 ms. By subtracting the voltage at the end of the integration phase from the reset voltage, we obtain a CDS voltage. This process is repeated to obtain a set of voltages which then allows us to calculate the signal-to-noise ratio (SNR) as

$$SNR=10\text{log}\frac{{\displaystyle {\sum }_{i=1}^N{V}_i^2}}{{\displaystyle {\sum }_{i=1}^N{\left(V_i-{\mu }_V\right)}^2}}$$ (1)

where V_i is the voltage from the ith cycle, μ_V is the mean of the voltages, and N is the number of samples. For the PMT measurement, we employ the same setup to be able to make a direct comparison. Since our PMT, Hamamatsu H10720–01, has a different sensor area than the CMOS sensor, we fabricate a custom nickel-plated mask with an opening of 25 μm × 25 μm (the same size as a CMOS pixel) and place it over the PMT to admit the same photon flux as for a single CMOS pixel, thereby enabling a direct comparison between the performance of a single CMOS pixel sensor and the PMT when subjected to identical optical stimulus. The PMT is set for maximum gain (control voltage = 1 V). The masked area of the PMT does not generate noise because the ambient temperature is insufficient to eject electrons from the PMT’s scintillator. The PMT output is amplified by a transimpedance amplifier, Hamamatsu C5438–01, and filtered by a 500-Hz low-pass filter. FIG. 10(b) shows the measured PMT signal. Note that the waveform of the PMT is distinct from that of the CMOS due to the two sensors’ fundamental differences – the PMT operates in continuous time while the CMOS operates in discrete phases. Nonetheless, we can make a direct comparison by integrating the PMT output for the same amount of time (200 ms) as the CMOS sensor to obtain an equivalent voltage. This process is repeated to acquire a set of voltages, which allows us to calculate the PMT’s SNR using Eq. (1). FIG. 11(a) shows the result of this study for different integration times.

FIG. 10.

(a) CMOS sensor output showing four integration cycles and (b) PMT output for the same test conditions.

FIG. 11.

(a) SNR vs integration time for the CMOS sensor and PMT. (b) CMOS sensor SNR vs incident optical power. (c) CMOS sensor output voltage vs dye concentration of a 9,10-diphenylanthracene-based chemiluminescent solution for different integration times. The dashed lines denote the dark signal floor.

The CMOS sensor with a 100 ms integration time achieves an SNR of 40 dB at 1´ op amp gain and 45 dB at 10´ gain. The SNR improvement at 10´ is due to the suppression of off-chip noise when the op amp gain is high. The PMT meanwhile exhibits an SNR of 28 dB for the same integration time. Each SNR measurement increases at a rate of 10 dB/decade as the integration time increases due to noise averaging.²⁵ For integration times longer than 100 ms, the CMOS sensor’s SNR starts to taper off due to circuit saturation. The maximum CMOS SNR measured is 47 dB at 10´ gain and 200 ms of integration time. We note that the CMOS sensor’s SNR exceeds that of the PMT by about 17 dB across the integration time range, indicating, for the first time, that the CMOS image sensor can achieve significantly better SNR than the PMT in a contact-imaging application.

We analyze how the SNR varies with the incident optical power to understand the noise sources in the system. In this test, we vary the power of the LED by adjusting its bias current and measure the incident optical power with a power meter. We then plot the measured SNR of the CMOS sensor (at 1´ gain and 100-ms integration time) as a function of the incident power [FIG. 11(b)]. The resulting curve exhibits a 10-dB/decade slope, suggesting that the SNR is limited by shot noise rather than thermal noise.²⁶ The peak observed SNR is 50.4 dB at an incident power of 12.7 pW/μm².

To validate the contact-imaging system in a microfluidic environment, we fill the microfluidic imaging channels with chemiluminescent sample and measure the sensor output. The sample mixture consists of 1 mg of 9,10-diphenylanthracene (the dye), 25 mg of bis-[2,4,5-trichloro-6-(pentyloxycarbonyl) phenyl] oxalate (CPPO), 50 mg of sodium acetate, 1 ml of 30% hydrogen peroxide, and 5 ml of diethyl phthalate. The chemiluminescent intensity is varied by diluting the dye component. The measurements are performed immediately after dye mixing to minimize errors due to chemiluminescence decay. Measurements are typically completed within a few minutes of mixing, while the 1/e time for chemiluminescent decay is approximately 30 minutes. FIG. 11(c) shows the CMOS output as a function of the dye concentration for different integration times. The output increases from 20 mV to 800 mV as the dye concentration is increased from 25 μM to 500 μM for 8 s of integration time. We also observe that the output increases with longer integration times, as expected. The minimum detectable concentration is 25 μM, limited by the pixel’s dark signal.²⁴ The dark signal levels are measured with no dye present in the device, and are denoted by the dotted lines in FIG. 11(c). Note that the sensitivity is dependent on the underlying chemistry of the chemiluminescent system (i.e., the photon production rate as a function of chemical constituent concentration). Other chemiluminescent systems will have different concentration sensitivities.

6. Conclusion

We have presented the design and characterization of a hybrid PDMS-CMOS-FR4 contact-imaging system. The system embeds the CMOS image sensor directly in a PDMS layer instead of a chip package to allow large-scale microfluidic structures to be integrated. The sensor is wire-bonded to the PCB without the need of delicate epoxy application. The PDMS layers in our contact-imaging systems are fabricated using lithography and assembled to form a network of channels, valves, chambers, and inlets/outlets. The CMOS image sensor contains two rows of pixels with readout buffers, a programmable-gain amplifier, and logic control. Owing to the flexibility afforded by the integration process, the device demonstrates, for the first time, integrated valves in a contact-imaging system. We have also demonstrated the first direct comparison of the sensitivity of a custom CMOS image sensor and a PMT in a contact-imaging environment. Using a calibrated light source, the CMOS image sensor achieves 17 dB better SNR than the PMT across a broad range of integration times, with a maximum SNR of 47 dB at the 10× gain mode and 200 ms of integration time. Chemiluminescent testing successfully shows signal detection for different analyte concentrations and integration times. The contact-imaging system demonstrates a detection limit of 25 μM of a 9,10-diphenylanthracene-based solution.

Biography

Andres M. Galan was born in Machala, Ecuador. He received his B.S. and M.S. degrees in 2015 and 2017 respectively, with a minor in Business Administration from Brigham Young University. In 2014, he worked as a PCB Design and Test Engineer at Braven Speakers. He is currently working as a SOC Design Engineer with an emphasis in analog and digital circuits at Intel Corporation. His research interests are CMOS image sensors, power gates, memory IO and PLL integrated circuit design.

Gregory P. Nordin received degrees in physics (BS, 1984, BYU and MS, 1986, UCLA) and electrical engineering (PhD, 1992, University of Southern California). He worked at the Hughes Aircraft Company 1984–1992. From 1992 to 2005, he was at the University of Alabama in Huntsville, and since 2005 has been at Brigham Young University. His research focuses on 3-D printing for microfluidics, and micro- and nanofabricated devices for biosensing, photonics, and MEMS.

Shiuh-hua Wood Chiang received degrees in computer engineering (B.S., 2007, University of Waterloo) and electrical engineering (M.S., 2009, University of California, Irvine and Ph.D., 2013, UCLA). He was a Senior Engineer at Qualcomm (2013–2014). He joined Brigham Young University in 2014. He is currently the director of the Micropower Circuits Laboratory. His research interests include RF/analog/mixed-signal integrated circuits.