Lithium ion trapping mechanism of SiO₂ in LiCoO₂ based memristors

Abstract

Pt/LiCoO₂/SiO₂/Si stacks with different SiO₂ thicknesses are fabricated and the influence of SiO₂ on memristive behavior is investigated. It is demonstrated that SiO₂ can serve as Li ion trapping layer benefiting device retention, and the thickness of SiO₂ must be controlled to avoid large SET voltage and state instability. Simulation model based on Nernst potential and diffusion potential is postulated for electromotive force in LiCoO₂ based memristors. The simulation results show that SiO₂ trapping layer decreases the total electromotive field of device and thereby prevents Li ions from migrating back to LiCoO₂. This model shows a good agreement with experimental data and reveals the Li ion trapping mechanism of SiO₂ in LiCoO₂ based memristors.

Introduction

Boasting high memory density and energy efficiency, memristors are promising alternatives to complementary metal oxide semiconductors (CMOS) for high-density storage and high-performance computing^1–3. Neural networks based on crossbar arrays of filamentary memristors or phase change memories have been reported and successfully implemented in image recognition and word classification^4–9. Despite significant progresses, these devices still suffer from several limitations such as excessive “write” noise as well as high switching voltages and currents^10–12. LiCoO₂ based memristors are expected to overcome several limitations. A major advantage of LiCoO₂ based memristors is that the intercalation and extraction of Li ions in LiCoO₂ are highly reversible leading to high device stability^13,14. Moreover, Li ions migration in LiCoO₂ based memristors is similar to information exchange processes between synapses and neurons in the brain¹⁵. With a low energy barrier for Li ions transporting, LiCoO₂ based memristors have a smaller threshold voltage and are expected to satisfy low-power consumption requirement in high performance computing^16,17.

Generally, LiCoO₂ based memristors operate by a common electrochemical reaction between LiCoO₂ and Si^18,19. The conductivity of LiCoO₂ changes as a function of Li ions concentration^20,21. Under a positive electrical field, Li ions migrate from LiCoO₂ to Si and the variation of Li ions concentration in LiCoO₂ produces a resistive switching (RS) behavior. The RS processes corresponding to Li ions migration out of Li-based oxide have been experimentally verified^22,23. Furthermore, the electrochemical reaction between LiCoO₂ and Si produces an electromotive force (EMF) which in LiCoO₂ based memristors can cause electrical short circuit between Li_xCoO₂ and Li_xSi decreasing device retention²⁴. It has been reported that SiO₂ between LiCoO₂ and Si can work as solid state electrolyte allowing transport of Li ions and trap Li ions when external voltage is removed thus increasing device retention^23,24. SiO₂ has been also reported to be a promising candidate for the electrolyte or controllable barrier layer in CMOS and Li-ion batteries, which can be used to modulate the Li ions transporting^23–27. However, the influence of SiO₂ on memristive behavior in LiCoO₂ based memristors has not been investigated and the Li ion trapping mechanism of SiO₂ in LiCoO₂ based memristors remains to be revealed.

In this work, Pt/LiCoO₂/SiO₂/Si stacks with different SiO₂ thicknesses are produced and the corresponding memristive properties such as electrical properties, stabilities and retentions are investigated. SiO₂ serves as a trapping layer for Li ions and is favorable for device retention. It is also necessary to control the SiO₂ thickness to an appropriate range for higher durability and state stability. A simulation model for EMF in LiCoO₂ based memristors is proposed to explain the influence of SiO₂ on Pt/LiCoO₂/SiO₂/Si stacks. The origins of EMF include Nernst potential and diffusion potential. Thus, this model is based on Nernst potential and diffusion potential and the total electromotive fields of device are calculated. It can be seen that SiO₂ trapping layer can decrease electromotive field of Pt/LiCoO₂/SiO₂/Si stacks. This model is consistent with the experimental results and reveals the Li ion trapping mechanism of SiO₂ in LiCoO₂ based memristors.

Methods

The 40 nm LiCoO₂ films were deposited on highly doped p-type Si (111) or SiO₂/Si substrates by pulse laser disposition (PLD) using a stoichiometric LiCoO₂ target. LiCoO₂ layer was fabricated in O₂ (10 Pa) atmosphere at 550 °C to obtain R-3m LiCoO₂ phase through a KrF laser (LightMachinery IPEX-800, λ = 248 nm and τ = 25 ns) operated at 3 Hz with a fluence of ≈1.3 J cm⁻². SiO₂ layers were formed by thermal oxidization in an oxygen environment at 900 °C. The thickness of SiO₂ layer was determined by profilometry. The SiO₂ layers had thicknesses of 10 nm, 20 nm and 40 nm ($d_{Si{O}_2}:d_{LiCo{O}_2}=1:4,1:2,1:1$) in order to investigate the influence of the SiO₂ thickness on the memristive behavior of Pt/LiCoO₂/SiO₂/Si stacks. The LiCoO₂ deposition was carried out under same conditions to obtain same Li ions concentration and layer thickness. To avoid introducing other metal ion such as Ag⁺ or Cu²⁺, noble Pt was used as the top electrodes. The 80 nm thick Pt top electrodes were prepared by magnetron sputtering in pure Ar with a metal mask covering the LiCoO₂ layer. The diameter of the top electrode was 1 mm.

The electrical and memristive properties were measured by the voltage sweeping mode on Keithley 4200-SCS semiconductor parameter analyzer at room temperature. The voltages were applied to the Pt top electrode with Si substrate grounded. The cycle tests were collected continually by the direct-current (DC) voltage sweeping mode. The retention tests were conducted after the devices switching to LRS, and the read voltage is 0.1 V. The LiCoO₂ layers were analyzed with a LabX XRD-6000 using Cu Kα radiation and operating at 40 kV and 30 mA. The scanning rate was 5°/min.

Results

The Pt/LiCoO₂/SiO₂/Si stacks with different SiO₂ thicknesses of 10 nm, 20 nm and 40 nm are fabricated and samples without SiO₂ are also prepared for comparison. The corresponding I-V curves of different samples are shown in Fig. 1. The I-V curve of sample (a) displays gradual RS processes without definite V_set and V_reset, corresponding to homogeneous RS in LiCoO₂²⁴. On the contrary, samples (b), (c) and (d) exhibit abrupt current increases similar to RS behavior of electrochemical metallization (ECM)¹⁰, as shown in Fig. 1(b–d) (More I-V curves during cycle tests are shown in supporting information, Fig. S3). Hence, samples with and without SiO₂ characterize different memristive properties which may be attributed to different transport processes of Li ions in SiO₂ and LiCoO₂.

Figure 1.

I-V curves of samples with different SiO₂ thicknesses.

In order to investigate the device stabilities, durability tests are conducted on the different samples. As shown in Fig. 2, the V_SET and V_RESET of samples with 20 nm are more stable. To evaluate the dispersion degree, corresponding coefficients of variation (C_V) are calculated. C_V is defined by²⁸

$${\mathrm{C}}_V=\frac{\sigma }{\mu }$$ 1

where σ is the standard deviation and μ is the average of several data. The ranges of SET voltage and C_V of different samples are summarized in Table 1 (For each SiO₂ thickness, 15 points of the sample are measured). Samples with 20 nm show smaller C_V than other samples consistent with Fig. 2. To study state stability, the resistances of different samples at HRS and LRS for 128 cycles are also measured. Figure 3 plots the R_HRS and R_LRS of different samples during 128 cycles. The R_HRS of samples (a) and (b) show two orders of magnitude fluctuations while those of samples (c) and (d) are within one order of magnitude. The R_LRS of sample (c) shows the smallest fluctuation. The C_V of R_HRS and R_LRS are also calculated in Table 2 (For each SiO₂ thickness, 15 points of the sample are measured). As the SiO₂ thickness is increased, C_V of R_HRS decreases and sample (c) has the smallest C_V of R_LRS. However, sample (d) shows several RS failures during the durability test. Hence, samples with 20 nm SiO₂ characterize the best stability. SiO₂ with appropriate thickness is favorable for state stability but SiO₂ that is too thick decreases the state stability.

Figure 2.

V_SET and V_RESET of samples with different SiO₂ thicknesses (128 cycles).

Table 1.

The SET voltage, RESET voltage and corresponding coefficients of variation (C_V) of in samples with different SiO₂ thickness.

Thickness (nm)	VSET (V)	VSET CV	VRESET (V)	VRESET CV
0	—	—	—	—
10	2.62~6.82	0.17	−2.81~−6.97	−0.07
20	3.24~6.93	0.14	−3.2~−6.38	−0.08
40	3.42~6.21	0.18	−2.03~−4.28	−0.23

Figure 3.

R_HRS and R_LRS of samples with different SiO₂ thicknesses (128 cycles).

Table 2.

The HRS, LRS and corresponding coefficients of variation (C_V) of in samples with different SiO₂ thicknesses.

Thickness (nm)	HRS (Ω)	HRS CV	LRS (Ω)	LRS CV
0	107~108	0.59	103~104	0.97
10	106~107	0.46	103~105	1.01
20	108	0.44	103~104	0.80
40	107	0.13	103~106	0.95

Retention of Pt/LiCoO₂/SiO₂/Si stacks with different SiO₂ thicknesses is also assessed at a read voltage of 0.1 V to evaluate ability of data storage. Figure 4 shows that Pt/LiCoO₂/SiO₂/Si stacks without SiO₂ maintain retention characteristic of ~10³ s whereas samples with SiO₂ show good retention characteristics up to 10⁵ s. As SiO₂ thickness is increased, device retention increases from 10⁴ to 10⁵ s. In terms of Pt/LiCoO₂/SiO₂/Si stacks, EMF mainly drives Li ions from Si to LiCoO₂ without an external voltage and therefore, SiO₂ can decrease the influence of EMF on Pt/LiCoO₂/SiO₂/Si stacks leading to high retention.

Figure 4.

Retention tests of samples with different SiO₂ thicknesses at a read voltage of 0.1 V.

Discussion

To understand the mechanism of trapping of Li ions in SiO₂, it is necessary to investigate the Li ions transporting processes in the Pt/LiCoO₂/SiO₂/Si stacks. The schematic of Pt/LiCoO₂/SiO₂/Si stacks and Li ions transporting processes are shown in Fig. 5(a). The Li ions transporting processes in LiCoO₂, SiO₂ and Si have been experimentally verified and reported for Li-ion battery^22,24–26. The electrochemical reactions involving Li ions in Pt/LiCoO₂/SiO₂/Si stacks are as follows:

$$LiCo{O}_2-\left(1-x_1\right)e^{-}\leftrightarrow L{i}_{x_1}Co{O}_2+(1-x_1)L{i}^{+}$$ 2

$$Si{O}_2+x_{2}L{i}^{+}+x_2{e}^{-}\leftrightarrow L{i}_{x_2}Si{O}_2$$ 3

$$Si+x_{3}L{i}^{+}+x_3{e}^{-}\leftrightarrow L{i}_{x_3}Si$$ 4

At a positive voltage, Li ions are extracted from LiCoO₂ and migrate in the interval positions of SiO₂ finally forming Li_xSi in Si substrate. The LiCoO₂ acts as Li ions source and RS layer, SiO₂ allows Li ions transportation, and Si is used to store Li ions. The LiCoO₂ layers are annealed at 550 °C to obtain R-3m phase (seen in Fig. S1) which is hexagonal layered structure with a uniform Li ions distribution^19,20. Owing to the uniform Li ions distribution in crystalline R-3m LiCoO₂, the RS processes occur in the entire LiCoO₂ layer displaying gradual current changes. In contrast to layered structure LiCoO₂, SiO₂ is amorphous with non-uniformity, and the Li ions intercalation processes are inhomogeneous and occur in some partial regions of SiO₂. Therefore, the memristive behavior of samples without SiO₂ shows gradual current changes while samples with SiO₂ exhibit abrupt resistance jumps. Furthermore, it has been reported in Li-ion batteries that insertion of Li ions in Si strongly strains the crystalline lattice thus harming the device stability, the SiO₂ can work as a buffer layer to decrease the crystalline lattice stress^22,29 and trap Li ions decreasing resistance degradation without an external voltage^23,24. However, thin SiO₂ layer (≤10 nm) is generally rough exhibiting non-uniformity²⁷, which may be adverse to device stability as shown in Fig. 3(b). And too thick SiO₂, such as 40 nm, exhibit stronger Li ion trap effect which can cause several set failures and reduced performances, as shown in Fig. 3(d). Hence, SiO₂ with the appropriate thickness improves the device stability.

Figure 5.

(a) Schematic of Pt/LiCoO₂/SiO₂/Si stacks and Li ions transportation processes; (b) Origins of electromotive force (EMF) in Pt/LiCoO₂/SiO₂/Si stacks (d₂ ≤ D); (c) Origins of EMF in Pt/LiCoO₂/SiO₂/Si stacks (D < d₂)

After applying a positive voltage, Li ions transport from LiCoO₂ to Si resulting in EMF between LiCoO₂/SiO₂ interface ($s\prime$) and SiO₂/Si interface ($s″$). Two factors mainly contribute to the EMF: (a) Nernst potential V_N and (b) diffusion potential V_d³⁰. SiO₂ works as a Li ion trapping layer allowing Li ions to transport at a positive voltage while trapping Li ions and avoiding resistance degradation without an external voltage. According to the different SiO₂ thickness (d₂), two origins of EMF in Pt/LiCoO₂/SiO₂/Si stacks are shown in Fig. 5(b) and (c). When d₂ ≤ Critical poin (D), SiO₂ undergoes fully lithiation and exhibits homogeneous Li ions distribution, as shown in Fig. 5(b), and V_EMF = V_N. When d₂ > D, the SiO₂ acts as a RS layer and has an inhomogeneous Li ions distribution as shown in Fig. 5(c), V_EMF = V_N + V_d. Therefore, the influence of SiO₂ trapping layer on EMF can be divided into two regions. According to the range of x₁ in ${\mathrm{Li}}_{{\mathrm{x}}_1}{\mathrm{CoO}}_2$ and x₂ in ${\mathrm{Li}}_{{\mathrm{x}}_2}{\mathrm{SiO}}_2$, the range of D between region I and region II can be calculated to be $6.96\mathrm{nm}<\mathrm{D}<13.91\mathrm{nm}$(Calculation processes are shown in Supplementary Information). Figure 6(a) shows different tendencies in 0~10 nm region and 10~40 nm region. When $0\mathrm{nm}<{\mathrm{d}}_2\le 10\mathrm{nm}$, the device retention rises rapidly with increasing SiO₂ thickness and when $10\mathrm{nm}<{\mathrm{d}}_2\le 40\mathrm{nm}$, device retention rises slightly with increasing SiO₂ thickness, indicating that D is near to 10 nm which is consistent with the calculation. This can also explain the abnormal tendency of HRS in Figs. 1 and 3. The HRS of devices mainly consist of ${\mathrm{R}}_{{\mathrm{Li}}_{\mathrm{x}}{\mathrm{CoO}}_2}$ and ${\mathrm{R}}_{{\mathrm{Li}}_{\mathrm{y}}{\mathrm{SiO}}_2}$. For samples without SiO₂, Li ions transport back to LiCoO₂ after reset process and ${\mathrm{R}}_{\mathrm{HRS}}\approx {\mathrm{R}}_{{\mathrm{LiCoO}}_2}$. For samples with SiO₂, the SiO₂ would trap large amount of Li ions during reset process resulting in decrease of Li ion concentration in LiCoO₂ and the retained Li ions in SiO₂ enhance the conductivity. Therefore, the HRS of Pt/LiCoO₂/SiO₂ (10 nm)/Si is lower than Pt/LiCoO₂/Si. Moreover, 10 nm SiO₂ undergoes full lithiation while 20 nm and 40 nm SiO₂ undergo partly lithiation. Full lithiated SiO₂ would retain higher Li ion concentration and cause lower Li ion concentration in LiCoO₂ and higher conductivity. Furthermore, thicker SiO₂ means larger Li ion storage and stronger Li ion trap effect leading to lower Li ion concentration in LiCoO₂, which may cause that the HRS of samples with 40 nm SiO₂ is lower than that of samples with 20 nm SiO₂.

Figure 6.

(a) Experimental device retention as a function of SiO₂ thickness (2 different regions are observed); (b) Simulated E-d₂ characteristics in Pt/LiCoO₂/SiO₂/Si stacks without an external voltage (d₂ ≤ 10 nm); (c) Simulated E-d₂ characteristic in Pt/LiCoO₂/SiO₂/Si stacks without an external voltage (10 nm < d₂ ≤ 40 nm)

The device retention is mainly relative to the electromotive field (E = V_EMF/d₂), thus the E-d₂ characteristics are discussed. In region I, SiO₂ behaves as solid-state electrolyte exhibiting a homogeneous Li ions distribution and V_EMF = V_N. EMF drives Li ions migration from Li_xSi to Li_xCoO₂ and the main electrochemical reactions are as follows:

$$C{o}^{4+}+e^{-}\leftrightarrow C{o}^{3+}(Interfaces\prime )$$ 5

$$L{i}^{+}+e^{-}\leftrightarrow Li(Interfaces″)$$ 6

The Nernst potential is given by³⁰:

$$V_N=V_{s\prime }-V_{s″}=V^0+\frac{kT}{e}ln\frac{a_{C{o}^{4+}}\cdot a_{Li}}{a_{C{o}^{3+}}\cdot a_{L{i}^{+}}}$$ 7

$V^0$ is the difference in the standard potentials of these reactions, k is Boltzmann constant, T is temperature, e is electron charge, $a_{M^{z+}}$ denote the activity of the cations (a = γc, γ is activity coefficient). The amount of Li ions in Pt/LiCoO₂/SiO₂/Si stacks is constant:

$$c_0{d}_{1}S=c_1{d}_{1}S+c_2{d}_{2}S+c_3{d}_{3}S$$ 8

where c₀ denotes the initial concentration of Li ions in LiCoO₂, c₁, c₂ and c₃ are the concentration of Li ions in Li_xCoO₂, SiO₂ and Si, S is the cell size. d₁, d₂ and d₃ are the thicknesses of LiCoO₂, SiO₂ and Si, respectively. The concentration of Li ions can be defined as $c=\frac{\frac{\rho V}{M}}{V}=\frac{\rho }{M}$ ($\rho$ is mass density, V is volume and M is the molar mass). Equation (8) can be written by:

$$\frac{{\rho }_1}{M_1}{d}_1=\frac{{\rho }_1}{M_1}{d}_1{x}_1+\frac{{\rho }_2}{M_2}{d}_2{x}_2+\frac{{\rho }_3}{M_3}{x}_3{d}_3$$ 9

where ρ₁, ρ₂ and ρ₃ are mass densities of LiCoO₂, SiO₂ and Si, respective. M₁, M₂ and M₃ are molar mass of LiCoO₂, SiO₂ and Si, respectively. x₁, x₂ and x₃ are the atomic percent in $L{i}_{x_1}Co{O}_2$, $L{i}_{x_2}Si{O}_2$ and $L{i}_{x_3}Si$. Due to low concentration of Li ions in LiCoO₂ and SiO₂ and small molar mass of lithium, the influences of Li ions on $\rho andM$ are neglected. Thus, $c_{C{o}^{4+}}=\frac{{\rho }_1}{M_1}(1-x_1)$, $c_{C{o}^{3+}}=\frac{{\rho }_1}{M_1}{x}_1$, $c_{L{i}^{+}}=\frac{{\rho }_2}{M_2}{x}_2$, $c_{Li}=\frac{{\rho }_3}{M_3}{x}_3$. Based on Equation (9) and γ assumed to be one, the electromotive field in region I (E₁ = V_EMF/d₂) can be calculated by:

$$E_1=\frac{V^0}{d_2}+\frac{kT}{e{d}_2}ln\frac{(1-x_1)\left[\frac{{\rho }_1}{M_1}{d}_1(1-x_1)-\frac{{\rho }_2}{M_2}{d}_2{x}_2\right]}{x_1{d}_3\cdot \frac{{\rho }_2}{M_2}{x}_2}$$ 10

To facilitate the discussion of EMF, reference values are chosen according to previous reports, $x_1=0.7$, ${\rho }_1=2.5g/c{m}^3$, ${\rho }_2=2.648g/c{m}^3$, ${\rho }_3=2.329g/c{m}^3$, $M_1=97.87g/mol$, $M_2=60.086g/mol$,$M_3=28.085g/mol$, $V^0=3.6V$, $x_2=2/3$^13,21,31,32. The thickness of different layers are measured, $d_1=40nm$, $d_3=550\mathrm{\mu }m$. D is simulated to be 10.43 nm, and the simulated E-d₂ characteristics are shown in Fig. 6(b). E₁ decreases rapidly with d₂, and thereby device retention rises rapidly with increasing SiO₂ thickness.

In region II, SiO₂ acts as a RS layer and V_EMF = V_N + V_d. The main electrochemical reactions are as follows:

$$C{o}^{4+}+e^{-}\leftrightarrow C{o}^{3+}(Interfaces\prime )$$ 11

$$S{i}^{4+}+e^{-}\to S{i}^{3+}(Interface{s}^{″})$$ 12

Nernst potential is given by³⁰

$$V_N=V_{s\prime }-V_{s″}=V^0+\frac{kT}{e}ln\frac{a_{C{o}^{4+}}\cdot a_{S{i}^{3+}}}{a_{C{o}^{3+}}\cdot a_{S{i}^{4+}}}$$ 13

Similarly, the amount of Li ions in Pt/LiCoO₂/SiO₂/Si stacks is constant:

$$c_0{d}_{1}S=c_1{d}_{1}S+c_2{d}_{2}S$$ 14

It can be also written as:

$$\frac{{\rho }_1}{M_1}{d}_1\left(1-x_1\right)=\frac{{\rho }_2}{M_2}{d}_2{x}_2$$ 15

The Li ions distribution in SiO₂ is inhomogeneous, to simply the Li ions distribution in SiO₂, it is assumed that Li ions in SiO₂ follows constant-total-dopant diffusion and the Li ions distribution in SiO₂ can be defined by³³:

$$c\left(y,t\right)=\frac{Q}{\sqrt{\pi D\prime t}}\exp (-\frac{y^2}{4D\prime t})$$ 16

where Q is dopant number of average area, D′ is the diffusion coefficient, t is the diffusion time and y is the depth. Assuming diffusion length is equal to SiO₂ thickness $(L=\sqrt{D^{\text{'}}{t}_1}=d_2)$, the total dopant is the amount of Li ions extracted from LiCoO₂, thus $Q=(1-x_1)\frac{{\rho }_1}{M_1}{d}_1$. Herein, $c_{C{o}^{3+}}=\frac{{\rho }_1}{M_1}{x}_1$, $c_{C{o}^{4+}}=\frac{{\rho }_1}{M_1}(1-x_1)$, $c_{S{i}^{3+}}=c_{L{i}^{+}}=$ $c\left(d_2,t_1\right)=\frac{(1-x_1)\frac{{\rho }_1}{M_1}{d}_1}{\sqrt{\pi }{d}_2}\exp (-\frac{1}{4})$, $c_{S{i}^{4+}}=\frac{{\rho }_2}{M_2}-c_{S{i}^{3+}}$. Based on Equations (15, 16) and assuming γ = 1, the electromotive field (E_N) originating from Nernst potential can be calculated by:

$$E_N=\frac{V^0}{d_2}+\frac{kT}{e{d}_2}ln\frac{{\rho }_1{M}_2{d}_1{(1-x_1)}^2\exp (-\frac{1}{4})}{x_1\left[\sqrt{\pi }{\rho }_2{M}_1{d}_2-\exp (-\frac{1}{4}){\rho }_1{M}_2{d}_1(1-x_1)\right]}$$ 17

In region II, V_d should be also taken in account. The diffusion potential formula is given by³⁰:

$$V_d=-\frac{kT}{e}\overline{t}ln\frac{a_{s^{\text{'}}}}{a_{s^{\text{'}\text{'}}}}$$ 18

where $\overline{t}$ is ion transference number averaged throughout layer thickness, $a_{s^{\text{'}}}$ is the activity of Li ions at LiCoO₂/SiO₂ interface and $a_{s^{\text{'}}}$ is the activity of Li ions at SiO₂/Si interface. According to Equation (16), $c_{s^{\text{'}}}=c\left(0,t_1\right)$ and $c_{s^{\text{'}\text{'}}}=c\left(d_2,t_1\right)$. The remaining reference values are $\overline{t}=0.4$, $T=298K$³⁰. Assuming γ = 1, the diffusion potential ($V_d$) is calculated to be −2.5 × 10⁻³ V, which is much less than V_N, meaning that V_d can be neglected. Thus V_EMF ≈ V_N, reference values are $x_1=0.7$, ${\rho }_1=2.5g/c{m}^3$, ${\rho }_2=2.648g/c{m}^3$, $M_1=97.87g/mol$, $M_2=60.086g/mol$, $V^0=1.4V$^13,21,31. The simulated E₂-d₂ characteristics are presented in Fig. 6(c), $E_2$ decreases with increasing of the SiO₂ thickness. Thus, SiO₂ works as a Li ion trapping layer. When external voltage is removed, the SiO₂ trapping layer decreases the total electromotive field of device and maintains the states resistances.

With external voltage, Li ions transport from LiCoO₂ to SiO₂ and Si layers, which can produce a V_EMF and exhibit a nanobattery-like behavior. The phenomenon is similar to the observation reported in other redox-based memristors^23,24,34,35. It has also been demonstrated that V_EMF is dependent on the chemistry and the transport properties of the materials system^30,36,37. Thus, Li ion trapping mechanism, especially the relationship between electromotive field and SiO₂ thickness in different regions, may be also adapted to other devices based on LiCoO₂ and SiO₂ material system such as Li-ion batteries and Li-ion based transistors. The critical point is actually relative to thickness and Li ion concentration of LiCoO₂ layer, may change with fabrication parameters of devices.

Conclusion

The influence of SiO₂ trapping layer on memristive behavior of Pt/LiCoO₂/SiO₂/Si stacks is investigated in terms of electrical properties, device stability and retention. For the LiCoO₂ based memristors, the trapping layer benefits device retention. It is necessary to control the thickness of trapping layer to improve device properties. A model based on Nernst potential and diffusion potential is proposed to elucidate the Li ion trapping mechanism in SiO₂ and two different relationships between the electromotive field and SiO₂ thickness are found. According to this model, SiO₂ trapping layer decreases the total electromotive field of device and hence prevents Li ions from migrating back to LiCoO₂. These findings reveal the Li ion trapping mechanism of SiO₂ in LiCoO₂ based memristors and provide insights into the performance improvement of memristors and other devices based on LiCoO₂ and SiO₂.

Author Contributions

Q.H. and R.M.L. contributed equally to this work. Q.H. and R.M.L. fabricated the devices, performed electrical measurement and film characterizations; R.M.L., Q.H., X.J.Z. and A.P.H. proposed the simulation model; All authors (including Q.G., M.W., H.L.S., Z.S.X.) discussed the results; Q.H. and R.M.L. wrote the main manuscript text and prepared figures and tables with the help of P.K.C. and A.P.H.; All authors reviewed the manuscript.

Data Availability

The datasets generated and analysed during the current study are available from the corresponding author.

Competing Interests

The authors declare no competing interests.

Additional information

Supplementary information accompanies this paper at 10.1038/s41598-019-41508-3.