A Thermal Model of the LabPET II ASIC

Abstract

The LabPET II detection module is the building block of PET scanners for ultra-high-resolution imaging of small to mid-sized animals and the human brain. For optimal performance, it must be operated at a stable temperature. The detection module is composed of four APD-LYSO detector arrays with two flip-chip ASICs mounted on the backside of an interposer generating 550 mW each. Currently, the scanner architecture includes an air cavity around the electronics and smaller cavities close to the detectors. Cooling down the front-end electronics located in these small cavities becomes problematic as the number of modules increases to address the different targeted configurations of the LabPET II scanners from mouse to human brain geometries. A basic knowledge of the heat distribution is necessary to develop an efficient thermal management in all cases. The aim of this work is to build a model of the LabPET II ASIC and associated PCB for enabling heat flow simulations and circumscribe the thermal management requirements. The Flow Simulation module (SolidWorks), was used to build the thermal model. The ASIC and the interconnection with the PCB were reproduced accurately while some adjacent structures were simplified to ease the simulation burden. The model was applied to simulate three different configurations of printed-circuit boards carrying the ASICs and other components where a fan is turned on/off to create a forced airflow. Each simulation was compared to some experimental measurements. A temperature difference of less than 5 degree Celsius between the simulations and experimental measurements is noticed, giving confidence that the thermal model of the ASIC is valid and transferable to different mechanical assemblies.

1. Introduction

The LabPET II detection technology was designed to achieve ultra-high-resolution positron emission tomography (PET) imaging from small to mid-sized animals and of the human brain [1–4]. The scanners are typically built with a main board supporting coincidence processing on which FPGA-based embedded signal processing unit (ESPU) boards are mounted radially. Each ESPU board contains from 4 to 18 Adapter Boards (AB) aligned linearly in the axial direction to connect Detector Modules (DM) (Fig. 1). Each DM includes four 4 × 8 Avalanche Photodiode (APD)-based arrays coupled one-to-one to 1.12 × 1.12 mm² LYSO crystals at a 1.2 mm pitch, with the signals individually routed through a Daughter Board (DB) interposer to two 64-channel, 4.6 × 5.9 mm² 180nm-CMOS Application-Specific Integrated Circuits (ASIC) [1–3].

Figure 1:

Pictures of the different components of the LabPET II scanner, (a) The detector module (DM) with four APD-LYSO detector arrays and two ASICs, (b) the embedded signal processing unit (ESPU) shown here with 8 adapter boards/detection module (AB/DM), and (c) the geometry of a mid-sized animal-dedicated LabPET II scanner with 36 ESPUs.

The APD-based detector technology is known to be highly temperature dependent [5–7]. For optimal performance, the APD requires a stable operational temperature close to the room temperature. With a power dissipation of 550 mW each, in close proximity to the APD arrays, the two ASICs represent the major heat source in the front-end electronics. The ASICs embed temperature sensors to monitor the DM temperature in any location of the scanner.

Currently, the scanner architecture allows air gaps between the radially disposed ESPUs, but the volume of these air gaps is reduced and becomes more confined as the radial and axial field-of-view (FOV) of the scanners is increased. Considering the complexity of the front-end assembly, a finite element simulation is required to build a thermal model of the ASIC and to understand the heat dissipation process of the DM. Such a model will enable thermal management solutions to be elaborated and simulated before their implementation.

This work proposes a simplified thermal representation of the ASIC soldered on a printed-circuit board (PCB) that will be applicable to all LabPET II scanner geometries and boards. The thermal model is developed with the SolidWorks software (v.18.5) and simulated in 3D with the Flow Simulation module (v.18) [8, 9]. The simulation results of three different PCBs including ASICs axe compared to experimental measurements with the same conditions to validate the model.

2. Materials

A realistic approach with the detailed description of all elements of the ASIC and PCB would require excessive computational resources. The model was built and simplified iteratively to decrease the required resources while accounting for the most salient features of the complex DM assemblies. For instance, since objects with a circular shape (ex. vias) require expensive simulation resources even for small and simple components, they were substituted with rectangular shapes of equivalent area. The next subsections will describe how the model was created for the different components of the DM, by detailing the material assignment and thermal data required for the simulations.

2.1. Flow Simulation

SOLIDWORKS Flow Simulation is a CAD-Embedded Computational Fluid Dynamics (CFD) analysis software that is fully embedded in the mechanical design environment [10, 11]. It is based on a Cartesian meshing implemented directly on the native CAD geometry [10]. The software integrates some CFD solvers using a discrete numerical technique based on the Finite Volume (FV) method and a boundary layer treatment technology that allows to use a relatively coarse Cartesian-based mesh. Coupling interface and approximation models, as Two-Scales Wall Functions (2SWF) or cell-centered FV method, are automatically used locally to compensate if the mesh is not fine enough for a full 3D modelling. This combines advantages of approaches based on regular grids and ones with highly accurate representation of geometries boundaries.

In the following simulations, the solver was used as a black box with all parameters set to automatic. To help the automatic mesh building considering the high scaling size between the smallest part (5 μm) and the entire model (40 cm), the initial minimum gap size is set to 600 μm, as recommended in the technical reference book [11]. This allowed the full simulation of a PET scanner dedicated to small animals to fit inside 32 GB of RAM. This parameters can be set to 300 μm and 1 mm without significant difference in the results. The 600 μm gap value was selected to reduce the computational memory resource.

2.2. Thermal model of the DM

2.2.1. Thermal model of the ASIC

A simplified thermal model of the ASIC was implemented as a 10 μm aluminum layer between two silicon layers of 5 and 335 μm. The Ball Grid Array (BGA) at the bottom of the ASIC was represented by a single 60 μm x 60 μm line of SAC305 (Sn96Ag3.5Cu.5) conductor having the same total contact area as the BGA, surrounding a 5000 × 3800 × 60 μm³ layer of epoxy underfill (301–2, Epotek, USA) filling the space at the bottom of the ASIC (Fig. 2).

Figure 2:

3D rendering of the simulated ASIC chip (left) and zoomed side view (right). All dimensions are in millimeter.

2.2.2. Thermal model of PCB and electronic components

PCBs, connectors, FPGAs and clock buffers are modeled by a parallelepipoid with/without heat source assignment depending on the component. Other PCB components that are expected to have little effect on heat diffusion are ignored and not represented. Flow Simulation functions were assigned to these components, that is, the connector function to the connector, Flip Chip Ceramic Ball Grid Array (FC CBGA) and Quad Flat No-Lead (QFN) package functions to FPGA and clock buffers, respectively. Printed-circuit functions, which use a copper filling factor approximation, are applied to the PCBs. The copper layer in contact with the ASIC is reproduced as is because of its importance for transverse heat distribution. PCB and connector functions are adjusted to the estimated conduction values as specified in Table 1.

Table 1:

Package function used in simulation model.

Part	Physical material	Simulated function
Printed-circuit	FR4 (XX layers)1	PCB function with XX layers1
FPGA	FPGA with BGAs	FC CBGA package function
Clock buffers	QFN chips	QFN package function
Fan	3615KL-05W-B50	3615KL-05W-B50 fan function

¹XX is the number of layers which depends of the simulated PCB.

Each layer was set with its thickness and copper filling factor.

2.2.3. Thermal model of vias and BGAs

The internal vias are kept and rendered in copper with hollow square tubes of 40 × 40 × 1560 μm³ with 20 μm wall. Micro-vias and buried vias were neglected, but thermal vias were all modeled. The BGA balls were depicted by an equivalent volumetric cubes.

2.2.4. · Material assignment

The material assignment for parts without function designation was performed with values given in Tables 1 and 2, in agreement with their thermal conduction values.

Table 2:

Relation between real and simulated material.

Part	Physical material	Simulated material
PCB conductor	Copper	Copper
PCB dielectric	Dielectric	Laminate
ASIC BGA	SAC305 (Sn96Ag3.5Cu.5)	SAC305 (Sn96Ag3.5Cu.5)
ASIC Top/Bottom	Silicon	Silicon
ASIC Electric layer	Aluminum	Aluminum
Thermal interface	Thermal Pad	Custom material (2 W/mK)
Underfill	Epoxy	Custom material (0.3 W/mK)
Room	Air	Air

2.2.5. Temperature and power dissipation

Table 3 gives the power dissipation of the main components generating heat. The 550 mW heat source was assigned to the aluminum layer of the ASIC. Heat sources of 3 W per FPGA and 0.4 W per clock buffer were simulated.

Table 3:

Power dissipation used in simulation model.

Part with power dissipation	Value
Aluminum layer of the ASIC	550 mW
FPGA	3 W
4 Clock buffers	1.6 W

2.3. Experimental set-ups to validate the thermal model

A robust evaluation of the thermal model requires the ASIC to be tested in various conditions. Three PCB configurations were chosen: 1) a development board (DevBoard) comprising a single ASIC, 2) an Adaptor Board coupled to a Daughter Board (DB) with two ASICs and 3) an organic interposer having two ASICs in sandwich with a Carrier Board (CB). All these boards are further described below. Each PCB was modeled according to the thermal model developed in SolidWorks and Flow Simulation.

2.3.1. DevBoard

This DevBoard measures 34 mm by 62 mm with an internal structure comprising eight copper layers filled at 20%, 20%, 80%, 80%, 80%, 20%, 20% and 20%, respectively. The ASIC is placed close to the center of the PCB (Fig. 3) and covered with black paint to allow thermal imaging with a infrared camera.

Figure 3:

DevBoard with one ASIC and black paint.

2.3.2. AB/DB assembly

The AB/DB assembly is the current detector module configuration of the LabPET II scanner for small and mid-sized animals. The ABs link ESPUs to the DB on which are located two ASICs next to the connector (Fig. 4). The AB measures 75 mm by 23 mm and the DB, 12.5 mm by 23 mm. The AB has eight copper layers each filled at 20%, 20%, 80%, 80%, 80%, 20%, 20% and 20%, respectively. The DB has 12 copper layers each filled at 20%, 80%, 95%, 30%, 95%, 95%, 90%, 95%, 30%, 95%, 80% and 20%, respectively.

Figure 4:

AB/DB assembly covered with black paint.

2.3.3. CB/interposer

This assembly is a low-profile front-end with the same function of the AB/DB assembly but designed to be compatible for an MRI insert [12]. The ASICs are placed on a BGA-like interposer soldered on the CB in such a way that the ASICs are sandwiched between the interposer and the CB (Fig. 5). The ASIC bulk layer is facing a thermal pad on the top side of the CB to ease heat extraction with a second thermal pad on CB bottom. The interposer measures 11.9 mm by 23.2 mm to house the two ASICs and a dual ring of BGA. The CB measures 150 mm by 23.2 mm and accepts up to four interposers. The Interposer and CB both have 12 layers of copper filled at 20%, 80%, 95%, 30%, 95%, 95%, 90%, 95%, 30%, 95%, 80% and 20%, respectively.

Figure 5:

LabPET II insert pictures. (Left) Top and bottom view of a carrier board (CB) with two interposers. (Right) Zoom on the front side of the interposer with the flip chipped ASICs and BGA.

2.3.4. · Mechanical support and electronic link

All boards configurations described above require a mechanical support and an electronic link to conduct the experiments. A standalone ESPU board with 12 copper layers measuring 125 × 290 mm² was used for this purpose. The main parts of the modelled ESPU are a FPGA, four clock buffers and 12 connectors accepting the PCB to be tested. An axial fan with a flow rate of 2.13 m³ min⁻¹ was placed at a distance of 18 cm above the connectors (3615KL-05W-B50, NMB Technologies Corporation, USA) to create a forced airflow.

3. Methods

The three described PCB assemblies were first used with the ESPU to obtain experimental temperature readings using the ASIC embedded temperature sensors. The temperature was read out every 5 s until a steady state was reached. Then, the boards were modeled in SolidWorks with the thermal model described in the previous section. Figure 6 displays the experimental setups (on the left) together with the 3D rendering of the three modeled assemblies (on the right).

Figure 6:

Display of (a) the experimental set up and (b) the 3D rendering of the simulation model for the three board assemblies: (top) DevBoard mounted on ESPU; (middle) DB/AB mounted on ESPU board; (bottom) CB/interposer also mounted on ESPU.

Natural airflow was estimated at 0.1 m/s and room temperature was always maintained at 23 °C. The results were compared to validate the thermal model of the ASIC.

3.1. Precision of experimental measurements

Due to physical differences in the assembly process, the embedded temperature sensors in the ASIC have some temperature offset due to uneven calibration. This offset temperature distribution was used to define an acceptable confidence interval between the experimental readings and the simulated temperatures. The ASIC temperatures were recorded for 24 DB placed on the same AB with the fan of the ESPU turned off, allowing only natural airflow. The steady state temperature was read out and histogrammed. A χ² test was used to verify that the data was normally-distributed, as expected, and a gaussian fit was applied to extract the standard deviation σ. This σ was used as the confidence interval to compare the experimental readings and the simulated temperatures.

3.2. Experimental measurements

3.2.1. DevBoard measurements

The DevBoard was placed on the third connector of the ESPU and the temperature acquisition was started with/without fan. This measurement was repeated with eight different DevBoards to acquire statistics.

For one DevBoard, the temperature was also measured with a thermal camera (model Ti10, Fluke Corporation, WA, USA) without the fan. The surface emissivity varies according to the material and affects the temperature reading [13]. The Ti10 thermal camera has only one emissivity parameter that is set for black painted surface. So, following the manufacturer’s recommendation, the ASIC was covered with black paint (Fig. 3) and the camera was placed straight over the DevBoard to ensure a temperature reading accuracy of 5 °C for this material.

3.2.2. AB/DB measurements

An AB/DB assembly was placed on the first connector position on the ESPU for the initial measurement. A second measurement was done with eight AB/DB assemblies mounted on the ESPU in positions one to eight. The same measurements were repeated with the fan activated.

3.2.3. CB/interposer measurements

The four interposers were added sequentially on the CB and temperature measurements were obtained with/without fan. In this way, eight measurements were done. For these measurements, the acquisition was stopped when the internal ASIC temperature reached 75 °C to protect the prototype.

3.3. Thermal simulation

3.3.1. DevBoard simulation

A simulation of the DevBoard on the ESPU was carried out in the same experimental conditions, with/without forced airflow.

3.3.2. AB/DB simulation

Four simulations were carried out reproducing the experiments with one and eight AB/DB assemblies, with/without forced airflow.

3.3.3. CB/interposer simulation

Simulations were performed with the same meshing to check the evolution of the temperature as the number of interposers was increased from one to four. The four CB/interposer configurations were simulated with and without forced airflow.

4. Results

4.1. Precision of experimental measurements

The temperature data of the 48 embedded sensors were founded to be normally-distributed with a chi-square (chi²) larger than 0.999. The mean value of the measured temperature without air flow was 72.5 °C with a standard deviation of 2 °C. A mean difference of 2 °C was observed between the temperature values of the DM ASICs. The temperature values of both ASICs analyzed separately gave a chi² of 1. The data are summarized in Table 4.

Table 4:

Summary of the statistical data for 24 DB used on the same AB : Mean, Standard Deviation (σ), Minimum temperature (Min), Maximum (Max) temperature and χ²

	Mean [°C]	σ	Min	Max	χ2
ASIC 0	73.7	1.6	70	76	1
ASIC 1	71.3	1.6	67	75	1
ASICs	72.5	2	67	76	.9999

4.2. Experimental Measurements

4.2.1. DevBoard

Table 5 shows the temperature for the eight tested DevBoard, where the internal temperatures are found to vary between 40 °C and 44 °C without fan and between 31 °C and 37 °C with fan. Figure 7 shows the temperature distribution measured on the ESPU and DevBoard with the thermal camera. The emissivity factor being adjusted for the black paint, this area indicates a maximum temperature of 44±5°C for the ASIC. The temperature distribution on the PCB shows a fast temperature drop around the ASIC. The temperature measurements with the embedded sensor was 51 °C.

Table 5:

Summary of the temperature measurements on DevBoards with the embedded sensor in the ASICs. The temperature measurements were performed without/with fan in [°C].

	1	2	3	4	5	6	7	8
Without Fan	43	42	44	44	44	44	42	40
With Fan	35	34	35	35	37	36	33	31

Figure 7:

Thermal camera picture of a DevBoard on the ESPU. The image on the right is a zoom on the DevBoard. The white dotted line represents the section with black paint. The values 33.5 and 41.9 in white close to the scale indicates the temperature at the image centre where is placed the cross.

4.3. AB/DB

With one AB/DB on the ESPU, the temperatures given by the ASIC sensors were 74 °C and 73 °C. When the fan was activated, the temperature dropped to 55 °C and 52 °C.

Table 6 shows the temperature for eight AB/DB assembled on the ESPU. The temperature reached between 76 °C and 88 °C without fan and dropped between 49 °C and 58 °C with fan.

Table 6:

Summary of the temperature measurements with eight AB/DB on the ESPU using the ASIC embedded sensor. The temperature measurements were made without/with the fan in [°C].

	DB1	DB2	DB3	DB4	DB5	DB6	DB7	DB8
ASIC 0	80/52	87/53	88/58	83/57	86/53	84/53	88/56	81/54
ASIC 1	76/53	83/54	83/53	82/54	87/52	85/49	84/51	82/51

4.4. CB/interposer

Table 7 shows the evolution of the temperature as the CB is being populated by interposers. Without thermal management and with two and more interposers, the temperature reached 75 °C in less than 6 min and the experiment was stopped.

Table 7:

Temperatures in [°C] read out with the ASIC embedded sensor for each of the eight interposer configurations.

Interposer		1	1/2	1/2/3	1/2/3/4
No	ASIC 0	50	> 75	> 75	> 75
Fan	ASIC 1	51
With	ASIC 0	37	46/42	53/50/46	55/52/50/48
Fan	ASIC 1	37	45/44	51/52/45	53/55/49/48

4.5. Thermal simulation

4.5.1. DevBoard

Figure 8 represents the temperature distribution on the DevBoard and the ESPU surface. The maximum simulated temperature of 45 °C is reached in the ASIC. The ASIC temperature drops to 34 °C with the forced airflow.

Figure 8:

Temperature distribution in [°C] on the DevBoard with one ASIC mounted on ESPU. (a) Simulation with natural air convection; (b) simulation with ESPU fan activated. Labels show the temperature at specific points: PCB surface (black), top surface of clock buffer (green) and top bulk surface of the ASIC (red).

4.6. AB/DB

With one AB/DB, the temperature obtained with the simulations are 71 °C and 74 °C for the ASIC 0 and 1 with natural convection and 56 °C and 51 °C when the fan is turned on. Simulation with eight AB/DB are also reported in (Fig. 9).

Figure 9:

Temperature distribution in [°C] on one AB/DB with two ASICs (top) and eight AB/DB (bottom), (a) natural air convection simulation, (b) simulation with ESPU fan activated. Labels show the temperature at specific points: PCB surface (black), top bulk surface of the ASIC (red) and bottom side surface of the DB (orange).

4.7. CB/interposer

Figure 10 shows the temperature gradient on the CB and the interposers with specific measurements on the ASIC aluminium layer and interposer edges. Temperature rises to a maximum of 37°C, 45 °C, 52 °C and 57°C from one to four interposers with forced airflow, contrary to without thermal management where the temperature already rises to a maximum of 52 °C for one interposer.

Figure 10:

Temperature distribution in [°C] on the CB/interposers: (a) natural air convection simulation, (b) simulation with ESPU fan activated. Labels show the temperature at specific points: aluminium layer surface (red) and edge surface of an interposer (orange).

5. Discussion

Experimental measurements show that, in the same assembly configuration and experimental setup, the internal temperature reading of the ASIC has a perfectly normal distribution with a standard deviation of 2 °C. This temperature distribution results from the non-calibrated ASIC temperature sensors and from physical differences in the underfill and tin layers under the ASICs due to manual assembly.

Table 8 reports an analysis of the relative temperature differences between the simulated results and the experimental readings. A relative mean difference of 0.3 °C with a standard deviation of 2°C is observed with all measurement configurations. As expected, this mean is centred around 0 corresponding to the case where the simulation results give the mean experimental temperature readings. A small offset of 0.6 °C is noticed in the natural airflow simulation, but not in the forced airflow cases (0.1 °C). In addition to the statistical errors in the simulations and measurements, the main contribution to this offset appears to result from the natural airflow estimation, which was assumed to be the same for all simulations. A modification of the natural airflow value in the simulation successfully corrects this offset. Also, if the natural convection is believed to be the dominant factor, a calibration board can be used to verify if the natural airflow estimation is valid. In the case of the four interposers configuration with fan on, an offset of 1 °C is observed. A plausible explanation is a fan displacement.

Table 8:

Summary of the difference between experimental readings and simulated temperatures : Mean, Standard Deviation (σ)

	Mean difference [°C]	σ
All configurations	0.3	2
Without fan configuration	0.6	2
With fan configuration	0.1	2
DevBoard configuration	0	1
AB/DB configuration	0	2
CB/interposers configuration	1.1	2

Overall, the standard deviation of 2 °C on the difference between simulation and measurements is identical to the standard deviation on the experimental readings, demonstrating that the simulation does not add significant bias. However, the positive values of this offset indicate that the simulation tends to overestimate the temperature. Considering that the simulation will be used to help in designing the thermal management required to keep the APD temperature as low as possible, this overestimation can be tolerated.

Under these conditions, a temperature difference up to 6 °C, corresponding to a confidence interval of 99% (3σ) on the ASIC surface, can be accepted between simulations and experimental results.

The aim of this work was to build a reliable thermal model for the LabPET II ASIC in order to enable the simulation of the heat flow in a full scanner, hence the generalisation case must be addressed. The simulation results do not seem to be affected significantly by the number of ASICs and their configurations, as demonstrated by the interposers and AB/DB results, thus confirming the robustness of the thermal model of the ASIC and associated hardware. A visual comparison of the ESPU thermal image with the simulated data shows a similar temperature distribution, that is corroborated by several temperature point measurements. Since the ESPU is another key part of the LabPET II scanner, our work suggests that a full scanner can realistically be simulated using this model.

The interposers on the CB were developed to be compatible for an MRI insert and to facilitate its thermal management. Comparing the temperature difference between the bottom side of the DB/interposer and the ASIC, a smaller temperature difference is noticed with the interposers than the DB. The thermal contact to the ASICs is more efficient in this assembly, the interposers and CB both serving as heat sink. Consequently, the heat load being distributed by conduction on a larger surface will be more easily extracted by forced airflow.

6. Conclusion

A thermal model of the LabPET II ASICs was implemented and investigated in various conditions on different carrier boards. The agreement between experimental and simulation results for three different assemblies demonstrate that the dissipation model of the ASIC is valid and transferable to different boards with a ±3°C accuracy. Moreover this model enables the simulation of a full-sized small animal scanner with Flow Simulation using a computer with only 32 GB of memory.