Skip to main content
Springer Nature - PMC COVID-19 Collection logoLink to Springer Nature - PMC COVID-19 Collection
. 2020 Mar 13;12078:155–172. doi: 10.1007/978-3-030-45190-5_9

Safe Decomposition of Startup Requirements: Verification and Synthesis

Alessandro Cimatti 10, Luca Geatti 10,11, Alberto Griggio 10, Greg Kimberly 12,, Stefano Tonetta 10
Editors: Armin Biere8, David Parker9
PMCID: PMC7439741

Abstract

The initialization of complex cyber-physical systems often requires the interaction of various components that must start up with strict timing requirements on the provision of signals (power, refrigeration, light, etc.). In order to safely allow an independent development of components, it is necessary to ensure a safe decomposition, i.e. the specification of local timing requirements that prevent later integration errors due to the dependencies. We propose a high-level formalism to model local timing requirements and dependencies. We consider the problem of checking the consistency (existence of an execution satisfying the requirements) and compatibility (absence of an execution that reaches an integration error) of the local requirements, and the problem of synthesizing a region of timing constraints that represents all possible correct refinements of the original specification. We show how the problems can be naturally translated into a model checking and synthesis problem for timed automata with shared variables. Exploiting the linear structure of the requirements, we propose an encoding of the problem into SMT. We evaluate the SMT-based approach using MathSAT and show how it scales better than the automata-based approach using Uppaal and nuXmv.

Contributor Information

Armin Biere, Email: biere@jku.at.

David Parker, Email: d.a.parker@cs.bham.ac.uk.

Alessandro Cimatti, Email: cimatti@fbk.eu.

Luca Geatti, Email: lgeatti@fbk.eu, Email: luca.geatti@uniud.it.

Alberto Griggio, Email: griggio@fbk.eu.

Greg Kimberly, Email: greg.kimberly@boeing.com.

Stefano Tonetta, Email: tonettas@fbk.eu.

References

  • 1.Alur, R., Dill, D.L.: A theory of timed automata. Theoretical computer science 126(2), 183–235 (1994).
  • 2.André, É.: Parametric Deadlock-Freeness Checking Timed Automata. In: Theoretical Aspects of Computing - ICTAC 2016–13th International Colloquium, Taipei, Taiwan, ROC, October 24–31, 2016, Proceedings. pp. 469–478 (2016). 10.1007/978-3-319-46750-4_27.
  • 3.André, É., Chatain, T., Fribourg, L., Encrenaz, E.: An inverse method for parametric timed automata. International Journal of Foundations of Computer Science 20(05), 819–836 (2009).
  • 4.Astefanoaei, L., Rayana, S.B., Bensalem, S., Bozga, M., Combaz, J.: Compositional Invariant Generation for Timed Systems. In: Tools and Algorithms for the Construction and Analysis of Systems - 20th International Conference, TACAS 2014, Held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2014, Grenoble, France, April 5–13, 2014. Proceedings. pp. 263–278 (2014). 10.1007/978-3-642-54862-8_18.
  • 5.Astefanoaei, L., Rayana, S.B., Bensalem, S., Bozga, M., Combaz, J.: Compositional Verification of Parameterised Timed Systems. In: NASA Formal Methods - 7th International Symposium, NFM 2015, Pasadena, CA, USA, April 27–29, 2015, Proceedings. pp. 66–81 (2015). 10.1007/978-3-319-17524-9_6.
  • 6.Behrmann, G., David, A., Larsen, K.G., Håkansson, J., Pettersson, P., Yi, W., Hendriks, M.: Uppaal 4.0 (2006).
  • 7.Cimatti, A., Griggio, A., Magnago, E., Roveri, M., Tonetta, S.: Extending nuXmv with Timed Transition Systems and Timed Temporal Properties. In: Computer Aided Verification - 31st International Conference, CAV 2019, New York City, NY, USA, July 15–18, 2019, Proceedings, Part I. pp. 376–386 (2019). 10.1007/978-3-030-25540-4_21.
  • 8.Cimatti, A., Griggio, A., Magnago, E., Roveri, M., Tonetta, S.: Smt-based satisfiability of first-order ltl with event freezing functions and metric operators (2019).
  • 9.Cimatti, A., Griggio, A., Mover, S., Tonetta, S.: Parameter synthesis with ic3. In: 2013 Formal Methods in Computer-Aided Design. pp. 165–168. IEEE (2013).
  • 10.Cimatti, A., Griggio, A., Mover, S., Tonetta, S.: Verifying LTL Properties of Hybrid Systems with K-Liveness. In: Computer Aided Verification - 26th International Conference, CAV 2014, Held as Part of the Vienna Summer of Logic, VSL 2014, Vienna, Austria, July 18–22, 2014. Proceedings. pp. 424–440 (2014). 10.1007/978-3-319-08867-9_28.
  • 11.Cimatti, A., Griggio, A., Mover, S., Tonetta, S.: Infinite-state invariant checking with IC3 and predicate abstraction. Formal Methods in System Design 49(3), 190–218 (2016). 10.1007/s10703-016-0257-4.
  • 12.Cimatti, A., Griggio, A., Schaafsma, B.J., Sebastiani, R.: The mathsat5 smt solver. In: International Conference on Tools and Algorithms for the Construction and Analysis of Systems. pp. 93–107. Springer (2013).
  • 13.De Alfaro, L., Henzinger, T.A., Stoelinga, M.: Timed interfaces. In: International Workshop on Embedded Software. pp. 108–122. Springer (2002).
  • 14.De Moura, L., Bjørner, N.: Satisfiability modulo theories: introduction and applications. Communications of the ACM 54(9), 69–77 (2011).
  • 15.Niemelä, I.: Stable models and difference logic. Annals of Mathematics and Artificial Intelligence 53(1–4), 313–329 (2008).
  • 16.Stigge, M., Ekberg, P., Guan, N., Yi, W.: The digraph real-time task model. In: 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium. pp. 71–80. IEEE (2011).
  • 17.Stigge, M., Yi, W.: Combinatorial abstraction refinement for feasibility analysis of static priorities. Real-Time Systems 51(6), 639–674 (2015). 10.1007/s11241-015-9220-5

Articles from Tools and Algorithms for the Construction and Analysis of Systems are provided here courtesy of Nature Publishing Group

RESOURCES