Ultrafast, Zero-Bias, Graphene Photodetectors with Polymeric Gate Dielectric on Passive Photonic Waveguides

Abstract

We report compact, scalable, high-performance, waveguide integrated graphene-based photodetectors (GPDs) for telecom and datacom applications, not affected by dark current. To exploit the photothermoelectric (PTE) effect, our devices rely on a graphene/polymer/graphene stack with static top split gates. The polymeric dielectric, poly(vinyl alcohol) (PVA), allows us to preserve graphene quality and to generate a controllable p–n junction. Both graphene layers are fabricated using aligned single-crystal graphene arrays grown by chemical vapor deposition. The use of PVA yields a low charge inhomogeneity ∼8 × 10¹⁰ cm^–2 at the charge neutrality point, and a large Seebeck coefficient ∼140 μV K^–1, enhancing the PTE effect. Our devices are the fastest GPDs operating with zero dark current, showing a flat frequency response up to 67 GHz without roll-off. This performance is achieved on a passive, low-cost, photonic platform, and does not rely on nanoscale plasmonic structures. This, combined with scalability and ease of integration, makes our GPDs a promising building block for next-generation optical communication devices.

Telecommunication networks and interconnections in data centers require a bandwidth increase combined with a reduction of power consumption and cost to cope with the growing demands for data transmission.^1,2 The Ethernet roadmap³ foresees a bandwidth doubling roughly every two years. The present target is to develop transceiver (transmitters and receivers) modules working at 1.6 Tb s^–1 by 2022.⁴ The established technologies based on InP⁵ and Si photonics⁶ are continuously improving. However, the requirements in terms of bandwidth and power consumption have not been fulfilled in one system yet.⁶

Single-layer graphene (SLG) is ideally suited for optoelectronic and photonic applications.⁷⁻¹⁰ The absence of a bandgap enables absorption in a very broad range of optical frequencies, spanning from the UV to the far-infrared.^7,9,11 The ultrafast electron excitation dynamics (< 50 fs)¹² upon optical excitation, and the consequent short relaxation time, of the order of few ps,¹² enable high-speed devices.¹³ Fast graphene photodetectors (GPDs) have been demonstrated,^8,14−19 with bandwidth > 100 GHz.¹⁷⁻¹⁹ In terms of speed, such devices can compete with Ge-based PDs.²⁰ However, these GPDs typically require nanoscale plasmonic structures, using metals not compatible with complementary metal oxide semiconductor (CMOS) integration.^18,19 Furthermore, these GPDs are based on photovoltaic (PV)¹⁹ and photobolometric (PBM)^17,18 effects and are thus operated with a bias ∼0.5 V^17,18 to ∼1.5 V,¹⁹ leading to significant dark current (up to a few mA),¹⁸ orders of magnitude larger than typical p–n junction near-infrared PDs.²¹

GPDs based on the photothermoelectric (PTE) effect promise large bandwidth,^8,22 with the additional advantage of bias-free operation and, thus, zero dark current photovoltage generation.^15,23−25 The absence of dark current avoids any noise contribution coming from a DC current.²⁶ Indeed, for a large (∼mA) dark current, we expect an increase of generation–recombination (GR) noise caused by the statistical generation and recombination of charge carriers.²⁷ The GR noise power spectral density (PSD) is directly proportional to the square of the DC current.²⁸ GR noise contributes to the overall noise also at microwave frequencies (2.5 GHz).²⁹ With a dark current of the order of mA, even shot noise, originating from the discrete nature of the electric charge, and dependent on the current flowing without relation to operating temperature²⁷ and with PSD proportional to the DC current,²⁹ may give a non-negligible contribution.²⁹ In PTE-based GPDs, the photoresponse is generated by the Seebeck effect induced by two main factors: the spatial gradient of the SLG electronic temperature induced by the absorption of the optical signal, and the spatial variation of the SLG Seebeck coefficient, S.³⁰ The S profile along SLG can be induced by electrostatically generated p–n junctions.³¹ Such junctions can be achieved either by doped waveguides (WGs),^15,25 with increased fabrication complexity and cost, or by external gates,²³ which requires SLG dielectric encapsulation. The photovoltage V_ph can be written as³⁰⁻³²

1

where S₂ and S₁ are the Seebeck coefficients in each side of the SLG p–n junction, T_e is the electron temperature, and T₀ is the SLG lattice temperature. The ratio between V_ph and the incident optical power P_opt is the voltage external responsivity, R_V, expressed in V W^–1_.^15,24,25

Waveguide-integrated PTE-GPDs were reported,^15,23−25 with R_V ∼ 3.5 V W^–1 (ref (25)) to 12.2 V W^–1 (ref (24)) but limited in bandwidth (BW), with evidence of roll-off at 65 GHz for exfoliated SLG,²⁵ and at 42 GHz for CVD SLG.²⁴ These performances were reached by enhancing the optical absorption, exploiting subwavelength confinement of the electromagnetic field with nanoscale structures, such as photonic crystals,¹⁵ slot,²⁵ and plasmonic WGs.²⁴ The local field enhancement in SLG allows for a higher gradient of the electronic temperature ΔT_e, leading to a larger photovoltage, but the fabrication of these structures typically requires sub-100 nm resolution, therefore a simpler GPD geometry based on a passive straight WG is preferable.

According to eq 1, the photovoltage may also be improved by increasing S. This is related to the SLG mobility, μ,²⁴ and residual carrier concentration n* at the charge neutrality point (CNP).³³ To date, a large S (i.e., S ∼ 183 μV K^–1) was only reported for exfoliated SLG on hexagonal boron nitride (hBN) (μ > 10,000 cm² V^–1 s^–1).³⁴ For CVD grown polycrystalline SLG, S < 20 μV K^–1 was observed.³⁵

Here, we demonstrate a SLG-polymer-SLG PTE GPD fabricated using scalable CVD single-crystal SLG arrays for both channel and split gates. The use of polymer dielectric, poly(vinyl alcohol) (PVA) allows us to preserve the SLG quality (i.e., n* = 8 × 10¹⁰ cm^–2 at the CNP and μ ∼ 16,000 cm² V^–1 s^–1) and to obtain S up to 140 μV K^–1. The GPDs have a compact footprint and are fabricated on a single-mode straight WG using top gates to electrostatically induce a p–n junction, thus not requiring the ion implantation used in conventional devices.²⁶ Deposition of common dielectrics, like Al₂O₃, HfO₂, and Si₃N₄, typically leads to a degradation of μ and n* (refs (36−40)). Here, PVA is deposited by spin-coating, yielding a conformal coverage. It is nonsoluble in organic solvents,⁴¹ widely used in nanofabrication, and does not compromise the SLG properties. Static characterization at 1550 nm shows a 6-fold pattern photovoltage map as a function of gate voltage, a signature of PTE.³² The responsivity is ∼6 V W^–1, comparable to GPDs using photonic structures with feature sizes <100 nm.^15,24,25 Dynamic characterization is performed up to 67 GHz, showing a flat electro-optical frequency response without roll-off. This frequency response is, to the best of our knowledge, the highest thus far for a zero-bias GPDs.

Results

A schematic cross-section diagram of GPDs is in Figure 1a. They comprise a CVD single-crystal SLG channel on a Si₃N₄ WG, a PVA dielectric spacer, and top SLG split gates above the SLG channel, aligned with the center of the photonic WG. By applying a voltage to each split gate, a p–n junction is created enabling the generation of photovoltage when a T_e gradient is induced across the junction by light absorption in a SLG channel above the photonic bus WG.³⁰

Figure 1.

Design and fabrication flow of double SLG PTE PD. (a) Cross-section. (b) Wafer (light blue) with a Si₃N₄ photonic WG (teal). (c) Single-crystal SLG (gray) transferred on the WG. (d) SLG shaped into PD channel. (e) Ni/Au contacts (yellow) deposited by thermal evaporation. (f) PVA dielectric (semi-transparent blue) spin-coated on the chip. (g) Top SLG (darker gray) aligned and transferred on the device. (h) Top SLG shaped into split gate geometry by RIE. (i) Ni/Au gate contacts (darker yellow) deposited by thermal evaporation. (j) Schematic diagram of design (not to scale) dimensions optimized for high R_V. Inset: key dimensions of bottom and top SLG structures. (k) Optical micrograph of a typical device. Darker yellow squares are the contact pads for the GPD channel (not visible). Lighter yellow are the pads for the split gates. A Si₃N₄ WG (thin dark green line) is visible at the center of the device.

Figure 1b–i outlines the process flow. Devices are fabricated on a wafer containing Si₃N₄ WGs cladded (as depicted in panel b) with a thin (∼25 nm) layer of boron–phosphorus tetraethyl orthosilicate (BPTEOS) (further information in Methods). SLG crystals are deterministically grown in arrays,⁴² matching the WG geometry, electrochemically delaminated from a Cu via semidry transfer,⁴² and aligned (panel c) on the WGs. Deterministic growth and transfer allows us to transfer up to 300 crystals at a time on adjacent WGs and to process ∼20 at a time. Images of the SLG crystals used for GPD fabrication are shown in Figure 2a–c. SLG is then shaped into the active device channels using electron-beam lithography (EBL) and reactive-ion etching (RIE), Figure 1d. Ohmic contacts are fabricated using EBL and thermal evaporation of 7 nm Ni and 60 nm Au, followed by lift-off in acetone, Figure 1e. A PVA solution (5% in water, Sigma-Aldrich, MW: 23–75 kDa, 89% hydrolyzed) is spin-coated on the devices at 8000 rpm, achieving a conformal coating. This is then cured on a hot plate at 90 °C for 2 min, Figure 1f. A second layer of SLG single-crystals is then aligned and laminated on the devices using semidry transfer,⁴²Figure 1g. The top SLG crystals are shaped into split gates and contacted using the same methods used for the bottom SLG, Figure 1h,i. To ensure the operation of the gates even in the event of a discontinuity in the 80 μm-long and 3.5 μm-wide SLG stripes, metal connections to the gates are fabricated from both sides in a “butterfly” configuration, Figure 1i,k. As a final step, PVA is removed from the WGs outside the device with deionized (DI) water. The deterministically grown single-crystal SLG arrays and the PVA dielectric allow us to make multiple devices in parallel. PVA, if left uncovered, could be affected by humidity.⁴³ A further encapsulation step via semidry transfer of CVD hBN can be used to provide a humidity barrier to the PVA.

Figure 2.

(a) Optical image of a typical SLG crystal transferred on 285 nm SiO₂. (b) Dark-field microscopy image of a SLG crystal array with a periodicity of 200 μm. (c) False color optical image of SLG array transferred on two adjacent WGs.

In order to evaluate both the SLG electrical and thermoelectric properties when PVA is used as the gate dielectric, n* is extracted from the field-effect transistor (FET) measurements (see Methods). A typical field-effect curve for a SLG FET using PVA as gate dielectric is in Figure 3a. We get n* ∼ 8.2 × 10¹⁰ cm^–2 (∼35 meV) by performing a linear fit (Figure 3b) to a logarithmic plot of conductivity as a function of carrier density.^44,45 A similar value is also obtained by fitting the field-effect resistance curves as for ref (46) (see Methods for details). This n* is lower than in samples encapsulated using technologies compatible with wafer-scale processing, such as atomic layer deposition (ALD) (∼2.3 × 10¹¹ cm^–2 46 and ∼3 × 10¹¹ cm^–238) and is approaching those reported for exfoliated or CVD-based SLG/hBN heterostructures.^44,45,47,48

Figure 3.

(a) Field-effect response of SLG/PVA. (b) Extraction of n*. (c) Calculated S for n* = 8 × 10¹⁰ cm^–2. (d) Electric field profile of the simulated fundamental quasi-TE mode of the Si₃N₄ WG (1200 nm × 260 nm, λ₀ = 1550 nm). (e) S spatial profile in SLG p–n junction (red curve) and spatial profile of ΔT_e (blue curve). (f) Simulated photovoltage map as a function of voltage applied to the split gates, assuming 1 mW incident power, for channel length 10 μm and channel width 80 μm (see Figure 1j). Different regions are evident, corresponding to different doping configurations, p–n, p–p, n–p, and n–n. As emphasized by the dashed lines, the photovoltage sign reversal leads to additional p–p′ and n–n′ configurations, thus the 6-fold symmetry characteristic of PTE.^30,32

We use the model of ref (33) to calculate S using our experimental n*. S as a function of n is plotted in Figure 3c (see Methods for details). We get S ∼ 140 μV K^–1 for n* ∼ 8 × 10¹⁰ cm^–2. This is higher than for SLG on SiO₂^35,49−51 and similar to that reported for SLG on hBN.³⁴

In order to model the PTE effect and to compute the T_e profile along with the generated photovoltage, we adapt the model of ref (32) to describe a GPD on a photonic integrated WG. Figure 3d shows the electric field profile of the simulated fundamental quasi-TE mode propagating in a Si₃N₄ WG, using a commercial mode solver, and the surface conductivity model for the SLG optical properties of ref (52) (see Methods for further details). An example of the spatial profile of ΔT_e in a cut of the GPD is in Figure 3e, along with the S spatial profile for two gate voltages.

The optimum design is chosen by simulating photovoltage maps of several device geometries with channel length, L, ranging between 10 and 25 μm and width, W, between 40 and 80 μm. The optimization of the aspect ratio, W/L, of the SLG channel is necessary to minimize the series resistance in order to reduce the electrical power dissipation of the GPD when connected to 50 Ω matched read-out electronics. The maximum W is determined by the length of the mode absorption. Above 50 μm, the mode is attenuated by a factor e. Therefore, for devices with W ≫ 50 μm, no significant increase in photocurrent is expected. Accordingly, the photovoltage, V_Ph, drops due to a saturated photocurrent, I_Ph, and decreasing resistance, R (as per V_Ph = R × I_Ph).³⁰ For a minimum channel length L ∼ 10 μm, determined by fabrication constraints (as discussed in Methods), a channel width W ∼ 80 μm provides the best compromise, with a resistance of several hundred Ω and R_V > 5 V W^–1. The gate electrodes, Figure 1j, consist of two SLG strips 3.5 μm wide separated by a 1 μm gap. This spacing is chosen as it is compatible with typical i-line optical lithography at 365 nm,⁶⁴ making it suitable for large-volume production. Even though EBL can achieve a resolution ∼50 times smaller than that of i-line optical lithography, simulations of devices having split gate separation in the range ∼0.2–1.1 μm show only a small penalty (22%) of maximum achievable R_V when going from EBL to optical resolution (see Figure 11e). The photovoltage is simulated as a function of the split gate voltage, as shown in Figure 3f. The maximum photovoltage is observed in the regions with opposing gate polarity, n–p and p–n. Doping configurations where both gates are of the same polarity with respect to the CNP are split into additional regions n–n, n–n′ and p–p, p–p′, with n′ (p′) indicating stronger n-type (p-type) doping with respect to n (p). A photovoltage sign reversal is observed due to the nonmonotonic variation of S with gate voltage.^30,32 This leads to a 6-fold pattern of alternating positive and negative photovoltage, typical of PTE.^30,32 Dashed guides to the eye separate the six distinct regions.

Figure 11.

(a) Field-effect response of SLG with PVA gate dielectric. (b) Fit with eq 4. (c) Fit with eq 7. (d) S as a function of n for n* ∼ 8 × 10¹⁰ cm^–2 (red curve) and n* ∼ 7 × 10¹⁰ cm^–2(blue dashed curve). (e) Simulation of maximum responsivity as a function of split gate spacing, normalized to R_V (200 nm).

At each fabrication step, the SLG quality is assessed by Raman spectroscopy. Raman spectra are acquired at 532 nm with a Renishaw InVia spectrometer, a laser power ∼1 mW, and 50× objective, giving a spot size ∼2 μm. The top SLG layers Raman spectra are measured outside the areas with two overlapping SLG, allowing for an independent analysis of top gate and active channel.

Representative spectra of SLG crystals are shown in Figure 4a: SLG on Cu, SLG after transfer on BPTEOS, SLG after PVA coating, and SLG after transfer on PVA. The SLG spectrum on Cu (shown after Cu luminescence subtraction) has a 2D peak with a single Lorentzian shape and with a FWHM(2D) ∼ 22.4 cm^–1, a signature of SLG.⁵³ The G peak position, Pos(G), is ∼1597 cm^–1, with FWHM(G) ∼ 8 cm^–1. The 2D peak position, Pos(2D) is ∼2713 cm^–1, while the 2D to G peak intensity and area ratios, I(2D)/I(G) and A(2D)/A(G), are ∼1.2 and ∼1.3, respectively. No D peak is observed, indicating negligible defects.^54,55 After transfer on BPTEOS, the 2D peak retains its single-Lorentzian line shape with FWHM(2D) ∼ 26.5 cm^–1. After PVA coating, FWHM(2D) ∼ 26.4 cm^–1. The D peak remains negligible, indicating that no significant defects are induced by SLG transfer or PVA.

Figure 4.

(a) Representative spectra for SLG grown on Cu (gray), transferred on BPTEOS (red), with PVA coating (blue) and on top of PVA (green). The spectra are normalized to have the same I(G). Same colors are used in the correlation plots (b–d). (b) A(2D)/A(G) as a function of Pos(G). (c) FWHM(2D) as a function of Pos(G). (d) FWHM(G) as a function of Pos(G). (e) Pos(2D) as a function of Pos(G). Solid lines of corresponding color show linear fits of the data for the three sample configurations.

Raman mapping is performed over an area ∼20 μm × 8 μm on SLG after transfer on BPTEOS, after PVA coating, and after transfer on PVA. Figure 4b–e plots Raman data extracted from the maps: A(2D)/A(G), FWHM(2D), FWHM(G), and Pos(2D) as a function of Pos(G). Pos(G) depends on both doping⁵⁶⁻⁵⁸ and strain.⁵⁹ This implies that local variations in strain and doping manifest as a spread in Pos(G) which, after transfer and PVA deposition, is ∼1582.5 ± 0.6 cm^–1 and 1583.7 ± 0.7 cm^–1, respectively. For graphene on BPTEOS, FWHM(G) is ∼16.4 ± 1.3 cm^–1, Pos(2D) ∼2675.0 ± 1.2 cm^–1, I(2D)/I(G) ∼6.5 ± 0.5, and A(2D)/A(G) ∼10.5 ± 0.5, which indicates a doping of ≪100 meV.^57,58 After PVA deposition, FWHM(G) ∼ 11.6 ± 1.2 cm^–1, Pos(2D) ∼2676.0 ± 1.2 cm^–1, and I(2D)/I(G) and A(2D)/A(G) are ∼4.3 ± 0.4 and ∼9. 0 ± 0.6, respectively. An almost identical range of FWHM(2D) is measured before and after PVA deposition (26.5 ± 1 cm^–1 and 26.4 ± 0.8 cm^–1). This indicates that PVA has no significant effect on the overall SLG quality, except for increased doping (∼100 meV).^57,58 SLG on top of PVA presents larger values and spread of Pos(G) ∼1585.2 ± 1.3 cm^–1 and lower FWHM(G) ∼9.8 ± 1.4 cm^–1, indicating a higher level and variation of doping in the top SLG.

The rate of change of Pos(2D) and Pos(G) with strain is ruled by the Grüneisen parameters,⁵⁹ which relate the relative change in the peak positions in response to strain. Biaxial strain can be differentiated from uniaxial by the absence of G and 2D peak splitting with increasing strain.⁵⁴ However, at low (≲0.5%) strain, the splitting cannot be resolved.^59,60Figure 4e plots the correlation between Pos(2D) and Pos(G). In general, both strain and doping influence Pos(G) and Pos(2D),⁵⁷⁻⁶⁰ while strain does not influence A(2D)/A(G). FWHM(G) can change due to strain inhomogeneities giving a distribution of slightly different Pos(G) in the area probed by the laser spot size or for a uniform strain, at the onset of the splitting of the G peak.⁵⁹ We use this approach to analyze the data in Figure 4. We first derive the doping from A(2D)/A(G). We then consider Pos(G) as a function of Pos(2D). In undoped samples, Pos(G) and Pos(2D) are linked by the Gruneisen parameters.⁵⁹ Any deviation from the relation between Pos(G) and Pos(2D) expected for undoped samples can thus be assigned to the presence of both strain and doping. Finally, for doping <1/2 the energy of the G phonon (∼100 meV),⁶¹ the variation of Pos(G) is mostly due to strain,⁵⁷ which can then be derived. This approach is applied to analyze the fits in Figure 4 as follows. At linear fit to data, solid lines in Figure 4e, gives a slope ΔPos(2D)/ΔPos(G) ∼ 1.44, ∼1.52, ∼1.65 for SLG on BPTEOS, SLG with PVA, and SLG on PVA, respectively. These values indicate a variation of both doping and strain within the mapped area, comparable to that of polycrystalline CVD-SLG encapsulated with hBN.⁴⁸ The presence (or coexistence) of biaxial strain cannot be ruled out. For uniaxial(biaxial) strain, Pos(G) shifts by ΔPos(G)/Δε ∼ 23(60) cm^–1/%.^59,60,62 For intrinsic SLG (E_F < 100 meV), the unstrained, undoped Pos(G) ∼1581.5 cm^–1.^53,61 Our graphene on BPTEOS, SLG with PVA, and SLG on PVA has a mean Pos(G) ∼1582.5, 1583.7, 1585.2 cm^–1. These values suggest a mean uniaxial (biaxial) strain ε ∼ 0.04% (∼0.02%), ∼ 0.1% (∼0.04%), and ∼0.13% (∼0.05%), respectively.

We perform static and radio frequency (RF) characterizations, as detailed in Methods, in order to estimate the maximum R_V and the BW. We bias the devices at 10 mV and measure the current in a two-terminal configuration as a function of the voltages applied to the two split gates (V_G1 and V_G2). The resistance map in Figure 5a shows four regions, defined by the different doping in the two sides of the junction. The quadrants correspond to finite n in the gated regions, with the four possible doping configurations n–n, n–p, p–n, and p–p. The peak R lines track the CNPs at 1.2 and 0.8 V for split gates 1 and 2, respectively. Considering the thickness of the PVA (120 nm) and the 14.5 dielectric permittivity (see Methods), at V_G1,G2 = 0 V, we estimate n ∼ 1 × 10¹² cm^–2 and ∼7 × 10¹¹ cm^–2, for the two gated regions, in agreement with the Raman estimates.

Figure 5.

(a) Resistance map as a function of the voltage applied to split gates. Four regions are evident, corresponding to p–n, p–p, n–p, and n–n doping. (b) Photovoltage map. Sign reversal leads to the appearance additional regions p–p′ and n–n′, thus a six-fold symmetry, characteristic of PTE.^30,32 (c) Photocurrent and (d) responsivity maps as a function of voltage applied to both gates, showing six-fold symmetry.

Figure 5b is a V_Ph map of the GPD, over the same V_G1–V_G2 range for an unbiased device coupled to a 1550 nm laser. While the resistance map has four gate voltage regions, the photoresponse shows a 6-fold pattern of alternating voltage as a function of V_G1 and V_G2, as emphasized by the dashed lines. The nonmonotonic variation of photoresponse as a function of gate voltage is reminiscent of the S dependence on n in Figure 3c. The PV effect, due to the variation of gate potential along the channel,^32,63 is a photoconversion mechanism competing with PTE.^32,63 In general, and depending on device geometry and wavelength, both mechanisms can be present.⁶³ However, PV is generally weak in graphene p–n homojunctions with respect to PTE at zero bias,³² even more so for samples having a narrow charge neutrality region (<100 meV) and high mobility (>10 000 cm² V^–1 s^–1).³² In our case, the dominance of PTE is experimentally verified from the photovoltage/photocurrent maps in Figure 5b–d, showing six different zones of alternating photoresponse sign, as marked by the dashed lines and labels. This is the signature of the PTE effect, because it is due to variations of the S difference between the two sides of the junction,³² and cannot be attributed to PV, which would exhibit only two zones of different signs in the photoresponse map.³²

The experimental Figure 5b is consistent with the simulated photovoltage map in Figure 3f, confirming that the SLG-PVA structure supports sharp variations of S across the gated regions. At a 700 μW input power, the maximum V_Ph ∼ 4 mV is found for the p–n and n–p regions in proximity of the neutrality lines.

Considering the various sources of loss, as detailed in Methods, the optical incident power is ∼700 μW, yielding R_V ∼ 6 V W^–1. Figure 5c,d reports the photocurrent and responsivity maps for our GPDs, displaying the 6-fold pattern signature of PTE effect.^30,32 The doping can be tuned to be p-type or n-type, depending on the applied gate voltages, and hence p–n indicates the region of p-doping induced by the gate 1 (V_G1) and n-doping induced by gate 2 (V_G2), and so on, with n′ (p′) indicating stronger n-type (p-type) doping with respect to n (p).

Figure 6 plots the frequency response of the photodetector to an amplitude-modulated optical signal (see Methods). The response is flat up to 67 GHz, limited by our measurement set up, without evidence of signal roll-off, defined as the slope of the frequency response in the transition region between the passband (cutoff frequency of the flat electro-optical response) and stopband (cutoff frequency at which the electro-optical response is null).⁶⁴ Some ripples are present in the response, originating from cavity effects along the measurement cables, due to the presence of bias-tee and RF adapters in the setup, see Methods. The −3 dB level is defined by averaging the frequency response in the range 2–15 GHz, and using this as reference. Three separate frequency response measurements are performed. They show a similarly flat response up to 67 GHz, with no evidence of signal roll-off. The maximum theoretical PTE photodetector speed is related to the hot electron cooling time t ∼ 2–4 ps (ref (12)), corresponding to 250–500 GHz.²⁴Table 1compares our results with existing reports.^{14−16,23−25} This shows that our GPDs have the highest frequency to date, for zero bias devices. Our scalable technology is a key enabler for next-generation graphene-based transceivers.

Figure 6.

Frequency response of our GPD measured up to 67 GHz. The dashed line indicates the 3 dB drop of the electro-optical response. In the frequency range of the measurement, the roll off of the electro-optical response does not occur.

Table 1. Comparison of WG-Integrated GPDs.

ref	dominant mechanism	dark current (applied bias)	type of graphene	responsivity	bandwidth
this work	PTE	none	CVD	RV = 6 V W–1	>67 GHz (setup-limited)
(14)	PV	none	CVD	RI = 0.016 A W–1	41 GHz
(15)	PTE	none	flake	RV = 4.7 V W–1	18 GHz
	PV/PBM at 0.4 V bias	0.4 V		RI = 0.17 A W–1	(pulse measurement)
(16)	PBM	1 V	CVD	RI = 0.001 A W–1	76 GHz
				RV = 0.13 V W–1
(17)	n/a	1 V	CVD	RI = 0.18 A W–1 at 0.5 V bias	>128 GHz at 1 V bias (setup-limited)
		0.5 V		RV = V W–1 at 0.5 V bias
(18)	PBM	4 mA	CVD	RI = 0.5 A W–1	110 GHz
		(0.4 V)
(19)	PV	1.6 V	CVD	0.36 A W–1	110 GHz
(23)	PTE	none	flake	RI = 0.078 A W–1	42 GHz
				(RI = 0.36 A W–1 at 1.2 V bias)
(24)	PTE	none	CVD	RV = 12 V W–1	42 GHz
(25)	PTE	none	flake	RV = 3.5 V W–1	65 GHz
				RI = 0.035 A W–1

Conclusion

We demonstrated ultrafast scalable double-SLG photodetectors integrated on a Si₃N₄ WG, using SLG as an active channel and split gates, separated by a PVA dielectric. Our devices operate with zero dark current, showing a flat frequency response up to 67 GHz without roll-off. The GPDs are fabricated using deterministically grown single-crystal SLG arrays. These and the fabrication process are compatible with back-end-of-line wafer-scale integration. The use of a polymer dielectric allows us to preserve the SLG quality, unlike conventional dielectrics, such as Al₂O₃ or HfO₂, whose deposition process typically degrades SLG.³⁶ This is also CMOS compatible, since the deposition of PVA poses a low risk of contamination and does not require a high temperature. Thanks to this dielectric we get carrier mobility >16,000 cm² V^–1 s^–1 in ambient conditions and without hBN encapsulation. The high carrier mobility is a key enabler for high-performing graphene-based photonics.¹⁰ Thanks to the polymeric dielectric, the GPD channel has a narrow charge neutrality region (∼35 meV) and high Seebeck coefficient, allowing our devices to operate in a PTE regime. Our GPDs do not require either a doped Si structure for gating²⁵ or nanoscale plasmonic structures,^15,24,25 making them ideal for large-scale integration on any photonic platform, thus a key building block for optical communications.

Methods

Fabrication

The devices are fabricated by depositing 260 nm Si₃N₄ on 15 μm SiO₂via low-pressure CVD. The 1.5 μm-wide WGs are defined in Si₃N₄ using EBL and reactive ion etching. The surface is then planarized with BPTEOS with a final thickness of 25 nm.

Our semidry transfer procedure uses a micrometric stage to laminate the SLG crystals onto the target substrate in a controlled manner, thus avoiding the formation of wrinkles, as shown in the high-contrast optical micrograph in Figure 2a. The SLG single crystals are grown deterministically in arrays,⁴²Figure 2b. For a ∼1.5 × 1.5 cm² substrate, a well-ordered matrix of ∼5000 crystals is grown. Depending on the geometry of the target photonic chip, ∼200–300 of these crystals can be aligned and transferred to WGs, as shown in Figure 2c. In a typical fabrication run, ∼20 crystals are processed into GPDs, which demonstrates the scalability of this approach. Reference (42) showed by selected area electron diffraction that the crystals have a single orientation. The Raman spectrum of a representative crystal in Figure 4a shows no D peak, indicating negligible defects.^54,55 Our single crystals encapsulated in hBN have a room-temperature mobility ∼1.3 × 10⁵ cm² V^–1 s^–1 (at a charge density ∼10¹¹ cm^–2) and a low-temperature (4.2 K) mobility >6 × 10⁵ cm² V^–1 s^–1 (at a charge density ∼10¹¹ cm^–2) and show signatures of electronic correlation, including the fractional quantum Hall effect, as discussed in ref (65).

Typical SLG/PVA/SLG FETs have gate breakdown voltages up to 0.4 MV cm^–1. However, overlapping the top split gate with the bottom metal contacts can give values ∼1 order of magnitude lower. Therefore, we place the split gate structure between the metal contacts. The design requires at least 1 μm of lateral separation between gates and metal source–drain contacts, where the spin-coated dielectric is more planar. Thus, the minimum source–drain distance used in our detectors is 10 μm.

PVA Preparation and Characterization

The PVA solution is prepared by dissolving PVA powder (Sigma-Aldrich, 23–75 kDa, 89% hydrolyzed) in DI water (∼ 18.2 MΩ cm) and then passing the solution through a 0.22 μm filter.

Atomic force microscopy (AFM) (Bruker Dimension Icon) in tapping mode is used to estimate the PVA roughness prior to transfer of the top SLG. A representative AFM image is in Figure 7a. Figure 7b plots the height distribution of 10 × 10 μm² of spin-coated PVA, indicating an RMS roughness ∼0.53 nm.

Figure 7.

(a) AFM image of 10 × 10 μm² surface of PVA. (b) Height distribution of the area in panel (a).

Cut-back measurements⁶⁶ are performed to estimate the optical absorption of PVA spin-coated on WGs. We use five WGs with different lengths ranging from 1 to 5 mm, on top of which 120 nm-thick PVA is deposited by spin-coating. The transmission of the WGs is measured in the 1500–1600 nm range in Figure 8a. At 1550 nm, the extracted losses are ∼2.5 dB mm^–1, Figure 8b.

Figure 8.

(a) Absorption of PVA coating at various lengths on a Si₃N₄ WG as a function of wavelength. (b) Calculated loss of PVA coating per unit length as a function of wavelength.

Refs (67−69) reported relative permittivity ε_r for thin PVA films (thickness <1 μm), ranging from 5⁶⁷ up to well above 20.⁶⁹ To determine the ε_r(PVA) for our devices, we fabricate double-gated FETs on highly p-doped Si wafers (<0.005 Ω cm) with 285 nm SiO₂. SLG growth, transfer, and fabrication are identical to those used for the GPDs in Figure 1. A profile of such structure is shown in Figure 9a. Field-effect measurements are performed on a double-gated device by sweeping top (bottom) gate and keeping the bottom (top) gate fixed. From the applied gate voltage we get n = ε₀ε_rV_g(t × q),⁷⁰ where ε₀ = 8.85 × 10^–12 F m^–1 is the permittivity of free space, ε_r is the relative permittivity, t is gate dielectric thickness (285 nm for SiO₂ and 120 nm for PVA), and q = 1.60 × 10^–19 C is the elementary charge. Using ε_r(SiO₂) = 3.9 (ref (71)), ε_r(PVA) is adjusted to find a good agreement of transfer curves obtained using the two gates, giving ∼14.5 (Figure 9b).

Figure 9.

(a) A cross-section of a double-gate test structure. (b) Comparison of field-effect characteristics when using bottom gate (SiO₂ dielectric) and top gate (PVA dielectric).

DC Characterization

DC measurements are performed by contacting the source–drain channel and the two split gates using micromanipulators with DC needle probes to Keithley 2602 source/measure units. A resistance map of each device is obtained by applying 10 mV to the source–drain channel, and sweeping the voltages applied to the split gates while measuring the current flow. The static photoresponse is measured by coupling a continuous wave (CW) laser at 1550 nm with a single-mode optical fiber and a grating coupler. A polarization controller is used to match the polarization of the optical field at the grating coupler. Photovoltage maps are obtained by imposing zero current between source and drain electrodes and sweeping the voltages applied to both SLG gates.

Due to the SLG band structure and zero band, SLG p–n homojunctions do not work like conventional diodes.²⁶ Due to the interband tunneling in proximity of the junction,^72,73 whenever a bias (0.1–1 V) is applied between source and drain contacts, a large (∼mA) current flows regardless of applied bias sign.⁷³ Therefore, a reverse bias region, where the dark current can be suppressed, does not exist. The only possible condition to avoid a significant (∼mA) dark current is zero bias operation. For this reason, the measurement of the photocurrent at nonzero bias is not done. Furthermore, the goal is to minimize power consumption, hence, there is no incentive in operating the devices at high voltage.

The output of the laser source is amplified by an erbium doped fiber amplifier (EDFA), giving a final power ∼17 dBm (50 mW). The optical power at the output of the polarization controller is ∼15 dBm. The optical power measured from the output grating coupler is ∼ –25 dBm. According to simulations of the optical mode of the WG with the detector stack, the SLG stack is expected to absorb ∼0.09 dB μm^–1, contributing 7.2 dB to the total loss (for a device length ∼80 μm). The remaining 32.8 dB losses are attributed to grating couplers and propagation loss. Grating couplers introduce a 7 dB loss each. The 18.8 dB propagation loss is due to the ∼25 nm BPTEOS cladding on the Si₃N₄ WG. Any residues due to the various fabrication steps can introduce propagation loss. By assuming homogeneously distributed losses along the WG, we estimate a ∼16.4 dB loss between polarization controller and GPD. The optical power reaching the GPD is therefore ∼ –1.4 dBm (700 μW). Negligible propagation losses from the grating coupler to the device could be achieved by using thick (>1 μm) cladding, which can lead to propagation losses as low as 1.5 dB cm^–1 for Si₃N₄ WGs.⁷⁴ Selective removal of oxide could be used to reduce the cladding to ∼20 nm in the device areas, which is required for the evanescent coupling between GPD and WG mode, as shown by the simulations in Figure 3d.

RF Characterization

To measure the optoelectronic bandwidth of the GPD up to 67 GHz, an electrical Vector Network Analyzer (VNA) is employed. We use the measurement scheme of Figure 10a. A distributed feedback (DFB) laser generates a CW optical signal at 1.55 μm. The laser optical power is fed into a Mach–Zehnder modulator (MZM) with 40 GHz BW. The MZM is used to amplitude modulate the DFB CW laser from 2 to 67 GHz, with a sinusoidal signal. The electrical modulation to the MZM is delivered by one of the ports of an electrical VNA (port 1 in Figure 10a). The modulated laser beam is then amplified by an EDFA (Keopsys, with a tunable optical output from 22 to 30 dBm) and guided with an optical fiber up to the GPD, where it is coupled by a grating. The GPD is electrically connected to a second port of the VNA (port 2 in Figure 10a) through electrical probes for on-wafer measurements (Cascade Microtech APC67). Consequently, the modulating electrical frequency at port 1 of the VNA is swept, which is delivered to the MZM, up to 67 GHz. For each frequency sweep step, the GPD photoresponse is measured at port 2. During characterization, the frequency response of the MZM up to 67 GHz is measured. This allows us to correct the experimental results for various frequency-dependent losses introduced by the MZM. To do so, we use an Optical Signal Analyzer (OSA) (Yokogawa AQ6370D) to monitor the modulation depth (red dashed line in Figure 10) at each frequency sweep step of port 1. The optical power at the output of the MZM is P(t) = P₀(1 + m sin 2πf₀t), where P₀ is the constant part of the modulated optical power, f₀ is the RF frequency applied to the MZM, and m is the modulation depth.⁷⁵ As shown in Figure 10b, we perform a short-open-load-through calibration⁷⁶ to eliminate the contribution of the cables to the frequency response. Due to the presence of ripples also in the low-frequency region, we average the frequency response in the range of 2–15 GHz and use this as a reference level to define the −3 dB.

Figure 10.

Block diagram of the instrumental setup for (a) RF characterization of the GPD and (b) calibration of the RF measurement.

Simulations

We calculate the responsivity by adapting the model from ref (32) to the case of a WG-integrated GPD:

2

3

where L_C is the cooling length^30,32 and accounts for the hot electron relaxation,^30,32P_absorbed(x,z) [W m^–2] is the density of absorbed optical power in SLG, where the photocurrent is generated, K_e is the electron thermal conductivity, related to the SLG channel electrical conductivity through the Wiedemann–Franz law, h_g = 0.34 nm is the thickness of an ideal SLG,⁷⁷J⃗ is the current density [A m^–1], and μ(x) is the chemical potential at position x. P_absorbed is the spatial profile of the absorbed optical power density in SLG, extracted from a simulation of the fundamental quasi-TE mode profile of the Si₃N₄ WG (1200 nm × 260 nm, λ₀ = 1550 nm) with the detector stack (see Figure 3d). Eq 3 is solved using a commercial finite elements method solver.

In order to extract L_C, we realize a non-optimized GPD. We compare the measured R_V with those simulated for devices having the same geometry. Simulation parameters like S and channel resistance are obtained by the measurements of FET resistance curves of SLG with PVA as gate dielectric. L_C is varied in a range 0.1–1 μm, since the values reported in literature for this parameter vary from 140 nm⁷⁸ to 1 μm.²³ The value extracted, 130 nm, is compatible with that in polycrystalline CVD SLG encapsulated in hBN.⁷⁸

Seebeck Coefficient

In order to calculate S, we use the field-effect measurement in Figure 11a to extract n*. The model in ref (46) is used to fit the contact resistance, R_C, the field-effect mobility μ_FE and n* (Figure 11b). We also use the model in refs (44 and 45). We find good agreement of the parameters extracted by the two methods.

From ref (46), R can be written as

4

and

5

where N_sq = L/W is the SLG channel aspect ratio, q is the elementary charge, σ is the conductivity, V_CNP is the voltage at CNP, C_gate is the gate capacitance, and V_gate^′ = V_gate – V_CNP.

From eq 5, for n ≫ n*, the conductivity can be approximated as

6

7

Therefore, μ_FE can be extracted by the linear fit in Figure 11c. We get n* ∼ 8.2 × 10¹⁰ cm^–2 and μ_FE ∼ 16,000 cm² V^–1 s^–1. The model of ref (33) is then used to calculate S, as in Figure 11d. We consider screened charged impurities as the main scattering mechanism at low carrier density.^33,79−81 Because of an inhomogeneous dielectric environment, due to the different permittivities of substrate and superstrate, an effective dielectric constant ε_r = (ε_PVA + ε_SiO2)/2⁸² is used. We assume the impurity plane at 0 nm from the SLG. The effective medium theory^33,83 is used to take into account random potential fluctuations in proximity of the Dirac point that break up the density landscape in electron–hole puddles.^80,84 We also estimate the value of n* by taking into account the quantum capacitance C_q. We get n[V_gate] from ref (46):

8

where ,⁸⁵ℏ = 1.05 × 10^–34 J s is the reduced Planck constant, and v_F = 1 × 10⁶ m s^–1 is the Fermi velocity. The obtained value n* ∼ 7 × 10¹⁰ cm^–2 does not lead to a significant change to the calculated S, as shown in Figure 11d (blue dashed curve).

In order to study various split-gate geometries, the photoresponse is simulated by varying the split gate spacing between 0.2 and 1.1 μm. We assume a step S spatial profile (as in Figure 3e) and vary the width of the split gate separation where S = 0. Though such an abrupt transition of chemical potential and S is not expected between the different zones, this allows us to get a lower bound estimation of R_V, as the step profile represents the worst case for evaluation of R_V as a function of gap width. At 1 μm separation, the R_V is ∼78% of R_V obtained with a 200 nm gap, as shown in Figure 11e. This is due to the ∼1.5 μm spatial extension of the optical mode sustained by the Si₃N₄ WG. The resulting T_e profile has its maximum ∼500 nm from the center of the channel (see Figure 3e).

Author Present Address

^⊗ (S.P.) NEST, Istituto Nanoscienze-CNR and Scuola Normale Superiore, Piazza San Silvestro 12, Pisa 56127, Italy.

Author Contributions

^◇ These authors contributed equally.

The authors declare no competing financial interest.