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. 2020 Jul 17;12(32):36355–36361. doi: 10.1021/acsami.0c09541

Improved Current Density and Contact Resistance in Bilayer MoSe2 Field Effect Transistors by AlOx Capping

Divya Somvanshi †, Emanuel Ber †, Connor S Bailey ‡, Eric Pop ‡,§,∥, Eilam Yalon †,*
PMCID: PMC7588022  PMID: 32678569

Abstract

graphic file with name am0c09541_0006.jpg

Atomically thin semiconductors are of interest for future electronics applications, and much attention has been given to monolayer (1L) sulfides, such as MoS2, grown by chemical vapor deposition (CVD). However, reports on the electrical properties of CVD-grown selenides, and MoSe2 in particular, are scarce. Here, we compare the electrical properties of 1L and bilayer (2L) MoSe2 grown by CVD and capped by sub-stoichiometric AlOx. The 2L channels exhibit ∼20× lower contact resistance (RC) and ∼30× larger current density compared with 1L channels. RC is further reduced by >5× with AlOx capping, which enables improved transistor current density. Overall, 2L AlOx-capped MoSe2 transistors (with ∼500 nm channel length) achieve improved current density (∼65 μA/μm at VDS = 4 V), a good Ion/Ioff ratio of >106, and an RC of ∼60 kΩ·μm. The weaker performance of 1L devices is due to their sensitivity to processing and ambient. Our results suggest that 2L (or few layers) is preferable to 1L for improved electronic properties in applications that do not require a direct band gap, which is a key finding for future two-dimensional electronics.

Keywords: molybdenum diselenide, monolayer, bilayer, contact resistance, field-effect transistor, oxide capping, doping, 2D semiconductors

1. Introduction

Reducing contact resistance and finding industry-compatible doping methods are two major challenges for the fabrication of electronic devices based on two-dimensional (2D) materials.1−3 These challenges are tightly interrelated because higher doping concentration can reduce contact resistance. Phase engineering of contacts,4 ultrahigh vacuum metal deposition,5−7 transfer of contacts onto 2D materials,6,8,9 and edge contacts10−12 have been suggested as means of lowering contact resistance. Deposition of substoichiometric oxides was demonstrated for electron doping and contact resistance reduction in MoS2 monolayers (1Ls),13,14 yet further reduction by an order of magnitude needs to be achieved for this technology to prove competitive with silicon-based devices.15,16

There have been extensive efforts invested toward the fabrication of good 1L devices. Interuniversity Microelectronics Centre17 has recently reported 300 mm wafer scale 1L WS2 field effect transistors (FETs) with a current density of ∼10 μA/μm and mobility of few cm2 V–1 s–1. In addition, Smithe et al.18 showed low electrical variability in CVD-grown 1L MoS2 despite the presence of bilayers (2Ls) because of small 1L/2L conduction band offsets. However, to date, there is no clear-cut compelling argument for the use of 1L semiconductors, as opposed to 2L, trilayer (3L), or few layers (FL) for optimized device behavior. Naturally, 1L transistor channels have better electrostatic control; however, FL devices can achieve better contact resistance and mobility and carry more current.19−22 Moreover, the evaporation of metal contacts can damage the top layer of the target material.23 Edge contacts10−12 can be significantly improved in FL devices, thanks to the larger cross sectional area of charge injection. It is clear, therefore, that it would be interesting to investigate 2L (or FL) devices, as their benefits compared to 1L devices may be the key to achieving the sought-after order of magnitude improvement in contact resistance and current density, while preserving the superior electrostatics.

MoSe2 is potentially a good candidate for low power electronic applications with a direct electronic (optical) band gap of ∼2 eV (∼1.5 eV) in 1L and ∼1.1 eV indirect band gap in the bulk.24−29 Furthermore, its ambipolar behavior coupled with relatively high electron and hole mobilities (200 and 150 cm2 V–1 s–1, respectively, in multilayer films)19,30−33 is promising for CMOS applications. Still, MoSe2 remains relatively unexplored in the device community,34 likely because of more challenging growth of large-area high-quality materials as compared with MoS2 and WS2.19,35−37 However, Li et al.19 have recently demonstrated controlled layer-number (1L and FL) large area synthesis of crystalline MoSe2, further advancing the possibility of the 1L versus FL debate. Therefore, comparing the electrical properties of FL and 1L MoSe2 becomes relevant and essential for the purpose of device optimization and is the centerpiece of our research.

In this work, we compare the electrical characteristics of CVD-grown 1L versus 2L MoSe2 FETs. We use Raman spectroscopy maps to identify the number of layers (1L or 2L) of transistor channels and apply AlOx and N2 annealing for passivation and electron doping of both types of devices. Our AlOx-capped 2L devices achieve a record-high current density for atomically thin MoSe2 of ∼65 μA/μm, with an Ion/Ioff > 106 and RC of ∼60 kΩ·μm.30,34,38−40 These results represent ∼20× improvement in RC and ∼30× enhanced current density compared to our (AlOx-capped) 1L devices. The AlOx doping effect aligns well with previously reported data for 1L and FL MoS2 and ReS2 encapsulation.14,41 Our findings suggest that more research focus should be dedicated to exploring synthetic FL (likely 2L or 3L) transistor channels and contacts for future 2D electronics.

2. Results and Discussion

2.1. Material Characterization and Device Structure

Figure 1 shows an optical image of our 1L MoSe2, a schematic diagram of the fabricated device, Raman, and photoluminescence (PL) spectra of the MoSe2 1L with and without AlOx capping. The MoSe2 film was deposited on SiO2/Si substrates by CVD, more details about the process are found in Section S1. The optical image in Figure 1a consists mostly of 1L MoSe2 triangles of size ∼10–20 μm, although some 2L regions (∼1–2 μm) are also present. To evaluate the electrical properties of 1L and 2L MoSe2, we fabricated FETs on SiO2 (tox = 90 nm) on p++ Si substrates, which serve as back gates. A schematic diagram of the as-fabricated 1L FET is shown in Figure 1b. We capped the devices with ∼20 nm substoichiometric aluminum oxide (AlOx) by atomic layer deposition (ALD) for encapsulation and electron doping.14,41 Fabrication details for the MoSe2 devices and AlOx capping are given in the Methods section.

Figure 1.

Figure 1

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Material characterization and device structure. (a) Optical image of CVD-grown 1L MoSe2. The orange colored area is the bare SiO2/Si substrate, and the green triangles are 1L MoSe2 on SiO2/Si substrates. Some 2Ls and FLs are present at the nucleation centers. (b) Schematics of the MoSe2 FET (capped by ∼20 nm AlOx) with Au source/drain electrodes on tox = 90 nm SiO2 with a p++ Si substrate, which serves as a global back gate. (c) Raman spectra of 1L MoSe2 before (orange) and after (blue) AlOx capping. Blue shift (∼1.15 cm–1) and broadening in the A1′ Raman mode are observed, which indicate induced electron doping. (d) PL measurement of MoSe2 before and after AlOx capping. 1L MoSe2 shows a strong peak at 1.52 eV with high intensity, displaying the direct optical band gap of 1L MoSe2. After AlOx capping, a decrease in PL intensity and broadening of ∼25 meV is observed without change in the peak position.

We use Raman and PL spectroscopy (532 nm) for optical characterization of MoSe2 with and without AlOx capping. The measured Raman spectra of bare (orange) and AlOx-capped (blue) 1L MoSe2 are displayed in Figure 1c. The A1′ Raman active mode (out-of-plane vibration of Se atoms) is observed at 240.2 cm–1 for 1L MoSe2, which is consistent with previous reports on the MoSe21L.42−45 We note that A1 notation of this Raman mode is valid for 1L and odd number of (few) layers, whereas it is labeled A1g for bulk and even number of layers.7,46,47 After capping the 1L MoSe2 by AlOx, a blue shift of ∼1.15 cm–1 and broadening in the A1′ Raman mode are observed, demonstrating strong doping dependence, as previously reported for 1L MoS2.48 The room temperature PL spectrum of bare 1L MoSe2 shows a strong emission peak at 1.52 eV with a full-width at half-maximum (fwhm) of ∼50 meV, as shown in Figure 1d. This is attributed to the optical band gap of 1L MoSe2 at the K high symmetry point of the Brillouin zone38,44,49 (we note that the electronic gap of 1L MoSe2 is larger by ∼0.5 eV, the exciton binding energy27,28). After the AlOx capping, however, the PL intensity is quenched and broadened (fwhm ∼ 75 meV), while the peak position remains constant. This is attributed to the creation of defect states and the enhanced recombination rate in 1L MoSe2 due to AlOx capping.14

2.2. Raman Spectroscopy and Optical Microscopy Characterization of 1L and 2L MoSe2 Devices

Figure 2a,b shows the Raman spectral comparison between 1L and 2L MoSe2. The distinction between layer numbers is made clear by the characteristic ∼1 cm–1 red shift from the A1′ peak in 1L MoSe2 to the A1g peak in 2L MoSe224,50 and is further confirmed by the B2g peak that is present only for 2L MoSe2.24,36,43Figure 2c shows the optical image of several FETs fabricated on the same MoSe2 sheet, and Figure 2d overlays the Raman mapping based on the 1L, 2L, Au, and Si spectra on top of Figure 2c. Figure 2e compares the different spectra used for Raman mapping. Figure 2c shows fabricated FETs based on 1L and 2L channels distinctively, which can be used to compare their electrical characteristics.

Figure 2.

Figure 2

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1L and 2L Raman spectra and transistor channel Raman maps. (a) Overlaid Raman spectra of 1L and 2L MoSe2, showing a red shift of ∼1 cm–1 from A1′ in 1L to the A1g mode in 2L. A low intensity B2g Raman mode is present only for 2L MoSe2. (b) Enlarged B2g1 Raman mode for 1L and 2L MoSe2, showing no peak for 1L MoSe2, whereas a clear peak is observed for 2L MoSe2. (c) Optical image of 1L and 2L MoSe2 transistor channels with the area used for Raman mapping highlighted. (d) Raman intensity map of 1L and 2L MoSe2 transistor channels (blue and red) with the gold electrode (yellow) and SiO2/Si substrates (turquoise). (e) Comparison of Raman spectra that correspond to Au, Si, 1L, and 2L MoSe2 channels shown in (d). The intensities in (a), (b), and (e) are normalized by the Si peak.

2.3. Electrical Characteristics of 1L and 2L MoSe2 FETs and AlOx Capping

We analyze the electrical characteristics of bare 1L and 2L MoSe2 FETs and the effect of AlOx capping on the performance of the fabricated devices. It is noted that the reports available on the electrical properties of MoSe2 are limited; mostly, reported studies are focused on either multilayer30,31,33,39 or 1L19,38,40 MoSe2 FETs. Little attention has been given to the electrical characteristics of 2L MoSe2 FET devices.19

Figure 3 compares dual sweep linear and logarithmic (log) scale DC transfer characteristics of 1L (orange) and 2L (black) MoSe2 FETs measured in air at VDS = 1 V. Note that all I–V measurements presented in this work were performed at room temperature with forward and backward sweeps. The bare 1L MoSe2 FET exhibits typical n-FET behavior with a drain current (ID) of ∼0.6 nA/μm at positive gate voltage (VGS) = 40 V, and the on–off current ratio (Ion/Ioff) is ∼102. Such poor performance is consistent with previous reports.36,40 The 2L MoSe2 FET shows ambipolar behavior, an ID of ∼6.5 nA/μm at VGS = 40 V with an Ion/Ioff of ∼103 and an ID of ∼0.1 nA/μm at VGS = −40 V. Li et al. observed similar transport behavior of 2L MoSe2 devices.19 The uncapped 1L and 2L MoSe2 FETs did not exhibit improvements in their current density following annealing in N2 ambient at 250 °C for 30 min.

Figure 3.

Figure 3

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Electrical characteristics of 1L and 2L MoSe2 FETs. (a) Transfer characteristics of 1L and 2L MoSe2 FETs at VDS = 1 V, measured in air. A typical n-FET behavior is observed for 1L MoSe2, whereas an ambipolar behavior is observed for 2L MoSe2 with dominant ID at positive VGS. (b) Transfer characteristics of the 2L MoSe2 FET with (blue) and without (black) AlOx capping. An increase in Ion, higher Ion/Ioff (∼105), and reduced hysteresis are observed for the capped devices. (c) Hole and (d) electron current output characteristics of the 2L MoSe2 FET with AlOx capping.

Next, the devices were capped by AlOx to improve their electrical characteristics. Figure S1 compares the transfer characteristics of the 1L MoSe2 FET before and after AlOx capping, demonstrating a less significant change in Ion/Ioff and ID with some hysteresis. Figure 3b shows transfer characteristics of uncapped and AlOx-capped 2L MoSe2 devices, and significant improvement in ambipolar characteristics is observed. The capped 2L devices show an improved Ion/Ioff of ∼105, a negative shift in threshold voltage (VT) of ∼−2.1 V across 90 nm SiO2 gate dielectric, and a field-effect mobility (μFE) of ∼2 cm2 V–1 s–1 (compared to ∼0.3 cm2 V–1 s–1 for uncapped devices). The increased ID and lower hysteresis with AlOx capping are consistent with those of AlOx-encapsulated MoS2 devices reported in the literature.14,41,51

Figure 3c,d shows the hole and electron current output characteristics of 2L MoSe2 FETs after AlOx capping. A nonlinear output characteristic is observed because of the presence of a Schottky barrier at the source and drain contacts.52−55ID increases with the increase in positive and negative VGS from 10 to 40 V, which also confirms the ambipolar characteristics of the device. It is observed that the performance significantly improves after AlOx capping, which is attributed to the removal of unintentional adsorbents in the transistor channel, thanks to passivation by oxide capping.41

2.4. High-Performance AlOx-Doped 2L MoSe2 FETs

After AlOx capping, annealing is performed in N2 ambient at 200 °C for 40 min. Figure 4a compares transfer characteristics of the AlOx-capped 2L MoSe2 FET before (blue) and after (red) N2 annealing. A negative shift in VT of ∼−7.5 V is observed after annealing, which indicates increased electron concentration. Both electron and hole currents are enhanced with an electron mobility μFE of ∼4 cm2 V–1 s–1. The ON current increases by more than ∼25%, with an improved Ion/Ioff of ∼106. Figure S1 compares the transfer characteristics of the 1L MoSe2 FET before and after N2 annealing, exhibiting similar trends for VT, although Ion/Ioff does not change significantly. The high Ion/Ioff ratio after N2 annealing can be partially attributed to the improvement in ID that is likely enabled by the lower resistance Au/2L contacts compared to Au/1L MoSe2 because of the lower Schottky barrier height and reduced surface damage from contact evaporation.21,22,56

Figure 4.

Figure 4

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AlOx doping and improved performance of 2L MoSe2. (a) Comparison of transfer (linear and log scale) characteristics before (blue) and after (red) N2 annealing. An increase in Ion, an improved Ion/Ioff ratio of > 106, and a threshold voltage shift of ΔVT = −7.5 V are observed, which indicate induced electron doping. (b) Transfer and (c) output characteristics of a 500 nm-long AlOx-capped 2L MoSe2 FET after N2 annealing at 200 °C for 40 min. The transfer curve shows a peak current density of ∼65 μA/μm at VDS = 4 V, and the output curve shows linear ID–VDS relation.

Because the devices were measured in air, the role of AlOx capping is twofold: it passivates the atomically thin channel from the air ambient and it may also increase the electron density. The effects of AlOx capping and annealing on our MoSe2 devices can be explained in a similar manner to the recent reports on MoS2 and ReS2 FETs.14,41 Based on internal photoemission measurements of 1L MoSe2,57 its band alignment with AlOx allows for electron doping, namely, its conduction band minima lie below donor-type defects in AlOx.41

Figure 4b shows the transfer characteristics of the AlOx-capped 2L MoSe2 FET (channel length L = 500 nm) after N2 annealing, reaching a peak current density of ∼65 μA/μm at VDS = 4 V with an Ion/Ioff of > 106. This device exhibits good performance with the best current density for an atomically thin (here 2L) MoSe2-based FET reported to date without degradation of the Ion/Ioff ratio.19,31,33,34,40 Comparable performance was achieved in 2L MoSe2 by Li et al.,19 although a quantitative comparison is difficult because the channel width was not well defined. The output characteristic of the same device is shown in Figure 4c, where VGS varies from 10 to 60 V with minimal hysteresis. The improved contact resistance and reduced Schottky barrier result in ohmic behavior of the L = 500 nm channel at large positive gate bias. Next, we show that the improved current density in 2L versus 1L MoSe2 devices correlates well with reduction in contact resistance.

2.5. MoSe2 Contact Resistance

We use the transfer length method (TLM) and Y-function technique to extract the RC of our AlOx-capped 1L and 2L MoSe2 FETs, before and after N2 annealing. For the TLM measurements, we have included short channels of ∼100 nm for accurate estimation of RC.5Figure 5a shows the extraction of RC from the TLM measurement for 1L MoSe2 FETs, where symbols represent experimental data and lines represent the linear fit. The carrier density is evaluated from the linear charge dependence on gate overdrive voltage given by n ≈ Cox (VGS – VT)/q where Cox ≈ 38.4 nF/cm2 is the oxide capacitance for the 90 nm SiO2, q is the elementary charge, VGS is the gate voltage, and VT is the threshold voltage determined by the linear extrapolation method for each channel length.

Figure 5.

Figure 5

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MoSe2 contact resistance. (a) RTOTvs channel length (L) for extraction of RC and Rsh before (blue) and after (red) N2 annealing for AlOx-capped 1L MoSe2. A significant decrease in RC and Rsh is observed with N2 annealing at 200 °C for 40 min; symbols are experimental data, and lines are linear fits to the experimental data. (b) RCvs VGS from the Y-function method for the 500 nm-long 2L MoSe2 FET. From the strong accumulation regime, we extract an RC of ∼60 kΩ·μm for 2L MoSe2 at VDS = 1 V and a VGS of > 35 V.

Decent linear fits are obtained for the measured total resistance (normalized by width) RTOTversus channel length L for our AlOx-capped MoSe2 before and after N2 annealing, signifying relatively uniform properties in the TLM array. The intercept of the linear fit yields 2RC, and the slope yields the sheet resistance (Rsh). We extract RC = 8 ± 2 MΩ·μm at 300 K for n ≈ 3.3 × 1012 cm–2 (with the uncertainty reflecting 96% confidence intervals) for AlOx-doped 1L MoSe2 (blue). Importantly, RC is reduced to 1.2 ± 0.4 MΩ·μm at 300 K for n ≈ 5.5 × 1012 cm–2 with a confidence interval of 98% after N2 annealing treatment (red). The value of Rsh is ∼42 MΩ/□ for AlOx-capped 1L MoSe2, and it decreases to ∼14MΩ/□ after N2 annealing. This is the first characterization of contact resistance in 1L MoSe2, and at this point, a substantial improvement in RC is needed to meet the requirements for practical applications. It appears that annealing in inert ambient (e.g., N2) after AlOx capping is an important step in the reduction of RC in 1L 2D semiconductors; a similar observation was reported in AlOx-doped MoS2 devices.14

For the 2L MoSe2 devices, no TLM arrays were available, and we have therefore used the Y-function method58,59 to evaluate their RC. Details about Y-function fitting are given in Section S3. The Y-function extraction for the AlOx-capped 2L MoSe2 FET after N2 annealing (L = 500 nm and W = 1.5 μm) shows a VT of ∼18 V (forward sweep) and a μ0 of ∼3 cm2 V–1 s–1 (Figure S2). Figure 5b displays RC extraction using the Y-function method at VDS = 1 V. The dashed (black) line represents an averaged RC value of ∼60 kΩ·μm for a VGS of > 35 V. It is noted that the RC calculated from the Y-function18,58 is an upper bound, and the true RC could be lower. Our results show that 2L MoSe2 devices achieve ∼20× better contact resistance compared with 1L, highlighting the need to optimize the layer number in 1L to FL 2D semiconductor devices.

Before concluding, we note that annealing at 350 °C in inert ambient was performed to test the stability of MoSe2 devices to the back end of the line processing temperatures. 1L devices improved upon annealing (Section S5), whereas 2L devices could not be tested because of the limited number of devices (which underwent electrical breakdown during measurements before this final annealing step). These results suggest that although selenides are less stable in air compared with sulfides, proper encapsulation can provide sufficient protection.

3. Conclusions

In summary, we report the first study of CVD-grown 1L versus 2L MoSe2-based FETs with AlOx doping. The Raman spectra and mapping depict the individual 1L and 2L devices. A stable electron doping effect was observed for AlOx-capped 2L devices after N2 annealing treatment, and an improved current density of ∼65 μA/μm and a good Ion/Ioff of > 106 with minimal hysteresis were achieved. The 2L MoSe2 devices show ∼30× better current density and ∼20× lower contact resistance compared with 1L devices. These results also indicate that a two-step process (i.e., AlOx capping with N2 annealing) is very promising for the passivation and electron doping of CVD-grown 2L MoSe2 FETs. We conclude that future work in this field should also focus on growing 2L (or otherwise atomically thin FL) MoSe2 and not exclusively 1L for high-performance 2D electronics applications.

4. Methods

4.1. MoSe2 FET Fabrication

MoSe2 was deposited on 90 nm of thermally grown SiO2 on Si (p++) substrates (<5 mΩ·cm) using the chemical vapor deposition (CVD) process (Section S1). Electron beam lithography (EBL) is used to define electrodes, channel area, and probe pads (100 μm × 100 μm) in three separate steps. Au metal electrodes of 50 nm were deposited by e-beam evaporation under high vacuum (∼5.8 × 10–8 Torr) conditions without any adhesion layer to achieve a clean contact interface. We used O2 plasma reactive ion etching (pressure = 20 mTorr and an O2 flow of 20 sccm) for 30 s to form well-defined channels. Furthermore, the contact pads of Ti (15 nm)/Au (50 nm) are deposited by the e-beam evaporation method under a vacuum condition of ∼9 × 10–7 Torr, followed by lift-off in acetone and IPA cleaning.

4.2. AlOx Capping and Annealing

Before AlOx capping, a seed layer of Al metal of thickness ∼1.5 nm (a deposition rate of ∼0.5 Å/s) was deposited on the MoSe2 devices by e-beam evaporation. The Al seed layer oxidizes upon exposure to air and serves as a nucleation layer for AlOx. Next, annealing was performed in a forming gas (FG) atmosphere at 250 °C for 30 min. AlOx (20 nm) was deposited by ALD using trimethylaluminum (TMA) and water (H2O) as precursors at 150 °C. Before the growth in ALD, we ran 10 nm Al2O3 deposition for chamber passivation and ran six washing cycles of TMA. AlOx covers the whole transistor structure, both the contact region and the channel regions, as shown schematically in Figure 1b. After AlOx deposition, annealing is performed in a N2 atmosphere at 200 °C for 40 min to further improve the device characteristics.

4.3. Characterization

The MoSe2 sample topography was first characterized using optical microscopy (Zeiss Axiotron). Raman and PL spectroscopy was carried out using a Horiba LabRam Revolution HR instrument with a 532 nm laser, 1800 1/mm grating, and objective of a 50× long working distance, while a Si peak position at 520 cm–1 was used as the standard peak reference. Raman mapping was performed with a WITec alpha300 R instrument using 532 nm laser, 1800 g/mm grating, 50x objective lens, and WITec Suite FIVE software for analysis. Raman and PL spectra were employed to characterize the thickness, uniformity, and the material quality of the MoSe2 samples. All the electrical characterizations were carried out with a Keysight B1500 semiconductor parameter analyzer at room temperature in air.

Acknowledgments

Fabrication was carried out at the Technion Micro–Nano Fabrication & Printing Unit (MNF&PU) with partial support from the Russell Berrie Nanotechnology Institute (RBNI). We thank A. Goldner for technical support with EBL, G. Frey and M. Beregovsky for assistance with ALD, and E. Koren and S. Katznelson for providing the Raman mapping setup. D.S. would like to thank the Department of Science and Technology (DST), India, for the INSPIRE faculty award (DST/INSPIRE/04/2017/000147) and for the permission to carry out postdoctoral research work at Technion-IIT Haifa. E.Y. is a Northern Californian Career Development Chair Fellow. C.S.B. and E.P. acknowledge funding from the Stanford System X Alliance and from ASCENT, one of the six centers in JUMP, a Semiconductor Research Corporation (SRC) program sponsored by DARPA.

Supporting Information Available

The Supporting Information is available free of charge at https://pubs.acs.org/doi/10.1021/acsami.0c09541.

  • CVD growth of MoSe2; effect of AlOx capping and N2 annealing on the 1L MoSe2 FET; Y function fitting of the AlOx-capped 2L MoSe2 FET with N2 annealing; forming gas annealing effect on MoSe2 electrical characteristics; and high temperature annealing effect on MoSe2 electrical characteristics (PDF)

Author Present Address

# Department of Electronics and Tele-Communication Engineering, Jadavpur University, Kolkata-700032, India.

Author Contributions

⊥ D.S. and E.B. contributed equally.

The authors declare no competing financial interest.

Due to production error, the abstract graphic was incorrect in the version published on July 31, 2020. The corrected paper was reposted on August 3, 2020.

Supplementary Material

am0c09541_si_001.pdf (963.6KB, pdf)

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