A Time-Domain Readout Technique for Neural Interfaces Based on VCO-Timestamping

Abstract

CMOS neural interfaces are aimed at studying the electrical activity of neurons and may help to restore lost functions of the nervous system in the future. The central function of most neural interfaces is the detection of extracellular electrical potentials by means of numerous microelectrodes positioned in close vicinity to the neurons. Modern neural interfaces require compact low-power, low-noise readout circuits, capable of recording from thousands of electrodes simultaneously without excessive area consumption and heat dissipation. In this article, we propose a novel readout technique for neural interfaces. The readout is based on a voltage-controlled oscillator (VCO), the frequency of which is modulated by the input voltage. The novelty of this work lies in the postprocessing of the VCO output, which is based on generating digital timestamps that contain temporal information about the oscillation. This method is potentially advantageous, because it requires mostly digital circuitry, which is more scalable than analog circuitry. Furthermore, most of the digital circuitry required for VCO-timestamping can be shared among several VCOs, rendering the architecture efficient for multi-channel architectures. This article introduces the VCO-timestamping concept, including theoretical derivations and simulations, and presents measurements of a prototype fabricated in 0.18-μm CMOS technology. The measured input-referred noise in the 300 Hz–5 kHz band was 5.7 μV_rms, and the prototype was able to detect pre-recorded extracellular action potentials.

I. Introduction

ACTION potentials (APs) are voltage signals generated by electrogenic cells, such as cardiomyocytes or neurons, and result from transmembrane ionic currents. In the brain, APs are the main feature of neuronal information processing, and their study is key for progress in neuroscience and the development of treatments to restore lost functions. APs can be detected by placing small electrodes close to neurons, since the ionic transmembrane currents cause small electrical-potential variations in the extracellular medium adjacent to the cell membrane. The amplitude of these voltage variations, known as extracellular action potentials (EAPs), is typically smaller than 1 mVpp, with the majority of the signal power contained within the 300 Hz–5 kHz band [1], [2].

Neural information processing involves a very large number of neurons, while electrophysiology tools have been traditionally limited in the number of electrodes that can be used in parallel. Over the last decades, CMOS technology has gained popularity for the implementation of active neural interfaces, enabling the recording from thousands of electrodes simultaneously [3], [4], [5], [6], [7], [8], [9], [10], [11]. The number of readout channels is typically limited by either power and heat dissipation, which may lead to tissue damage, or silicon real estate, which leads to increased fabrication costs and bulkier devices.

Analog circuitry typically consumes a significant part of the silicon area and overall power and requires considerable design efforts. Furthermore, designers tend to avoid deep submicron technologies to reduce manufacturing costs, since analog circuitry does not benefit from CMOS technology scaling [12], [13], [14], [15]. Larger feature sizes also limit the performance of on-chip digital signal processing circuits, which are not efficient in old CMOS nodes, so that signal processing is frequently performed off chip. Voltage-controlled oscillator (VCO)-based analog-to-digital converters (ADCs) have emerged as area- and power-efficient alternatives to other to well-established architectures, such as successive-approximation-register (SAR) ADCs or classical delta-sigma (ΔΣ) modulators [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26]. VCO-ADCs feature different topologies, such as open-loop converters [17], [21], [25], ΔΣ modulators with VCO-based quantizers [19], [20], or ΔΣ modulators with VCO-based integrators [23], [24], [27]. In these implementations, a significant part of the signal path is built by using standard digital cells and minimizing large analog circuits, such as operational amplifiers. Therefore, these “mostly-digital” circuits are particularly suitable for modern CMOS technologies, which are optimized for implementations of compact and efficient digital circuitry.

In this manuscript, we propose a new VCO-ADC topology designed for neural interfaces. The overall idea is the use of one VCO-based input-stage per channel, each of which generates a digital oscillation, modulated in frequency, which can then be processed using digital circuitry. However, instead of building one standalone VCO-ADC per channel frequency, we propose the use of shared digital circuitry to capture the position of VCO edges (referred to as “timestamps” in this work), which contain enough information to reconstruct the oscillation frequency and the input voltage after postprocessing. As illustrated in Fig. 1, this readout strategy is aimed at simplifying the on-chip analog circuitry in the system at the costs of adding on-chip and off-chip digital circuitry.

Fig. 1.

(a) Simplified block diagram of a generic voltage microsensor array, consisting of a set of preamplifiers (A₁), anti-aliasing filters (AAF), a multiplexer (MUX), shared amplification stages (A₂) and ADCs, and off-chip digital signal processing (DSP) logic. (b) Simplified block diagram of the proposed readout. Each input modulates the oscillation frequency of a VCO, the digital output of which generates a sequence of timestamps on-chip. The input voltage can be inferred from the oscillation frequency, which is estimated off-chip, based on the relative position of the timestamps. The proposed readout is aimed at simplifying on-chip analog circuitry at the costs of more complex off-chip digital processing.

This article is organized as follows. Section II describes the readout architecture, including the fundamentals of voltage-to-frequency conversion and timestamping. Section III elaborates on how the input signal can be reconstructed from an incomplete collection of timestamps. In Section IV, we evaluate the performance of the system by simulation of a system that has been exposed to different input signals. Section V describes a prototype, manufactured in 0.18-μm CMOS technology, and shows the results of electrical characterization with sinusoids and pre-recorded neuronal signals. Finally, Section VI concludes the article with a discussion about the potential of the proposed architecture.

II. Readout Architecture

The proposed readout system features three steps: voltage-to-frequency conversion, frequency-to-digital conversion (timestamping), and signal reconstruction. This section focusses on the first two steps, which comprise the on-chip mixed-signal operations required to transform analog input signals into digital ‘timestamps’. The algorithms required for the third step, signal reconstruction, are described in Section III.

A. Voltage-to-Frequency Conversion

The instantaneous oscillation frequency of a VCO can be described as

$$f_O\left(t\right)=f_{fr}+g\left({\upsilon }_{\text{in}}\left(t\right)\right)+f_n\left(t\right),$$ (1)

where f_fr represents the free-running oscillation frequency, ν_in(t) is the input voltage, g(·) is a function that represents the relation between input voltage and change in oscillation frequency, and f_n(t) is the random frequency fluctuation due to noise (visible as phase noise or jitter). Assuming small input signals, the oscillation frequency can be linearized as

$$f_O\left(t\right)=f_{fr}+K_{\text{VCO}}\left({\upsilon }_{\text{in}}\left(t\right)+{\upsilon }_{\text{IRN}}\left(t\right)\right),$$ (2)

where K_VCO represents the gain of the oscillator (in Hz/V), and ν_IRN(t) describes phase noise as input-referred noise. For simplicity, the oscillator is considered to be linear and noise-free for the rest of the manuscript. Nevertheless, the nonlinearities and phase noise of the VCO are the fundamental limitation in the accuracy of the voltage-to-frequency conversion process. A procedure to estimate the influence of nonlinearities and phase noise in VCOs can be found in [28].

Fig. 2 depicts a simplified model of a VCO, including the most relevant signals. Part of these signals can be physically measured in a circuit, such as the input voltage ν_in(t) and the output oscillation w(t). Other signals are only virtual and cannot be directly observed, such as the oscillation frequency f_O(t), unwrapped phase φ(t), or wrapped phase φ_w(t). The oscillation frequency (in Hz) follows (2), assuming ν_IRN(t) = 0. The oscillator phase (in radians) increases unbounded, since it is the integral of the oscillation frequency–always positive–over time. The wrapped phase is the modulo-2π of the unwrapped phase and is, therefore, contained in the interval [0,2π). The waveform function wf(·) describes the output voltage as a function of the wrapped phase, which - for a digital oscillation - can be

$$w\left(t\right)=wf\left({\phi }_w\left(t\right)\right)=\{\begin{array}{ll}1,\hfill & \text{if}{\phi }_w\left(t\right)<\pi \hfill \\ 0,\hfill & \text{if}{\phi }_w\left(t\right)\ge \pi \hfill \end{array}.$$ (3)

Fig. 2.

(a) Noise-free linear VCO modeled as a phase integrator. (b) Example of the most relevant signals of the VCO.

The rising edges of w(t) indicate the timepoints at which the unwrapped phase crosses a multiple of 2π. These timepoints can be listed as a discrete sequence t_r[i], so that φ_w(t_r[i]) = 0. Although a similar sequence could be built using falling edges, in that φ_w(t_f[i]) = π, the rest of the manuscript only considers rising edges for simplicity.

The oscillation period can be calculated as the first difference of t_r[i],

$$T_O\left[i\right]=t_r\left[i\right]-t_r\left[i-1\right],$$ (4)

where T_O[i] represents the average value of the instantaneous oscillation period (T_O(t)) for t_r[i-1] ≤ t ≤ t_r[i]:

$$T_O\left[i\right]=\frac{1}{t_r\left[i\right]-t_r\left[i-1\right]}{\displaystyle {\int }_{t_r\left[i-1\right]}^{t_r\left[i\right]}{T}_O\left(t\right)}dt.$$ (5)

Similar discrete sequences can be defined to describe the oscillation frequency and the input signal and their interdependence:

$$f_O\left[i\right]=\frac{1}{t_r\left[i\right]-t_r\left[i-1\right]}{\displaystyle {\int }_{t_r\left[i-1\right]}^{t_r\left[i\right]}{f}_O\left(t\right)}dt,$$ (6)

$${\upsilon }_{\text{in}}\left[i\right]=\frac{1}{t_r\left[i\right]-t_r\left[i-1\right]}{\displaystyle {\int }_{t_r\left[i-1\right]}^{t_r\left[i\right]}{\upsilon }_{\text{in}}\left(t\right)}dt,$$ (7)

$$f_O\left[i\right]=\frac{1}{T_O\left[i\right]}=f_{fr}+K_{\text{VCO}}{\upsilon }_{\text{in}}\left[i\right].$$ (8)

From (4) and (8) we can conclude that the discretized input signal ν_in[i] can be calculated from sequence t_r[i]. Furthermore, as shown in (7), the discretized input voltage results from the averaging of ν_in(t). This averaging is equivalent to a low-pass filter that suppresses signal variations that are faster than the oscillation frequency and inherently acts as an antialiasing filter.

B. Frequency-to-Digital Conversion

The proposed frequency-to-digital conversion scheme is based on timestamping. We assign “timestamping” to the generation of digital words –“timestamps”– that encode the timepoints at which oscillation pulses initiate. In its simplest implementation that we call “continuous timestamping” a “timestamper” is constantly monitoring the output of the VCO and generates a timestamp at every detected rising edge. The resulting sequence represents t_r[i] which, according to (4) and (8), can be used to recover the oscillation period and input signal. However, this approach would require one timestamper per VCO, which would result in relatively high power and area consumption. Therefore, we propose an alternative approach called here ‘multiplexed timestamping’, for which a single timestamper is shared among several VCOs, following the structure presented in Fig. 1(b).

1). Continuous Timestamping

Fig. 3(a) shows the block diagram of the proposed timestamper, which consists of a time reference generator (TRG) and a register. The TRG generates a digital word r(t), the value of which changes in every cycle of the clock clk(t) in a deterministic manner, such as an up-count. The register samples r(t) at every rising edge of the VCO oscillator w(t), generating a digital sequence m[i].

Fig. 3.

(a) Block diagram of the proposed timestamper. (b) Example of the most relevant signals of the timestamper.

Fig. 3(b) shows an example of the relevant signals of the proposed timestamp generator. The output of the up-counter is, neglecting overflow,

$$r\left(t\right)=\text{floor}\left(f_{\text{clk}}t\right),$$ (9)

where f_clk is the frequency of clk(t), and the floor(·) function returns the greatest integer number, which is less than or equal to its argument. The value of m[i] depends on the timepoint at which the latest rising edge of the oscillation has occurred:

$$m\left[i\right]=r\left(t_r\left[i\right]\right)=\text{floor}\left(f_{\text{clk}}{t}_r\left[i\right]\right).$$ (10)

The ‘floor’ function is equivalent to a quantizer, that can be modeled as additive quantization error e[i]:

$$m\left[i\right]=f_{\text{clk}}{t}_r\left[i\right]+e\left[i\right].$$ (11)

Note that the oscillation period can be estimated, combining (11) and (4), as follows:

$$\widehat{T_o}\left[i\right]=\frac{\left(m\left[i\right]-m\left[i-1\right]\right)}{f_{\text{clk}}}=T_o[i]+\frac{\left(e\left[i\right]-e\left[i-1\right]\right)}{f_{\text{clk}}}.$$ (12)

where $\widehat{T_o}\left[i\right]$ denotes the estimated oscillation period. The difference between the oscillation period and the estimated oscillation period is due to the time quantization error (i.e., due to the limited resolution of the timestamper).

Assuming no correlation between the oscillation w(t) and the reference clock clk(t), quantization error e[i] can be considered random, resulting in white quantization noise bounded to [0,1). From (12), we conclude that the time quantization error is high-pass filtered, resulting in first-order noise-shaping. Furthermore, as expected, increasing the frequency of the reference clock mitigates the effect of quantization noise, since higher clock frequencies increase the resolution of the timestamper.

The estimated input voltage $\widehat{{\upsilon }_{\text{in}}}\left[i\right]$ can be calculated from the complete sequence of timestamps m[i] by combining (12) and (8).

2). Multiplexed Timestamping

To minimize the area and power consumption per channel, the timestamper can be shared among several VCOs without a significant loss of accuracy. Fig. 4(a) depicts the on-chip stage of the system introduced in Fig. 1(b), with N VCOs multiplexed to a single timestamper. The sequence generated by the timestamper, m_mux[i], contains timestamps triggered by all the VCOs that have been eventually selected by the multiplexer. For simplicity, we consider only the first VCO (VCO₁) for the rest of the analysis. We can define m_S1[i] as the subset of timestamps contained in m_mux[i] triggered by VCO₁, while its corresponding selection signal (ϕ₁(t)) was active. Fig. 4(b) shows the most significant signals related to VCO₁. As in Section II-A, we can define sequence t_r1[i] as the timepoints at which VCO₁ rising edges occur. The selected rising edges, t_S1[i], are the ones captured by the timestamper and occurred while ϕ₁(t) = 1. The sequence t_S1[i] can be defined as

$$t_{S1}\left[i\right]=t_r\left[S_1\left[i\right]\right],$$ (13)

where S₁[i] is a discrete sequence of integer numbers denoting which rising edges have been selected.

Fig. 4.

(a) Block diagram of multiplexed VCOs sharing one timestamper. (b) Example of the subsampling of t_r1[i] to generate t_S1[i]. In this example, the first values of S₁[i] were {0, 4, 8, 13}, and the first values of N_S1[i] were {4, 4, 5}.

Like in (11), the value of timestamps can be described as

$$m_{S1}\left[i\right]=f_{\text{clk}}{t}_{S1}\left[i\right]+e_{S1}\left[i\right],$$ (14)

and the time elapsed between two consecutive timestamps can be described as

$$\begin{array}{l}\Delta t_1\left[i\right]=t_{S1}\left[i\right]-t_{S1}\left[i-1\right]=\frac{m_{S1}\left[i\right]-m_{S1}\left[i-1\right]}{f_{\text{clk}}}\\ -\frac{e_{S1}\left[i\right]-e_{S1}\left[i-1\right]}{f_{\text{clk}}}.\end{array}$$ (15)

The average oscillation period between two consecutive timestamps is therefore

$$T_O\left[i\right]=\frac{1}{t_{S1}\left[i\right]-t_{S1}\left[i-1\right]}{\displaystyle {\int }_{t_{S1}\left[i-1\right]}^{t_{S1}\left[i\right]}{T}_O\left(t\right)dt=\frac{\Delta t_1\left[i\right]}{N_{S1}\left[i\right]},}$$ (16)

where N_S1[i] represents the number of oscillations that occurred between t_S1[i] and t_S1[i-1] and can be defined as

$$N_{S1}\left[i\right]=S_1\left[i\right]-S_1\left[i-1\right].$$ (17)

Finally, similarly to (12), the oscillation period can be estimated as

$$\begin{array}{l}\widehat{T_{o1}}\left[i\right]=\frac{\left(m_{S1}\left[i\right]-m_{S1}\left[i-1\right]\right)}{N_{S1}\left[i\right]\cdot f_{\text{clk}}}\\ =T_{o1}\left[i\right]+\frac{\left(e_{S1}\left[i\right]-e_{S1}\left[i-1\right]\right)}{N_{S1}\left[i\right]\cdot f_{\text{clk}}}.\end{array}$$ (18)

Note that, while in (12) $\widehat{T_{o1}}\left[i\right]$ can be computed directly from the recorded timestamps, (18) also requires N_S1[i], which is a priori unknown. The following section explains how this unknown parameter can be estimated under certain assumptions, which then enables the reconstruction of $\widehat{T_{o1}}\left[i\right]$ and $\widehat{{\upsilon }_{\text{in}1}}\left[i\right]$.

III. Signal Reconstruction

Consider the sequence m_S1[i], a subset of timestamps captured while ϕ₁(t) is active. This sequence is the output of the hardware described in Section II and is the only data available off-chip for the reconstruction of the signal $\widehat{{\upsilon }_{\text{in}1}}\left[i\right]$. For simplicity, we assume for the rest of this section that f_clk is large enough, so quantization noise can be neglected and

$$t_{S1}\left[i\right]\approx \frac{m_{S1}\left[i\right]}{f_{\text{clk}}}.$$ (19)

The primary challenge of signal reconstruction is to find the number of oscillations that occurred between two consecutive timestamps, N_S1[i]. From the description given in the previous section, we know that the number of oscillations can be - in theory - any natural number:

$$N_{S1}\left[i\right]\in \mathbb{N}.$$ (20)

We do not have enough information to find N_S1[i] and ν_in1[i], since there are infinite possible numbers satisfying this condition. However, we can incorporate a-priori knowledge about the hardware and the input signal to facilitate finding the correct number of oscillations.

Fig. 5 shows an example of a reconstruction scenario, in which a VCO and a timestamper have been simulated with f_fr = 2MHz, K_VCO = 20 MHz/V, ν_in1 = 0, and random N_S1[i] ∈ [4, 6]. For each sample, we are plotting three possible estimations of the input voltage $\left(\widehat{{\upsilon }_{\text{in}1}}\left[i\right]\right)$ for different possible values of N_S1[i]. It can be observed that, although all the plotted values are feasible from a mathematical point of view, it will be possible to identify the correct values of $\widehat{N_{S1}}\left[i\right]$ and $\widehat{{\upsilon }_{\text{in}1}}\left[i\right]$, if the input signal is known to meet certain conditions.

Fig. 5.

Example of correct (solid line) and incorrect (dashed lines) reconstructions for f_fr = 2MHz, K_VCO = 20 MHz/V, ν_in1 = 0, and random N_S1[i] ∈ [4, 6].

A. Input Signal Amplitude Minimization

If the input signal is known to be small, signal reconstruction can be based on finding the sequence N_S1[i] that results in the smallest possible input signal. Combining (8) and (16) we get:

$${\upsilon }_{\text{in}1}\left[i\right]=\frac{N_{S1}\left[i\right]}{\Delta t_1\left[i\right]\cdot K_{\text{VCO}}}-\frac{f_{fr}}{K_{\text{VCO}}},$$ (21)

$$N_{S1}\left[i\right]=\Delta t_1\left[i\right]\cdot \left(f_{fr}+K_{\text{VCO}}{\upsilon }_{\text{in}1}\left[i\right]\right).$$ (22)

If the input voltage is known to be small, we can solve (22) for ν_in1[i] = 0, and round the result to find an integer sequence N_S1[i] that satisfies (20):

$$\widehat{N_{S1}}\left[i\right]=\text{round}\left(\Delta t_1\left[i\right]\cdot f_{fr}\right).$$ (23)

This approach is computationally efficient and leads to valid reconstructions, if the input signal is small enough. This method fails, if the input signal is outside the following interval:

$$\begin{array}{l}{\upsilon }_{\text{in}1}\left[i\right]\\ \in \left(\frac{N_{S1}\left[i\right]-0.5}{\Delta t_1\left[i\right]\cdot K_{\text{VCO}}}-\frac{f_{fr}}{K_{\text{VCO}}},\frac{N_{S1}\left[i\right]+0.5}{\Delta t_1\left[i\right]\cdot K_{\text{VCO}}}-\frac{f_{fr}}{K_{\text{VCO}}}\right).\end{array}$$ (24)

Note, that this approach requires accurate a priori knowledge of f_fr, since - from the reconstruction standpoint - deviations in the free-running oscillation frequency (Δf_fr) are indistinguishable from input offset (Δν_in = Δf_fr/K_VCO). Therefore, according to (24), unknown deviations in f_fr reduce the valid input range of this reconstruction algorithm.

B. Input Signal Variation Minimization

If the input signal is known to be slow, signal reconstruction can be based on minimizing the total signal variation (TSV), defined here as the sum of the absolute value of the first difference:

$$TSV\left(x\right)={\displaystyle \sum _{i=-\infty }^{+\infty }\left|x\left[i\right]-x\left[i-1\right]\right|}.$$ (25)

As shown in Fig. 5, incorrect reconstructions may show larger voltage variations than the correct reconstruction. This assumption is valid for slow or small input signals, for which two consecutive samples are expected to have similar values. The limits of this assumption will be explored in Section IV.

The number of oscillations can be found as a result of the following optimization problem, subject to (20), (21), and (25):

$$\widehat{N_{S1}}\left[i\right]=\text{arg}\underset{N_{S1}\left[i\right]}{\text{min}}TSV\left({\upsilon }_{\text{in}1}\left[i\right]\right).$$ (26)

This optimization problem can be solved using Viterbi algorithm [29], [30]. Note that, in contrast to the previous reconstruction method, unknown slow deviations of the free-running oscillation frequency do not affect the validity of the reconstruction, since offset does not affect signal variation.

IV. Simulation Results

We have evaluated the performance of the proposed readout technique by designing and simulating a VCO-ADC for neural interfaces. Table I summarizes the main parameters of the simulated system.

Table I. System Parameters Used in Simulations.

Circuit	Parameter	Value used
vco	ffr	2 MHz
	KVCO	20 MHz/V
Multiplexer	ϕS1,T	12.2 μs
	ϕS1,W	610 ns
Timestamper	fclk	50 MHz / 200 MHz

We have considered the case of 20 VCOs multiplexed to a single timestamper, meaning that the timestamper can only observe each VCO during 5% of the time. The period of ϕ_S1 (ϕ_S1,T) defines the average sampling frequency of the system. We set the average sampling frequency well above the band of interest (a few kHz for neural signals), in order to limit input signal variations between samples, which facilitates signal reconstruction. With ϕ_S1,T = 12.2 μs, the average sampling frequency is approximately 82 kHz. The pulse width has been set to ϕ_S1,W = ϕ_S1,T/20 = 610 ns, so that the same timestamper can monitor 20 VCOs.

The free-running oscillation frequency is chosen in a way that the oscillation period is always shorter than the ϕ_S1 pulse width, to make sure that there is at least one rising edge (and therefore at least one timestamp) in every ϕ_S1 window. The sensitivity of the VCO has been chosen to be realistic for a specific VCO topology, as will be shown in Section V-B.

We have first evaluated the accuracy of multiplexed timestamping. The behavioral model of the VCO-ADC described above has been simulated for a sinusoidal input of 100 μV_p at 1 kHz, generating the complete sequence of rising edges (t_r[i]). To demonstrate the influence of f_clk in the accuracy of the system, we have generated two sequences of selected timestamps (m_S1[i]) with different clock frequencies, f_clk = 50 MHz and f_clk = 200 MHz. Selected timestamps have been combined with (15), (21), and (23) to estimate the input signal $\left(\widehat{{\upsilon }_{\text{in}1}}\left[i\right]\right)$. Fig. 6 shows the spectra of the simulated reconstructed signals, obtained after interpolating and resampling $\widehat{{\upsilon }_{\text{in}1}}\left[i\right]$ at 200 kHz. Interpolation and resampling were employed to achieve uniform sampling and facilitate the estimation of the power spectra, since the input signal is non-uniformly sampled at its origin (see (7)). The input-referred noise, integrated in the 300 Hz–5 kHz band, is 3.1 μV_rms for f_clk = 50 MHz, and 0.96 μV_rms for f_clk = 200 MHz. As expected, quantization noise is inversely proportional to f_clk, since higher clock frequencies result in more accurate timestamps. Nevertheless, even for f_clk = 50 MHz, the in-band noise is low enough for action potential detection.

Fig. 6.

Simulated spectra of the system described in Table I for an input signal of 100 μV_p at 1 kHz.

After simulating the accuracy of the timestamper, we have evaluated the performance of the reconstruction algorithms described in Section III. We have simulated the system described in Table I for a collection of 15 000 input signals, with different combinations of amplitude and frequency, ranging from 10 μV_p to 10 mV_p and from 100 Hz to 10 kHz (uniformly distributed at logarithmic scale). White noise (100 nV/√Hz) was added to all input signals to model circuit noise. For each simulation of 50 ms, we have computed the selected timestamps (m_S1[i]) and the ground truth number of oscillations (N_S1[i]). We have then used the approaches, described in (23) and (26), to estimate the number of oscillations $\left(\widehat{N_{S1}}\left[i\right]\right)$. A reconstruction has been considered valid when sequences $\widehat{N_{S1}}\left[i\right]$ and N_S1[i] were identical for the entire duration of each simulation.

Fig. 7 shows a summary of the four sets of simulations, combining the two reconstruction algorithms and the two different clock frequencies. The first approach, described by (23), results in valid reconstructions for input signals smaller than approximately 2 mV_p, as expected from (24). The performance of the minimization of signal variation described in (26) depends on the resolution of the timestamper. For f_clk = 200 MHz, this algorithm is consistently able to reconstruct large slow signals and small fast signals, and fails to reconstruct large fast signals. This is expected, since large fast signals feature higher signal variation, and there may be incorrect reconstructions with lower TSV than the correct reconstruction. For f_clk = 50 MHz, the reconstruction performance follows a similar trend, but reconstruction is less consistent and fails more frequently. This may be due to the lower accuracy of the timestamper, which increases quantization noise and, therefore, signal variation.

Fig. 7.

Simulated performance of the two signal reconstruction algorithms described in Section III: signal amplitude minimization as described in (23), and signal variation minimization as in (26). Each rectangle represents the percentage of correct reconstructions in 25 simulations. Each simulation lasted for 50 ms, and the input signal was the combination of white noise (100 nV/√Hz) and a sinusoidal signal of varying amplitude and frequency.

Based on these simulation results, both reconstruction algorithms appear to be suitable for most extracellular neural signals reconstructions, provided that extracellular action potential amplitudes are typically below 1 mVpp, and signal power is mainly contained in the 300 Hz–5 kHz band. Input amplitude minimization is more robust against high-frequency noise, while input signal variation minimization responds better to large low-frequency signal fluctuations. Nevertheless, these methods still have limitations, and further algorithms need to be developed to achieve more robust signal reconstructions. For example, large abrupt voltage variations —which can be produced during neural stimulation—are likely to be missed by the proposed reconstruction approaches. Changes in system parameters, such as a different oscillation frequencies or multiplexing schemes, may be required to accommodate specific needs of different applications.

V. Experimental Validation

A prototype of the system described in the previous sections has been fabricated in 0.18-μm CMOS technology. This section describes the circuit implementation and the results of the electrical characterization.

A. Prototype Description

The main requirements for neural interfaces and microelectrode arrays include sensitivity and low noise (to detect small action potentials), and low real estate and power consumption (to integrate thousands of units in the same substrate) [31]. Therefore, ring oscillators are a good choice due to their simplicity, compact size, and relatively low phase noise. Moreover, although ring oscillators normally feature a nonlinear voltage-to-frequency conversion, distortion is not problematic due to the small amplitude of input signals.

Fig. 8(a) shows the schematic of our voltage-to-frequency converter. The input signal ν_in is first filtered by a passive RC high-pass filter (HPF), based on a 350-fF metal-insulator-metal (MIM) capacitor (C₁) and a pseudoresistor (M₁). The cut-off frequency of this filter is set at approximately 0.1 Hz in order to block low-frequency fluctuations and to minimize the noise contribution of the pseudoresistor in the band of interest. The high-pass filtered voltage drives the gate of a P-type transistor (M₁) which, in combination with a cascode (M₂), acts as a transconductor [32]. The resulting current (i_CCO) modulates the frequency of a current-controlled oscillator (CCO). As shown in Fig. 8(b), the CCO consists of three CMOS inverters, with three 60-fF MIM capacitors (C_2-4) used as load to achieve a lower oscillation frequency. Since the amplitude of the oscillation at ν_osc is approximately 700 mV_pp, a level-shifter (M_4-5) and a digital buffer is used to obtain a square rail-to-rail oscillation at output w. The size of the relevant transistors is summarized in Table II.

Fig. 8.

(a) Schematic of the voltage-to-frequency converter. (b) Schematic of the CCO.

Table II. VCO Transistor Size.

Transistor	W(μm)/L(μm)	Transistor	W(μm)/L(μm)
M1	1/0.4	M4	1/0.2
M2	30/1.2	M5	1/0.2
M3	10/1.2	M6-11	0.8/3

The timestamper is implemented following the structure described in Fig. 3(b), with an 8-bit Gray counter acting as TRG, driven at f_clk = 50 MHz by an external clock. Gray-code has been chosen to avoid potential problems caused by sampling a wrong code during a transition, right after a clock edge. The counter was oversized to prevent overflows at very low oscillation frequencies or very high clock frequencies. The number of bits could be further optimized, based on the maximum number of clock cycles expected between two consecutive sampled VCO rising edges.

Fig. 9 shows the micrograph of the prototype, in which the areas containing the relevant building blocks have been highlighted. The estimated real estate and the simulated power consumption of each block are summarized in Table III. The total area and power of our circuits amount to 5550 μm² and 40.05 μW. However, since the timestamper can be shared among several VCOs, the effective area and power per channel depends on the number of multiplexed channels. For example, if we consider 20 VCOs sharing the same timestamper (as simulated in Section IV), area and power consumption per channel would be 1330 μm²/channel and 4.4 μW/channel.

Fig. 9. Micrograph of the prototype fabricated in 0.18 μm CMOS technology, with the location of three relevant circuits highlighted.

Table III. Summary of Area and Power Consumption.

Block	Circuit	Area (μm2)	Power (μW)
VCO	Transconductor	630	1.2
	CCO + LS	480	1.32
	Total	1110	2.52
Timestamper	Register	840	1.53
	TRG	3600	36
	Total	4440	37.53

B. Measurement Results

The transconductor was programmed to generate approximately 1 μA, with a transconductance of 20 μA/V. The resulting measured free-running oscillation frequency (f_fr) was 1.95 MHz with a sensitivity (K_VCO) of 22.0 MHz/V.

Fig. 10 shows the spectra of the recorded signals for a 100-μV_p signal applied at 1 kHz. The black spectrum is the result of continuous timestamping, where a complete sequence of timestamps was collected, and the input signal $\widehat{{\upsilon }_{\text{in}}}\left[i\right]$ was calculated combining (8) and (12). The noise in the band of interest (300 Hz–5 kHz) was 4.5 μV_rms, mainly limited by VCO phase noise. The blue spectrum shows the result of multiplexed timestamping, where timestamps were selected according to the multiplexing scheme used in Section IV (see Table I), and signal reconstruction was performed using the methods explained in Section III. Both reconstruction algorithms provided identical results. The noise in the band of interest (300 Hz–5 kHz) was 5.7 μV_rms. The contribution of quantization noise due to multiplexing is visible at high frequencies.

Fig. 10. Spectra of the recorded signals for a sinusoidal input of 100 μV_p at 1kHz.

As mentioned in Section IV, power spectral estimations were preceded by interpolation and resampling at high frequencies to achieve uniform sampling, since the timestamping process results in non-uniform sampling (see (7)). The resampling frequencies (20 MHz for continuous timestamping and 200 kHz for multiplexed timestamping) were chosen well above the average sampling frequency for each case (1.95 MHz for continuous timestamping, and 82 kHz for multiplexed timestamping). Note that interpolation and resampling were performed off-chip and only to facilitate spectral estimations, but none of these processes is required for normal operation of the system.

The system has also been tested with a pre-recorded neuronal signal. Fig. 11(a) shows the snippet of a signal captured using the CMOS microelectrode array described in [7], from an in-vitro culture of rat primary cortical neurons on day in vitro (DIV) 23. Fig. 11(b) shows the snippet of the reconstructed signal after injecting the pre-recorded signal at the input of the system, capturing timestamps and using (23) and (25) for reconstruction (both algorithms could be used to successfully reconstruct the signal). Note, that the prototype could digitize the signal successfully, and all significant APs (marked with red triangles, larger than five times the standard deviation of the recording noise) are visible in the reconstructed signal.

Fig. 11.

(a) Snippet of a pre-recorded neural signal captured with the HD-MEA described in [7] in an in-vitro culture of rat primary cortical neurons. (b) Snippet of the reconstructed signal. Red triangles mark significant action potentials with amplitudes larger than five times the standard deviation of the signal. Both signals have been band-pass filtered (300 Hz–5 kHz) before plotting.

VI. Conclusion and Outlook

In this manuscript we have presented a novel readout architecture for neural interfaces. As in other VCO-based systems, VCOs are used to transform analog input signals into digital oscillations that can be post-processed using digital circuitry. Here, we proposed the generation of timestamps, which contain information about when a VCO has completed one oscillation. This information is enough to reconstruct the oscillation frequency and the input signal off chip. The main advantage of the proposed architecture is that on-chip analog circuitry is minimized, since most of the circuitry required for VCO-timestamping is digital. Furthermore, the proposed architecture is easily scalable to a large number of channels, since the digital timestamper can be multiplexed among several VCOs.

The oscillation frequency of each VCO can be easily calculated when all the timestamps are collected. However, when multiplexing the timestamper, a significant number of timestamps is missed. In this case, signal reconstruction algorithms are required to infer the correct oscillation frequency. In this work, we have proposed two different approaches, both of them based on simple assumptions about the oscillation frequency and the amplitude and bandwidth of the input signal. Both algorithms have been simulated, and have been proven to be feasible solutions for the system evaluated in this manuscript. Nevertheless, other algorithms may be more efficient or robust, or may allow to relax the constraints of the VCO. The use of existing algorithms, developed for other fields that address comparable problems (such as module-ADCs [37] or compressed sensing [38], [39]), could be explored.

A single-channel prototype has been fabricated in 0.18-μm CMOS technology. The readout circuit featured 5.7 μV_rms of input referred noise in the 300 Hz–5 kHz band and could capture pre-recorded neuronal action potentials. The area and power consumption of the single-channel prototype was 5’550 μm² and 40.05 μW. The performance of a multi-channel neural interface, implemented using the proposed time-domain readout technique, would strongly depend on parameters not yet explored with this prototype. Multiplexing several VCOs per timestamper would significantly reduce the effective area and power per channel, since, as shown in Table III, the timestamper is the main contributor to area and power consumption. To illustrate the potential of the proposed architecture, we have estimated the performance of a hypothetical 20-channel system combining 20 VCOs and one timestamper. This estimation does not consider two factors: multiplexing circuitry and timestamper optimization. On the one hand, multiplexing would require additional circuitry (mainly switches) that may increase area and power consumption. On the other hand, the timestamper could be further optimized, e.g., by reducing the number of bits, to decrease area and power consumption.

Table IV presents a comparison between state-of-the-art neural readout circuits and the estimated performance of the hypothetical 20-channel system. The proposed system features very low real estate while achieving low power consumption. However, input-referred noise is comparatively high, and very small action potentials (on the order of 10–20 μV) may not be distinguishable from noise. Nevertheless, as shown in Section V-B, noise is low enough to capture larger extracellular action potentials.

Table IV. Performance Summary of a 20-Channel System and Comparison With State of the Art.

	[7]	[33]	[34]	[10]	[35]	[36]	[32]	Proposed system
Year	2017	2018	2018	2020	2021	2021	2021	2023
Architecture	SAR	ATC	Δ-ΔΣ	SS	IΔΣ	SAR	VCO-Q	VCO-TS
Technology (nm)	180	65	180	90/65	180	180	180	180
Sampling frequency (Hz)	20 k	_d	25 k	70 k	20 k	11.6 k	1 M	82 k e
Bandwidth (Hz)	300 – 10 k	11 k	0.5 – 12.7 k	300 – 10 k	300 – 10 k	300 – 5 k	300 – 6 k	300 – 5 k
Area/channel (mm2/ch)	0.024a	0.006	0.058c	0.014a	0.0046c	0.001a	0.0045b	0.0013 b,f
Power/channel (μW/ch)	16	1.2	3.05	130	8.59c	5.9	3.5b	4.4 b,f
Input-referred noise (μVrms)	2.4	3.8	3.32	5.5	4.37	10.4	5.0	5.7 f

ATC: Analog-to-Time Converter; SS: Single-slope; IAX: Incremental AX; VCO-Q: VCO-based quantizer. VCO-TS: VCO-timestamping.

^aEstimated.

^bExcluding biasing.

^cIncluding on-chip digital filter.

^dAsynchronous output.

^eAverage frequency (non-uniformly sampled).

^fAssuming 20:1 multiplexing.

One potential drawback of the proposed system is the relatively high data rate required to transmit all the timestamps off chip. Assuming an average sampling rate of 82 kSps and each timestamp being 8 bits long, the average data rate is 656 kbps per channel. However, the number of bits in the timestamper could be further optimized, and the sampling rate could be reduced at the cost of making the reconstruction process more challenging. It is worth noting that the proposed technique would benefit from CMOS-technology scaling, as most building blocks are digital circuits that would be more efficient in deep submicron technologies.

The proposed approach may be also suitable for cameras and other sensor arrays in which 1) several channels need to be monitored simultaneously, 2) a-priori knowledge about the input signal is available, and 3) advanced digital signal processing is possible.

Biographies

Fernando Cardes (Member, IEEE) received the B.S. degree in industrial electronics and automation engineering, the M.S. degree in advanced electronic systems, and the Ph.D. degree in electrical engineering, electronics and automation from Universidad Carlos III de Madrid, Madrid, Spain, in 2012, 2014, and 2018 respectively. He is currently a Postdoctoral Researcher with Bio Engineering Laboratory, ETH Zurich, Basel, Switzerland. His research interests include mixed-signal microelectronics, bioelectronics, and neural interfaces.

Ebrahim Azizi received the B.S. degree in physics with the Vali-e-Asr University of Rafsanjan, Rafsanjan, Iran, in 2011, and the M.S. degree in condensed matter physics from the University of Isfahan, Isfahan, Iran, in 2013. He is currently working toward the second M.S. degree in telecommunications engineering, signal and data analysis with the Polytechnic University of Milan, Milan, Italy. During 2021–2022, he was a Visiting Research Scholar with ETH Zurich, Zürich, Switzerland. His research interests include statistical signal processing, inverse problem in neuroimages, and unsupervised generative models in neuroscience.

Andreas Hierlemann (Member, IEEE) received the Ph.D. degree in chemistry with the University of Tübingen, Tübingen, Germany, in 1996. He then held Postdoctoral positions with Texas A&M University, College Station, TX, USA, in 1997, and Sandia National Laboratories, Albuquerque, NM, USA, in 1998. In 1999, he joined the Department of Physics, ETH Zurich, Zürich, Switzerland, where he was appointed Associate Professor in June 2004. In April 2008, he became a Full Professor with the Department of Biosystems Science and Engineering, ETH Zurich, Basel, Switzerland. His research interests include the development and application of microsensor, microfluidic, and microelectronic technologies to address questions in biology and medicine with applications in the fields of systems biology, drug testing, personalized medicine, and neuroscience. For details, see https://www.bsse.ethz.ch/bel/.