An Energy Efficient and Temperature Stable Digital FLL-based Wakeup Timer with Time-Domain Temperature Compensation

Abstract

This brief presents an on-chip digital intensive frequency-locked loop (DFLL)-based wakeup timer with a time-domain temperature compensation featuring a embedded temperature sensor. The proposed compensation exploits the deterministic temperature characteristics of two complementary resistors to stabilize the timer’s operating frequency across the temperature by modulating the activation time window of the two resistors. As a result, it achieves a fine trimming step (± 1 ppm), allowing a small frequency error after trimming (<± 20 ppm). By reusing the DFLL structure, instead of employing a dedicated sensor, the temperature sensing operates in the background with negligible power (2 %) and hardware overhead (< 1 %). The chip is fabricated in 40 nm CMOS, resulting in 0.9 pJ/cycle energy efficiency while achieving 8 ppm/ºC from -40ºC to 80ºC.

I. Introduction

DUTY-CYCLED radios have been widely adopted in various Internet-of-Things (IoT) applications where data is transferred at a relatively low rate, such that battery lifetime can be maximized. For a typical Bluetooth Low Energy (BLE) radio supplied by a coin-cell battery (e.g., 3 V 250 mAh CR2032), a less than 0.1 % (i.e., ±500 ppm) duty-cycling is required for a 10-year battery life. To minimize the power consumption of the radio system, an accurate wakeup timer (≤ ±500 ppm) is essential. The accuracy of the timer determines the guard time which is additional time required to keep the system active beyond the actual data communication period, so that the radio does not miss the communication event.

Additionally, since the timer needs to be constantly operational, it is crucial to ensure its power consumption is low (sub-µW). Crystal and MEMS based timers [1] can meet these requirements, but they are bulky and costly, as they are based on external components. Since long-term time accuracy is the primary concern for the timer, as opposed to short-term time accuracy, fully integrated RC-based timers [2]–[10] are a good alternative due to their low power consumption. Relaxation-oscillator timers [2] suffer from poor energy efficiency and frequency stability due to a continuous comparator. Although the uncertainty of the comparator delay can be excluded by a delay locked loop [3], its power consumption is non-negligible.

Frequency-Locked-Loop (FLL) based timers [4]–[10] circumvent this issue, but their temperature coefficients (TCs) are still limited (10’s ppm/ºC), which is typically restricted by resistor’s higher-order temperature coefficient (TC) [4]–[5]. Sub-10 ppm/ºC TC were achieved in [6]–[9], but with poor efficiency [5]–[7], small temperature range [8] or requires special temperature-compensated resistors [9].

To improve TC while still maintaining good energy efficiency, this work presents a low TC Digitally intensive Frequency-Locked-Loop (DFLL) based wakeup timer [10] with 0.9 pJ/cycle efficiency by employing two key techniques. First, a deterministic time-domain temperature compensation with complementary resistors achieves a near-zero TC (1.7 ppm/ºC with an external Temperature Sensor (TS)). Second, an embedded TS that reuses the DFLL circuitry acquires accurate temperature information from DFLL’s internal signals. This design improves both the trimming step and TC (8 ppm/ºC) while still maintaining excellent energy-efficiency compared to the state-of-the-art on-chip timers.

The rest of this brief is organized as follows. The proposed DFLL architecture is presented in section II. Section III details the analysis of proposed temperature calibration. Measurement results are described in section IV.

II. Proposed Time-Domain Temperature Compensation

A typical FLL-based timer [5] is shown in Fig. 1. The RC-based frequency detector output (V_FD) is charged during the half cycle of Φ₂, which is the clock divided the output clock (f_OSC) by 2N, and thus denotes the frequency difference between f_OSC and the target frequency, N/(4•R_refC_ref•ln2) [5]. With a proper amplification, it is then integrated by the loop filter and the oscillator is controlled toward V_FD = 0, i.e., frequency locked (Detailed timing diagram is shown in Fig. 4.).

Fig. 1. FLL-based timer with direct complementary resistor trimming.

Fig. 4. Timing diagram depicting operation of the proposed timer.

However, the frequency stability of the FLL-based timer is still limited by the frequency detector, especially the temperature dependency on its analog elements, e. g., resistors and capacitors, which impacts the timer’s TC. By using temperature-insensitive capacitors such as metal-oxide-metal (MOM) capacitors, the TC of capacitor is negligible, making the trimming for the resistor’s TC the primary focus.

The resistor’s TC can be directly calibrated by using complementary resistors that have opposite TCs [5], [11] as

$$R_{ref}=\alpha R_N+(1-\alpha )R_P$$ (1)

where R_N and R_P represent the resistance with negative and positive TCs, respectively, and α is the ratio between the R_N and the total resistance (R_N + R_P). α is tuned to minimize the TC of R at a single temperature (1-point) or multiple temperature points (N-points) with multiple configurations to reduce the TC.

Analog resistor trimming based on switched resistor array [5] can simply tune α and its resolution can be increased by reducing the unit resistor. However, its resolution is limited by the switch’s ON-resistance and leakage [12]. The TC in [12] remains at 31 ppm/ºC after 10-point trimming.

To minimize the switch’s non-ideality in the analog resistor trimming, pulse density modulated resistor was proposed in [11], [13]. Its resolution is no longer limited by the switch, and the TC can be reduced to 8.4 ppm/ºC.

The direct complementary resistor trimming shifts the flat region of TC to cover different temperature range but inevitably also shifts the absolute frequency due to the difference in TC between R_N and R_P [12]. It necessitates additional trimming of capacitor (C_REF) to compensate the frequency drift, but it is limited by the step size of C_REF.

Alternatively, the resistor’s temperature dependency compensation techniques [6], [7] can also calibrate the TC. Based on the resistor’s temperature profile across the temperature variation, it can provide better TC over the resistor trimming. Dual RC temperature compensation [6] can achieve low TC (2.5 ppm/ºC) by extracting two complementary resistor’s temperature profile and linearizing by polynomials. However, it requires dual circuitry that increases significant power and area overhead. Digital linear temperature compensation [7] can mitigate the hardware overhead by replacing one of RC branches with a temperature sensor and a high-order polynomial. However, it is still power hungry (142 μW) and requires dedicated temperature sensor.

To achieve low TC while maximizing the hardware efficiency, we propose a time domain temperature compensation as illustrated in Fig. 2. The proposed compensation employs two resistors (R_refp and R_refn) with complementary TCs and toggles between the two resistors during operation, resulting in two transient frequencies, f_OSC,Rrefp and f_OSC,Rrefn, and an averaged frequency of them over the averaging time (T_win) is f_OSC,avg, as

$$f_{OSC,avg}=\beta f_{OSC,Rrefp}+(1-\beta )f_{OSC,Rrefn}$$ (2)

where β is the ratio between the duration of f_refp and T_win (T_Rrefp/T_win). For each temperature sensed by temperature sensor, thanks to deterministic complementary frequency shift of R_refn and R_refp, β, i. e., toggling duty-cycle, can be set to assure a constant f_OSC,avg across the temperature. In this way, the complementary TCs of R_refp and R_refn are cancelled with each other over T_win, resulting in a near-zero TC.

Fig. 2. DFLL-based timer with proposed time-domain temperature compensation.

The proposed temperature compensation effectively calibrates both TC and the operating frequency at each temperature, thus requiring no additional frequency calibration for the frequency drift, as required in conventional complementary direct resistor trimming.

III. Wakeup Timer with Embedded Temperature Sensing

To support the proposed time domain temperature compensation, a DFLL-based wakeup timer with an embedded temperature sensor (TS) is proposed as illustrated in Fig. 3.

Fig. 3. Block diagram of the proposed timer and the embedded temperature sensor.

Compared to the analog FLL counterpart, the DFLL-based timer offers advantages in terms of area and energy efficiency [5]. To reduce the dynamic power consumption at the expense of settling time (~70 ms) [5], the output frequency f_OSC is divided by 32 and locked to a reference frequency, defined by R_ref (equivalent resistance by the trimming with R_refp and R_refn) and C_ref, as discussed in Sec. II. Since the timer is in always on domain, 70 ms settling time is usually unproblematic. f_OSC is then set to 32/(8•R_refC_ref•ln2) ≈ 428kHz with R_ref of 6MΩ and C_ref of 4pF. A dynamic comparator [5] is employed to quantize the sampled frequency difference (V_FD) for a bang-bang operation. Chopping technique is adopted to reduce the comparator offset which induces the fraction of the timer’s frequency offset. A digital loop filter accumulates the 1-bit quantized frequency difference and provides an Oscillator Tuning Word (OTW) to set the frequency of a Digitally Controlled Oscillator (DCO).

To relax the design complexity of DCO while keeping the Allen deviation floor low, a Sigma Delta Modulator (SDM) clocked at f_OSC/2 (16× oversampling ratio), is employed to further improve the DCO resolution from 2 kHz to below 250 Hz. A multi-phase divider generates non-overlapping multi-phase clocks (φ₁, φ₂, φ₃, φ₄ and φ₅) that run at f_OSC/32. As shown in Fig. 4, φ₁, φ₂ and φ₃ discharges, holds and samples the RC network of the frequency detector, respectively. φ₄ and φ₅ operate the comparator and digital circuitry.

During operation shown in Fig. 4, DFLL is firstly locked to a frequency f_OSC,Rrefp by connecting to R_refp (S_CAL=1), and then locked to another frequency f_OSC,Rrefn by connecting to R_refn (S_CAL=0). R_refp and R_refn are P-poly and N-poly type, respectively, having complementary TC (-85ppm/ºC and 150ppm/ºC, respectively) and give opposite frequency shifts with respect to temperature. As long as the temperature characteristic of R_refp and R_refn is deterministic, β can be well-estimated beforehand and stored in a Look-Up-Table (LUT). β is quantized to two pulse width modulating digits (N_PWM) CALP and CALN, defining the duty-cycle of S_CAL through a Pulse-Width-Modulation (PWM). In this way, the duty-cycle of S_CAL counteracts the opposite frequency shift of R_refp and R_refn with temperature, giving a constant averaged frequency of f_OSC, i.e., f_OSC,avg. As shown in Fig. 4(b), the PWM toggles between f_OSC,Rrefp and f_OSC,Rrefn, thus finally reaching the target frequency.

The step size of the proposed temperature compensation is improved in two ways: first, the frequency error is corrected over a longer time (T_win) rather than to a single period of f_OSC (T_OSC; 1/f_OSC). Second, thanks to the dual resistor (dual-R) operation, the trimming step is based on a relative value (T_φ5p-T_φ5n) instead of an absolute value (T_φ5), where T_φ5p and T_φ5n are the period of φ₅ with R_refp and R_refn, respectively. Thus, the trimming step is significantly improved to (T_φ5p-T_φ5n)/T_win. Thanks to the digital nature in time domain, the trimming step is no longer limited by the switched-array in the analog approach. Higher N_PWM gives a finer trimming step through PWM but requires longer T_win, i.e., T_win >>1/f_osc as shown in Fig. 5 (a). For example, 13-bit N_PWM with 1s T_win gives a ± 1 ppm trimming step, which is feasible for most IoT applications. Fig. 5(b) shows Monte Carlo simulation result of the frequency deviation over the temperature range (-40°C to 80°C) and different process conditions, after the proposed temperature compensation. The simulation result shows a small frequency deviation (~ ±12.4 ppm), with 3-sigma of 9.3 ppm.

Fig. 5.

(a) Simulation results of trimming step and minimum T_win with different N_PWM. and (b) Monte Carlo simulation (global + local) result of frequency deviation over the temperature range (-40°C to 80°C) after the proposed temperature compensation.

The proposed compensation requires a temperature sensor (TS) to choose CALP and CALN from LUT as shown in Fig. 3. However, the overhead in power and area incurred by recent TS designs [6] remains unaffordable for a nW timer. This work reuses the DFLL circuitry and performs as a resistor-based TS similar to [6]. Unlike [6] which still need to measure the oscillator output frequency using an equipment or a reference clock, a digital code that represents temperature can be directly readout from the internal signals of DFLL, which works as shown in Fig. 6 (a): f_osc equals to OTW·K_DCO, where K_DCO is the DCO frequency step. Since K_DCO is sensitive to temperature variations, OTW cannot be directly used for temperature sensing. Thanks to the dual-R operation, this issue is overcome by reading out OTW in both modes, such that the temperature sensitivity of K_DCO is cancelled as

$$\frac{f_{OSC,Rrefp}(T)}{f_{OSC,Rrefn}(T)}=\frac{R_{Rrefn}(T)}{R_{Rrefp}(T)}=\frac{OT{W}_P}{OT{W}_N}$$ (3)

Fig. 6.

(a) Procedure of time domain trimming with proposed embedded temperature sensing and (b) measurement result of OTW_P/OTW_N.

OTW_P/OTW_N only reflects the deterministic temperature dependency of R_refn/R_refp. Fig. 6 (b) shows the measurement result of OTW_P/OTW_N.

Note that reading out OTW_P and OTW_N is performed in the background to track the environmental temperature variations and does not interfere with the timer’s normal operation, as shown in Fig. 4.

As shown in Fig. 3, the signal processing and the β LUT is off-chip in this work to have some flexibility by implementing the logic off-chip since this is a prototype. It would be recommended to integrated them on chip in the future, to reduce the quiescent power overhead.

IV. Measurement Results

The timer is implemented in 40nm CMOS, occupying 0.07mm² as shown in Fig. 7(a). The chip consumes 380 nA at 1 V, where PWM consumes only 2 % (Fig. 7(b)).

Fig. 7.

(a) Chip micrograph and (b) power breakdown.

The resistor is initially trimmed out at a certain temperature (one-time calibration). Then, the frequency errors over the target temperature range (-40°C to 80°C) with R_refp and R_refn are measured to define the β profile. Fig. 8 (a) shows the measurement results of the deterministic temperature dependency of R_refp and R_refn. The chip is measured from -40 °C to 80 °C and the coefficient β and LUT are built with a 10 °C step. The frequency error after the temperature compensation with β profile is within ± 480 ppm from the target (428 kHz) (TC is 8 ppm/ºC). Fig. 8(b) shows the accuracy of the PWM. the measured averaged f_OSC (f_OSC,avg) can be set within the frequency error of ± 20 ppm at temperature points where the β generated. Fig. 8(b) also shows the result from a reference design using a 10-bit capacitor bank with a 1.5 fF unit for frequency trimming, where the frequency error after capacitor trimming is up to ± 1000 ppm.

Fig. 8.

(a) Effect of proposed time domain temperature compensation and (b) accuracy of the proposed compensation versus analog trimming with a 10-bit capacitor bank.

For each 10 °C, one predefined coefficient β (13 trimming points) is applied, the measured frequency error across 10 °C is shown in Fig. 9. The frequency variations in the flat region of TC curve are small (< 400ppm) within 10ºC, but the frequency changes exponentially outside the flat region (< 2000 ppm), which needs to be tackled by more β.

Fig. 9.

(a) local frequency error near the trimming points and (b) TC versus number of coefficients from LUT.

Fig. 9(b) shows the measured TCs versus number of configurations (β). With 1 configuration from the LUT, TC is 35ppm/ºC, and it can be improved to 8 ppm/ºC with 8 coefficients, which is limited by the TS performance. Assuming using an external TS with accurate sensing result with less than 2°C error, TC can reach 1.7 ppm/°C.

The measured Allan deviation floor shown in Fig. 10(a) is less than 10 ppm for a T_win of 100s. It is observed that the Allan deviation gets poorer with shorter gating interval, possibly due to the low frequency toggling for the temperature compensation. Fig. 10(b) shows the measured β profile.

Fig. 10.

(a) Measurement result of Allan deviation and (b) measured β profile.

The embedded TS achieves 1.6 µs accumulated jitter in a 200-ms window, corresponding to a 0.063K temperature resolution.

Chip-to-chip variations are shown in Fig. 11, The systematic higher-order nonlinearity of f_Rrefp and f_Rrefn are extracted after an individual 1^st-order fit and is consistent among 3 chips. After removing this systematic nonlinearity (7^th order), the remaining frequency error is ± 300 ppm, limited by the process spread. The proposed temperature readout (OTW_P/OTW_N) has a chip-to-chip variation of 8 ºC after a 1^st-order fit following a systematic non-linearity removal as illustrated in Fig. 12(a). Fig. 12(b) shows the measured line sensitivity. Table I summarizes the performance and compares it with state of the art.

Fig. 11.

Measured timer’s performance: (a) frequency f_Rrefp and f_Rrefn after an individual 1^st order fit and (b) frequency f_Rrefp and f_Rrefn after a 1^st order fit followed a systematic removal (7^th order).

Fig. 12.

Measured chip-to-chip variation of (a) temperature error of TS and (b) line sensitivity.

Table I. Performance Summary and Comparison.

	This work	[5] TCAS-I’ 20	[4] ISSSC’ 23	[7] JSSC’ 22	[2] JSSC’ 16	[3] ISSCC’ 22
Architecture	Digital FLL		Analog FLL		Relaxation
	RC	R-RC
Process (nm)	40	130	180	65	65	0.07
Area (mm2)	0.07a	0.07	0.01	0.06	0.032	0.015
Power (nW)	380a	240	85000	142000	130	7600
Frequency (Hz)	428k	417k	10M	28M	18.5k	2.3M
TC (ppm/°C)	8/1.7b @ -40 ° C to 80 ° C	33 @ -20°C to 80°C	31.5 @ -45°C-125°C	2.56 @ -40°C to 85°C	46 @ -40°C to 90°C	7.93 @ -40°C to 125°C
Line sen. (%/V)	0.27	1.5	0.9	0.29	<5	0.51
Allan deviation (ppm)	10	12	2.3	2	20	9
	(<100s)	(<100s)	(<1s)	(<40s)	(<100s)	(>0.5s)
Energy eff. (pJ/cycle)	0.9c	0.57	8.5	5	7	3.3
Trim methods	Time-domain	Resistor	Resistor	Resistor	Not report	Resistor
Number of trimming points	8/13b	1	1+batch	2+batch	2	2
Number of samples	3	3	112	16	4	11
Embedded TS	Yes	No	No	No	No	No

^aPower and area of signal processing part are excluded.

^bUsing embedded TS/ Using external TS

^cIncluding power of the TS

V. Conclusion

This brief presented an energy-efficient wakeup timer featuring high temperature stability. Thanks to the proposed resolution limitations, which are reliant on the physical characteristics of analog elements, without significantly increasing hardware requirements. To support the trimming, the timer employs the temperature sensing by reusing the digitally intensive frequency-locking scheme, requiring no additional temperature sensor. Fabricated in 40nm CMOS technology with a 1-V supply, this work consumed an area of 0.07mm² and a power of 380nW, respectively. While consuming only 2% of total power for the time-domain trimming, it achieved TC of 8 ppm/ºC external temperature sensing, with state-of-the-art efficiency of 0.9pJ/cycle.