An Ultrasound-Powering TX with a Global Charge-Redistribution Adiabatic Drive Achieving 69% Power Reduction and 53° Maximum Beam Steering Angle for Implantable Applications

State-of-the-art intracortical neural recording and stimulation systems rely on subdural implants tethered to a cranial implant which itself has a wireless power and data link to the outside world [1] (Fig. 1). However, this tethered configuration poses challenges such as scarring and potential damage to the surrounding tissue due to strain and micromotions, making this approach unsuitable for chronical implants [7]. Consequently, there has been a growing interest in a wireless connection between cranial and subdural implants. This paper focuses on the crucial aspect of wireless powering between the implants, traversing the dura and cerebrospinal fluid (CSF) tissue layers over distances of 0.5-1cm (transdural powering). With modern burr-hole craniotomy, the hole drilled in the skull is ~6mm in diameter, limiting the available size for the TX. Moreover, the power dissipation of the TX must be low to keep tissue heating below 1°C [8]. RF and optical modalities suffer from higher attenuation in tissue compared to ultrasound (0.6dB/cm/MHz) [9]. Furthermore, for transdural powering the power losses from reflections at medium interfaces (e.g., skull) are avoided, making ultrasound (US) a prime candidate for efficient in-body wireless power transfer. Ultrasound is also preferable to inductive powering since US beam steering up to large angles (>45°) is needed to maximize power delivery and compensate for brain micromotions of up to ±4mm [10] and misalignment during surgery. However, prior art US driving systems either use single-phase transducer driving [2][3], incapable of beam steering, or use class D drivers with low power transfer efficiency (PTE) [4][5]. A phased array with increased driving efficiency was presented in [6], but it cannot perform beam steering without grating lobes that can be eliminated with miniature transducers with a pitch close to λ/2. To facilitate direct integration between CMOS and the transducer array, the CMOS driving units should also be pitch matched [4][5].

Figure 1. Simplified block diagram and concept illustration of the proposed transdural powering system.

Fig. 1 shows the chip architecture. A beam steering controller with 1.2V supply uses an external 250MHz clock to generate the time delays for the 16 driving units of a 16-element transducer array, implementing beam steering based on the equation in Fig.1. The delay between 2 adjacent elements (ΔT) sets the angle. For continuous powering, the delays of all elements can be contained within one ultrasound period (wrapped delays). While typically US powering uses <1MHz [6], this work uses ~8MHz such that the natural focus point of the mm-sized transducer array is close to the maximum powering distance. Furthermore, due to small attenuation for sub-cm distance and higher voltage-to-pressure sensitivity (kPa/V) of transducers at higher frequencies, PTE can be improved. However, the smaller pitch further complicates the design of power-efficient pitch-matched driving circuits. To achieve high driving efficiency, adiabatic driving with a “global charge redistribution” (GCR) concept is proposed. Unlike existing adiabatic driving, this method does not require external capacitors for the charge recycling, but instead leverages the parasitic capacitors of the full transducer array itself. Additionally, a GCR controller is proposed, that implements beam steering to large angles ensuring GCR. Fig. 2 shows the details of the GCR 16-unit 5-level adiabatic driving circuits implemented with switches S1-S5 that turn on and off sequentially and drive the transducers from VDD US (4.8V) supply. The GCR controller determines the operation of the switches and the delays of all units. The dominant source of power loss in US transducer driving is the energy stored in the equivalent parasitic capacitor Cp of each element. With adiabatic driving, a capacitive load can be charged via intermediate levels (V2, V3, V4). When the load is discharged, the charge Q_i can partially flow back into these levels to be reused in a later cycle, implementing charge recycling [2][6]. Theoretically 75% of the energy can be recycled with 5 level adiabatic driving. While adiabatic driving is well-known, it typically requires large capacitors (Cext in Fig. 2) on each intermediate voltage level, increasing the implant size beyond volume constraints. However, in theory in a phased array, if 1 element is charging to a specific level (V2, V3 or V4), and at the same time exactly 1 other element is discharging to the same voltage level, charge recycling directly between transducer elements can be achieved [2]. If this happens for all intermediate voltage levels and all elements (GCR condition), then no net charge flows into the intermediate nodes, eliminating the need for Cext and resulting in an area-efficient implementation. However, this has not yet been achieved, such that prior art still requires ~50nF of external capacitors [2]. This work proposes a special GCR beam steering scheme, achieving GCR condition for all non-zero angles and eliminating Cext (Fig.2).

Figure 2. Simplified schematic and concept illustration of the global charge redistribution adiabatic driver.

A fundamental condition for GCR to apply is that each voltage level (V2, V3, V4) is only connected to exactly one pair of a charging and a discharging element at each time. No elements in the array should have the same delay, otherwise they would be charging simultaneously to the same level. By setting the delay resolution to T_US/16 we ensure that for ΔT_min of 8ns, no delay repetition occurs. Furthermore, it is shown in Fig.2 right middle part that if a unit (e.g., V_US16) recycles its Cp at two consecutive intermediate voltage levels with 2 other units (V_US1 for level 2 and V_US2 for level 3), then the duration of these levels should be half of the delay τ between V_US1 and V_US2, i.e., τ/2. By setting τ equal to ΔT_min (8ns), GCR is achieved for the minimum angle. However, by applying a conventional linear beam steering pattern for larger angles, some delays are repeated and not all the elements share their Cp charge with exactly one other element at each intermediate voltage level (example Fig. 2 bottom), making charge redistribution partial and Cext necessary. This is solved with a “delay skipping” scheme, applicable for all ΔT, in which whenever the wrapped delay of a unit is about to be repeated in the 16-unit row, a “-τ” offset is introduced in the delay of this specific unit. It is shown for the example of ΔT= 4τ (Fig.2) and the necessary delay skips for all ΔT are mentioned in the table in Fig.2. It has also been validated that such delay skips do not affect the beam profile (Fig. 5).

Figure 5. Acoustic measurements with PMUT array for beam profiles at 0 and 53 degrees beam profiles with and without GCR.

For an 8MHz pitch matched transducer array the parasitic gate capacitance Cg of the high voltage driving switches is not negligible compared to the transducer Cp (few pF) and becomes a major source of circuit loss. As shown in [4], the switch driving circuits and the transducers have comparable power consumption. This is a bigger issue in adiabatic driving, because more power switches are needed. To overcome this issue, the proposed architecture not only minimizes Cg but also implements charge recycling between the parasitic gate capacitances of the switches. The implementation of the adiabatic driver unit is depicted in Fig.3. Switches S1-S3 are implemented with NMOS transistors and S4, S5 with PMOS to minimize the number of switch drivers and allow smaller switch V_gs. The control bits (D1-D5) from the GCR controller are level shifted and buffered to control the switches, drawing current from VDDH (4.8V). Both the power loss for charging and discharging Cg as well as the level shifter power loss are greatly reduced when limiting V_gs of the switches S1-S2 and S4-S5 to VDDH/2 (Fig.3). Thanks to the GCR, charge recycling between Cg will happen automatically via VDDH/2. If 1 unit has S2 closed, there will be exactly 1 other unit with switch S4 closed (units 3 & 1 at times t1 & t3). Similarly, charge recycling between switch S5 of every unit and an S1 of another unit will happen (t2). Thus, zero net current is drawn from VDDH/2 for the switch drivers. These circuit innovations result in a fully integrated 116μm×116μm driving unit that is the smallest US adiabatic driving unit and has the lowest power consumption among the state of the art.

Figure 3. Simplified schematic of adiabatic driving unit with power efficient and charge recycling switch drivers.

The chip was fabricated in 65nm CMOS, and the chip micrograph is shown in Fig. 7. 4 rows of 16 units are implemented, with the 4 units of each column having connected outputs, thus forming 16 TX channels for 1D beam steering. The presented TX is connected to a PMUT-array chip with a resonance frequency of ~7.8MHz, with each TX channel driving a row of 32 PMUT elements (60μ m width and 105μ m pitch each). Single channel measurements with PMUT array load (10pF load per channel in water) verify the adiabatic driving (Fig.4), while multichannel measurements verify the good delay linearity between channels. The measured power consumption demonstrates that the GCR adiabatic driver technique saves 69% of power from VDD US compared to class-D driving and 46% of power in total, including the power consumed by the adiabatic switch driver (VDDH) and the GCR controller (VDDL). The TX is also compatible with pitch-matched integration with a PZT transducer array for further miniaturization and increased pressure and PTE [5]. Acoustic measurements with the PMUT array in water (Fig.5) verify that beam steering at angles of up to 53degrees is achieved without grating lobes. Fig. 6 summarizes the performance and compares it with state-of-the-art US drivers and beam steering arrays. The presented TX array achieves the best dynamic power saving and the widest steering angle among beam steering arrays. The proposed GCR concept and charge recycling switch driver result in completely avoiding any capacitance or inductor [3] for the driver and having the lowest power consumption and smallest area per unit.

Figure 7. Chip micrograph, unit layout and ASIC to PMUT connection.

Figure 4. Measured single channel adiabatic output, multichannel outputs and power consumption of TX array.

Figure 6. Summary and comparison table of state-of-the-art ultrasound drivers and beam steering arrays.