DSP-based current source for electrical impedance tomography

Abstract

Objective:

EIT systems, particularly those that use a parallel, multiple source architecture, require current sources with very high output impedance. To meet this requirement, sources often use complex analog circuits and require manual or electronically-controlled adjustments. The goal is to implement a current source with simple, adjustment-free analog electronics with high effective output impedance even with significant stray impedance at its output.

Approach:

The excitation provided to the voltage-to-current converter is adjusted to accommodate the current lost in the finite output and stray impedances. The adaptive algorithm uses the measured voltage and the previously-measured output and stray impedance to determine the needed current adjustment.

Main results:

The structure of the source is presented along with an implementation, and experimental results that show the effectiveness of the approach for frequencies up to 1 MHz. The measured output impedance with and without the adaptive compensation are presented as well as measurements of resistive and complex loads.

Significance:

The new current source has low analog complexity, operates over a wide range of frequencies, and can compensate for a significant stray shunt impedance. It can be used to implement improved parallel or serial EIT systems.

1. Introduction

Many applications such as electrical impedance tomography (EIT) require high-precision current sources that can deliver a desired current to an unknown load impedance. The current sources often are in the form of a voltage to current (V-I) converter that takes a voltage at its input and produces a proportional current at its output. These current sources often have to operate over a relatively broad frequency range, i.e. the applied current can have a frequency that varies over a broad range. To achieve high precision, the current sources must have a very high output impedance such that the current delivered to the load is nearly independent of the voltage that appears on that load. The need for high output impedance is particularly acute in multiple source EIT systems where currents applied by multiple sources must sum to zero. The shunt stray capacitance to ground due to wiring and cables also appears in parallel with the current source output impedance, lowering its effective value. There are many circuits that are used to implement current sources that can provide very high output impedance, e.g. Wang et al (2012), Han et al (2017), Khalighi and Mikaeili (2018), Ross et al (2003), Cook et al (1994), Tucker et al (2013), Rao et al (2018), Bragos et al (1994), Seoane et al (2008), Rao et al (2019). Many current sources operate best at low frequencies and require precise component values and/or use of manual or automatic tuning of one or more circuit components. As the operating frequency increases, the capacitive portion of the output impedance presents a lower impedance value and the performance of the current source degrades.

To maintain high precision, i.e. a high output impedance at higher frequencies, several methods can be used to cancel out the output capacitance. One approach uses a negative impedance converter (NIC) circuit to place an adjustable negative capacitance in parallel with the output of the current source which, when tuned to produce a capacitance of equal magnitude but opposite sign, cancels out the output capacitance of the current source (Cook et al 1994, Bertemes-Filho et al 2003). Ideally, one adjustment of the NIC should cancel the output capacitance over a broad frequency range. However, frequency dependence of the current source output capacitance and the negative capacitance produced by the NIC circuit results in the need to re-adjust the NIC for different frequencies. Additionally, the NIC circuit is notorious for stability issues, i.e. producing undesirable oscillations. Another approach uses a generalized impedance converter (GIC) circuit in parallel with the output of the current source to produce an adjustable inductance (Ross et al 2003, Oh et al 2007, Wi et al 2014). This inductance is adjusted to produce a parallel resonant circuit with the current source output capacitance at the frequency of operation. This parallel LC resonant circuit will ideally present an infinite impedance at its resonant frequency, effectively cancelling the effect of the capacitance in the current source output impedance. A drawback of the GIC approach is the time constant associated with the resonant circuit which can produce lengthy transients if the applied current amplitude is changed.

Wang et al (2012) describes a comprehensive study on wide-band V-I converters. They simulate the performance of a current source implemented using the improved Howland source and a GIC to cancel out the capacitive part of the output impedance. They study the excitation frequency range of 1 kHz–10 MHz. The maximum output impedance achieved is 103.41MΩ at 1 kHz which drops below 1 MΩ at 1 MHz. Khalighi and Mikaeili (2018) describes several V-I converter configurations used in EIT systems. Their study includes the improved Howland circuit, a triple op-amp Howland circuit, and a new configuration which uses two triple op-amp Howland circuits to implement a floating current source. All configurations are simulated over a frequency band of 1 kHz–1 MHz. The simulation results show that the highest output impedance is achieved by using the dual triple op-amp Howland-based floating current source, which has a value of 110 MΩ at 1 kHz which drops to 0.3 MΩ at 1 MHz.

Another class of EIT current sources implements a current conveyor II (Sedra and Smith 1970). Bragos et al (1994) describes the design and analysis of a wide-band current conveyor source built using a current-feedback amplifier (CFA) that achieves an output resistance (> 1 MΩ) and an output capacitance (< 5 pF) over the frequency range from 10 kHz and 500 kHz. This type of current source is well-suited for integrated circuit (IC) implementation. Rao et al (2019) describes an IC current conveyor source that achieves and output impedance 101 kΩ at 1 MHz and 19.5 kΩ at 10 MHz. Neshatvar et al (2019) reviews the progress made in the development of IC current sources and discusses the performance of several current source types. The current source described in Seoane et al (2008) uses a differential amplifier with unity gain and positive feedback. However, the output impedance performance depends on the differential gain being unity. As the output impedance is a function of the differential gain, the system performance is affected by the frequency response, device tolerance, and the common-mode rejection ratio (CMRR) of the op amps used.

In active electrode EIT systems, the current sources are placed at the electrodes, significantly reducing stray capacitance and making it possible to maintain high output impedance without using capacitance cancellation techniques. However, the stray capacitance in conventional EIT systems, where the electrodes are connected to the EIT instrument using cables, generally require capacitance cancellation for high effective output impedance. These compensated current sources are analog circuits that require some trimming for optimal operation, though the trimming may be automated through the use of digitally-controlled elements such as digitally programmable resistors. However, these analog elements add complexity and cost to the system.

This paper discusses a new method of achieving a high-precision current source in which the adjustments necessary to produce a large output impedance are performed on the signal that is applied to the current source. In the simplest terms, the voltage signal that is applied to the V-I converter is adjusted to compensate for the current that will flow in the output impedance of the current source, including any additional stray capacitance, so that the desired current will flow in the load. The additional current is produced such that when the fraction of the current that flows in the current source output impedance is removed, the desired current flows in the load. In this way, the new technique can be considered to be a pre-distortion technique that adjusts the input signal in anticipation of the distortion that will occur in the current source. Additionally, this pre-distortion is done in the digital domain, using digital signal processing (DSP) techniques. By using DSP, the required signal processing can be implemented with the desired precision and is not subject to variations with time and temperature as are analog circuits. Additionally, replacing analog components with DSP has the potential to produce a lower-cost system.

2. New current source system

Figure 1 is a block diagram of the new current source system. A conventional V-I converter is used that has an output impedance that is characterized as a parallel resistor and capacitor, R_o and C_o, respectively. Many different types of V-I converter can be used, though the Howland current source is a suitable choice (Franco 2003). The V-I converter device takes an input voltage, V_o, and produces a proportional current, I_o = A_iV_o, where A_i is a gain constant. The output current, I_L, goes into an unknown load impedance, Z_load, producing a load voltage, V_L. Because of the current that flows in R_o and C_o, which is dependent on V_L, I_L does not equal I_o. The goal for the overall system is to make the load current, I_L, equal a desired value by controlling I_o. Note that it may be possible to omit the V-I converter in this system if a current-output digital to analog converter (DAC) is available that can provide an output impedance that is sufficiently stable over the expected range of the load voltage, V_L. Obviously, this change would simplify the hardware implementation of the system but the system operation would be the same.

Figure 1.

Block diagram of the current source system.

The input voltage for the V-I converter is generated inside the DSP block and is converted into analog form using a DAC. The digital processing can be implemented in multiple ways, including using a digital signal processor integrated circuit or a field programmable gate array (FPGA). The voltage produced on the load, V_L, is brought back to the DSP through an analog to digital converter (ADC). Note that for applications such as EIT, the system applies current and measures the resulting voltage, so the ADC is already needed in the system and does not represent added cost for the current source system. Also, since C₀ can include the capacitance of a cable connecting to an electrode, even if that capacitance is large, the ADC can be placed on the instrument side of the cable and the source will mitigate the effect of the cable capacitance.

The current source system is designed to generate a sinusoidal current at some desired frequency. It is assumed that the digital processing system has knowledge of the output impedance, Z_o, of the V-I converter at the desired operating frequency. Any additional stray impedance to ground is lumped into this Z_o which can be measured during a calibration process and stored in the DSP. The fundamental approach to canceling the effect of R_o and C_o, i.e. making the desired current, I_L, flow in the load, is to increase I_o by the amount of current that flows in Z_o. One solution is to operate in an additive mode, where output current is set equal to I_L plus the current lost in the output impedance, V_L/Z_o, where V_L is the voltage on the load. A drawback of this approach is that it produces an iterative algorithm, since each correction of the output current will change V_L/Z_o.

A better approach is to multiply the desired current by a scaling factor, S_scale, such that

$$I_o=S_{\text{scale }}{I}_L.$$ (1)

S_scale is a function of the fraction of the output current that flows in Z_o which determined by the current divider between Z_o and the load impedance, Z_L. Therefore, S_scale will not be a function of V_L for a fixed Z_L. To find S_scale, assume that the total load impedance seen by the system, Z_total, is the parallel equivalent of Z_o and the unknown load impedance, Z_load, i.e.

$$Z_{\text{total }}=Z_{\text{load }}\Vert Z_o=\frac{Z_{\text{load }}{Z}_o}{Z_{\text{load }}+Z_o}=\frac{V_L}{I_o}.$$ (2)

The relationship between I_L and I_o is found using the current divider relationship

$$I_L=\frac{Z_o}{Z_o+Z_{\text{load }}}{I}_o=\left[1-\frac{Z_{\text{load }}}{Z_o+Z_{\text{load }}}\right]I_o.$$ (3)

Substituting Z_total from (2) produces

$$I_L=\left[1-\frac{Z_{\text{total }}}{Z_o}\right]I_o=\left[1-\frac{\frac{V_I}{I_o}}{Z_o}\right]I_o$$ (4)

and solving for S_scale yields

$$S_{\text{scale }}=\frac{I_o}{I_L}=\frac{Z_o}{Z_o-\frac{V_L}{I_o}}.$$ (5)

For a fixed Z_load, S_scale is computed directly without iteration. The desired scaling factor can be computed during operation by using the known I_o, pre-determined Z_o, and measured V_L.

In a multiple-source EIT system, each current source would see a constant Z_o that would be measured, stored, and used to adapt the applied current. In a serial system in which a source is switched between electrodes, Z_o values for each electrode or electrode pair can be measured and stored during the calibration process and used to compensate the output current at the appropriate time. Applying different Z_o values at different times can easily be implemented by the algorithm since it does not require any hardware adjustments.

3. Digital signal processing details

Figure 2 is a block diagram of one approach to performing the digital processing that uses complex baseband processing.

Figure 2.

Digital processing for the current source system. Lines and blocks in bold represent complex signals and functions.

The signal from the ADC, V(k), is the sampled and quantized voltage on the load. A Hilbert transform is used to create the quadrature component of V(k). Since V(k) is a sinusoid, a simple implementation of the Hilbert transform is used:

$$\widehat{V}(k)=\frac{V(k-2)-V(k)}{2\text{sin}\left(2\pi f_{sig}/f_s\right)},$$ (6)

where k is the sample index, $\widehat{V}(k)$ is the Hilbert transform of V(k), f _sig is the signal frequency, and f _s is the sampling frequency. This Hilbert transform introduces a one sample delay and works for f_sig < 0.5f_s. The input signal is delayed by one sample and combined with the output of the Hilbert transform to create a complex signal. This complex signal is frequency translated to baseband by multiplying by the internally-generated signal $e^{\left(-j2\pi k{f}_{sig}/f_s\right)}$ to produce the complex baseband representation of the voltage on the load.

The complex baseband voltage, stored Z_o, and a delayed complex baseband representation of the applied current, I_o is used to compute S_scale according to (5). The delay is needed to compensate for the delay in the remainder of the transmit and receive paths, i.e. the current used in the calculation of S_scale must be the current applied to produce the particular voltage sample. The desired load current value, specified as a complex baseband quantity, is multiplied by S_scale to produce I_o which is split into real and imaginary components, multiplied by cos(2πkf_sig/f_s) and −sin(2πkf_sig/f_s), respectively, and summed to produce the signal that is fed to the DAC.

4. Implementation

A prototype of the current source has been implemented and tested. Table 1 shows the discrete components used in the implementation. The DSP processing is performed using an Artix-7 family FPGA on a Digilent CMOD-A7–35T module. In the implementation, the 18-bit AD4002 analog-to-digital converter (ADC) operates at 1.2 MSPS while the 16-bit LTC1668 digital-to-analog converter (DAC) operates at 24 MSPS.

Table 1.

Implemented system components.

Components	Parts
OpAmp	Analog Devices AD8033
Resistors	0.1%
DSP	Xilinx Artix 7 FPGA
DAC	Linear Technology LTC1668, 50 MSPS
ADC	Analog Devices AD4002, 2 MSPS

4.1. Analog implementation

The V-I converter is a Howland current source, an op-amp based V-I converter whose output impedance is controlled by matching resistors in the positive and negative feedback paths (Franco 2003). Howland-based current sources are extensively used in EIT systems because of their low complexity, superior driving capability, and good performance over a wide frequency range (Denyer et al 1994). Figure 3 shows the Howland source configuration that is used. For patient safety, a DC blocking capacitor is placed in the positive feedback path of the op amp, preventing the source from applying any DC current to the load (electrode) even if a DC signal is applied at its input. The source is implemented using the AD8033 op-amp and 0.1% resistors. No trimming resistors are included. A 100 kΩ resistor is placed from the current source output to ground, effectively limiting output impedance of the source. As will be described later, the native (non-compensated) output impedance of the circuit that is needed for the adaptive algorithm of (5) is obtained by a simple open circuit measurement. Limiting the impedance with the 100 kΩ resistor makes this measurement easy and reliable.

Figure 3.

Howland current source with a DC blocking capacitor.

The load voltage is buffered using a unity-gain follower followed by a second buffer that adds a DC offset equal to one-half of the ADC reference voltage, as required. Both circuits are implemented using the AD8033 op amp.

4.2. Digital implementation

The processing shown in figure 2 is implemented in the Xilinx Artix 7 FPGA. The implementation uses fixed-point arithmetic and makes extensive use of Xilinx LogiCORE IP blocks. Digital sine and cosine waveforms are generated using direct digital synthesis with the DDS Compiler v6.0 (Xilinx Inc. 2017) configured in rasterized mode.

The downconversion process in figure 2, i.e. the computation of the baseband in-phase and quadrature voltages, produces V_I and V_Q with only a small delay, enabling the current source to compensate for the output impedance within a few samples of startup. However, this process is suboptimal with respect to signal-to-noise ratio (SNR) if the noise on the input is assumed to be Gaussian. Consequently, separate digital matched filters process the voltage samples in parallel with the processing shown in figure 2 to provide the measured in-phase and quadrature voltages used for Z_o computation, image reconstruction, etc. A digital matched filter provides the maximum signal-to-noise ratio (SNR) in the presence of Gaussian noise and has been theoretically proven to be the maximum likelihood estimator (McEwan et al 2007) . In the present implementation, the matched filters integrate over 1024 samples.

4.3. Apparent output impedance measurement

The primary purpose of the described system is to compensate for any current loss in the V-I converter output impedance and any stray impedance to the ground. By doing this compensation, the apparent output impedance will be very high, making it difficult to measure accurately. One approach for estimating a high output impedance without using high precision external instrumentation is to use a pair of low temperature coefficient resistors as test loads. The method does not require precise knowledge of the resistor values, or even that they be pure resistances, but does require the values to be insensitive to the current flowing through them, hence the need for low temperature coefficient resistors.

The voltage is measured for the same applied current with loads of R₁, R₂, and the series combination of R₁ and R₂. These loads are assumed to be in parallel with the output impedance, Z_o, resulting in three equations with three unknowns, R₁, R₂, and Z_o. Denoting the total impedances measured, i.e. the ratio of measured voltage to the desired load current, for the R₁, R₂, and R₁ + R₂ loads as Z₁, Z₂, and Z₃, respectively, the output impedance can be found by solving the quadratic equation

$$\left(Z_3-Z_1-Z_2\right)Z_o^2+2Z_1{Z}_2{Z}_o-Z_1{Z}_2{Z}_3=0,$$ (7)

while the resistor values can be found using

$$R_1=\frac{Z_1{Z}_o}{Z_o-Z_1}$$ (8)

$$R_2=\frac{Z_2{Z}_o}{Z_o-Z_2}.$$ (9)

This approach will be used to find the apparent Z_o values presented later. Note that R₁ and R₂ are only used to evaluate the source performance and are not part of the current source calibration or operation. The output impedance used by the compensation algorithm is found using an open circuit measurement.

5. Calibration

As shown in (5), the computation of the scaling factor S_scale requires knowledge of the total non-compensated output impedance of the current source Z_o, where this value includes any additional shunt resistance or capacitance due to stray or parasitic effects. The first step in obtaining this Z_o is to calibrate both the current source voltmeter and current source output current (into a short) using a calibration circuit. The calibration circuit shown in figure 4 is built using many of the same components (FPGA, ADC, DAC) and algorithms (DDS, voltmeter) as the current source and includes a current-to-voltage (I-V) converter, reed relay switches, and a 2 kΩ precision resistor (Vishay Z-Foil VFCP Series, ± 0.01%, ± 0.2ppm/°C). The main clock for the calibration system and current source are the same, ensuring that the systems operate synchronously. Calibration is performed individually for each desired excitation (operating) frequency. A sinusoid at the excitation frequency with known amplitude is output from the DAC. Closing switch S4 alone applies that voltage to the ADC which collects samples that are processed by matched filters to produce the measured complex voltage. This voltage is used to compute a complex calibration factor relating the digital voltmeter reading to a complex analog voltage. Closing switches S1 and S4 simultaneously applies the voltage source to both the current source voltmeter being calibrated as well as the calibration voltmeter, enabling the computation of a complex calibration factor relating the digital voltage measured at the current source to a complex analog voltage. Note that the current source output current is set to zero during this step. Closing switches S3 and S5 simultaneously applies the known voltage to the precision resistor and, therefore, injects a known current into the virtual grounded input of the I-V converter. The I-V converter output is also connected to the calibration voltmeter, enabling the computation of a complex calibration factor relating the digital voltage measured by the voltmeter to the complex analog current applied to the I-V converter. Closing switches S2 and S5 connects the I-V converter to the current source, enabling the measurement of the output current into a (virtual) short. This measurement enables the computation of a complex calibration factor relating the digital current word provided to the current source to the complex analog current that it will deliver to ground.

Figure 4.

Calibration system.

The net result of these calibration steps are two complex calibration factors for the current source - one that is used to convert the digital voltage it measures to its analog voltage value and a second that can convert a desired analog current into the digital value that must be supplied.

Once the current source and voltmeter are calibrated, a small current is applied to an open circuit and the resulting voltage measured. The size of the applied current is kept sufficiently low that the resulting voltage does not saturate the voltmeter. The ratio of the measured voltage to applied current provide an estimate of Z_o. Note that a single calibration circuit can be used to calibrate multiple current sources. The calibration process is performed at each excitation frequency in the operating range (11 kHz–1 MHz).

6. Experimental results

In this section, the experimental results for the proposed current source architecture is discussed.

6.1. Waveforms

Figure 5 shows the operation of the system with a 5 kΩ load and a 1 MHz excitation frequency. The bottom trace in the figure shows voltage on the load at the start of the 2 ms burst of sinusoidal current that is applied. The upper trace shows a timing signal that indicates when the matched filters begin their integration period. This signal is used as a trigger for the oscilloscope and a timing reference for interpreting the results. To make the initial transient easier to observe, the output impedance compensation is engaged 25.8 μs after the start of the burst. As can be seen in the figure, the voltage on the load increases when the compensation is applied due to the increase in applied current that compensates for the current lost in the output impedance. When engaged, the algorithm immediately applies the additional current; there is no adaptation transient. In practice, the adaptation can be applied at the start of the burst without the delay shown in figure 5. Similarly, the matched filter voltage measurements currently starts 106.7 μs after the start of the burst, but this delay can be shortened. The matched filter integrates over 1024 samples taken at 1.2 MSPS resulting in an integration period of 0.853 ms.

Figure 5.

Adaptive operation scope shot.

6.2. Output Impedance

The method introduced in section 4.3 is used to measure the output impedance with and without compensation. Resistors with values of 0.5 kΩ and 1 kΩ are used to perform the measurements and (7) is used to calculate the output impedance. Figure 6 shows the results with and without compensation (adaptation). The output impedance is broken down into a parallel resistance and capacitance and results are shown for the frequency range of approximately 10 kHz to 1 MHz. Figure 6(a) shows that the uncompensated output resistance is approximately 100 kΩ as expected due to the 100 kΩ resistor across the output of the current source. In the adaptive mode, the output resistance is approximately 35 MΩ at the low frequencies and drops to approximately 7 MΩ at 1 MHz. Figure 6(b) shows that output capacitance is approximately 19 pF without compensation and drops to below 0.5 pF across the full frequency range with adaptive compensation.

Figure 6.

The new current source output impedance.

6.3. Resistive load

The ability of the adaptive current source to accurately measure a load impedance across a frequency range was evaluated with different resistive loads. Axial leaded resistors with different values but the same tolerance (0.1%) were used. The measurements were taken for three modes of operation: the non-adaptive mode where the source does not compensate for the output impedance, the adaptive mode, and a burst-by-burst mode. In this last mode of operation, the applied current is not adjusted within the burst but, rather, the burst is applied without any compensation and the load voltage is measured and returned to the controlling computer. The needed current adjustment is computed and used to set the appropriate current for the next burst. This burst-by-burst mode has the advantage of working with the matched-filter voltages which have higher SNR than those obtained by the sample-by-sample downconversion process. The burst-by-burst mode is only useful with a fixed, non-time varying load. It is presented here only for comparison to the regular adaptive mode, confirming the proper behavior of the adaptive algorithm implemented in the FPGA.

Figures 7 and 8 show the measured load resistance and capacitance (modelled as a parallel RC) when delivering current to a 1 kΩ and a 2 kΩ axial lead resistors, respectively, with excitation frequencies from 30 kHz to 1 MHz. The measured load is found using the known applied current and the measured voltage. In the ‘Non Adapt’ case, the current source is operating without compensation, producing a measured capacitance of approximately 18 pF in parallel with the resistor. In the ‘Burst Adapt’ and ‘Adapt’ cases, the system uses the previously measured output and stray impedance to correct the applied current, resulting in a decrease in the measured capacitance to below 0.5 pF.

Figure 7.

Measurements of 1 kΩ load.

Figure 8.

Measurements of 2 kΩ load.

Since an axial lead resistor will have a few tenths of a picofarad of parallel capacitance, the measured capacitance is not expected to become zero. Note that the uncompensated measured resistance is incorrect due to the 100 kΩ output resistance. Both the adaptive results provide the correct resistance at low frequencies. In both the adaptive and non-adaptive cases, the result is nearly independent of frequency, showing only a small decrease in the measured resistance with higher frequency. This drop in resistance value is likely due to small residual error within the calibration process.

The burst adaptive and adaptive results in figures 7 and 8 are nearly identical, indicating that using the lower SNR voltages in the adpative algorithm does not bias the results. In both cases, readings from 100 bursts were averaged to produce each data point. However, the lower SNR of the voltages used in the adaptive algorithm does introduce noise into the applied current and, therefore, the measured voltages. Figures 9(a) and (b) show the SNR of the matched filter voltage measurements for the adaptive and non-adaptive cases for the 1 kΩ and 2 kΩ loads. In each case, the adaptive case has some SNR degradation, though the loss is within 3 dB. If desired, introducing some filtering into the adaptive loop should be able to reduce this loss.

Figure 9.

SNR of load measurements.

The intended application for the high output impedance current source is an EIT system for medical applications, meaning that it will be applied to biological tissues. An electrical equivalent circuit for a biological tissue is represented by the Cole-Cole (Santos et al 2013) load which consists of two parallel load branches. One branch has the intracellular resistance in series with the membrane capacitance while the other branch contains extracellular resistance. A Cole-Cole model was built in the lab using a 680 Ω resistor for the extracellular resistance and 750 Ω resistor and 2.2 nF capacitor for the intracellular resistance and the membrane capacitance, respectively (Freeborn et al 2017). In the Cole-Cole load measurement, the complex impedance of the load was measured in both the adaptive and non-adaptive modes. Figure 10 shows the imaginary part (reactance) plotted as a function of the real part (resistance) for these measurements along with the analytical calculated result. The figure shows that the adaptive measured complex impedance matches the calculated values of the impedance more closely. These results demonstrate the effectiveness of the current source with a relatively highly capacitive load.

Figure 10.

Cole-Cole load measurements.

7. Summary

This paper describes a new current source that produces high effective output impedance by digitally adjusting the applied current. The source uses simple, adjustment-free analog electronics by moving most of the processing into the digital domain. The results presented show the effectiveness of the source for both resistive and complex loads.