Fabrication and modeling of recessed traces for silicon-based neural microelectrodes

Abstract

Objective.

Chronically-implanted neural microelectrodes are powerful tools for neuroscience research and emerging clinical applications, but their usefulness is limited by their tendency to fail after months in vivo. One failure mode is the degradation of insulation materials that protect the conductive traces from the saline environment.

Approach.

Studies have shown that material degradation is accelerated by mechanical stresses, which tend to concentrate on raised topographies such as conducting traces. Therefore, to avoid raised topographies, we developed a fabrication technique that recesses (buries) the traces in dry-etched, self-aligned trenches.

Main results.

The fabrication technique produced flatness within approximately 15 nm. Finite element modeling showed that the recessed geometry would be expected to reduce intrinsic stress concentrations in the insulation layers. Finally, in vitro electrochemical tests confirmed that recessed traces had robust recording and stimulation capabilities that were comparable to an established non-recessed device design.

Significance.

Our recessed trace fabrication technique requires no extra masks, is easy to integrate with existing processes, and is likely to improve the long-term performance of implantable neural devices.

1. Introduction

Clinical deep brain stimulators [1], cochlear implants [2, 3], and spinal cord stimulators [4, 5] are used for treatment of Parkinson’s disease, essential tremor, depression, obsessive-compulsive disorder, obesity, deafness, and chronic pain in cases where other options have failed. Collectively, these systems have benefitted hundreds of thousands of patients and demonstrated the signficant clinical potential of interfacing with the nervous system even at a relatively crude level.

Meanwhile, in research labs, the development of smaller, more complex microelectrodes has allowed for higher-bandwidth and more intimate contact with the nervous system. Since 1970 [6], many of these devices have been produced using microelectromechanical systems (MEMS) fabrication techniques, enabling studies of next-generation deep brain stimulators [7–9] and increasingly sophisticated visual [10, 11], auditory [12–14], and tactile/motor [15, 16] prostheses in animals and humans.

Unfortunately, advanced functionality has come at a cost to reliability. While there are examples of microelectrodes performing successfully for many years, in most cases, performance declines over months [17–19]. Understanding the causes of microelectrode failure is an active area of research. The prevailing view is that a variety of factors co-contribute, including device materials degradation and various aspects of the tissue reaction such as biofouling, encapsulation by glia, changes in neuronal health/activity/connectivity, and gross movement of the device over time [18–24]. In order to bring advanced neural microelectrodes into the clinic, engineers will need to mitigate each of these failure modes [25].

Materials degradation has been studied for a variety of device types and materials. Most commonly, the insulation materials develop cracks or pinholes [19–21, 26–28], exposing too much of the electrode sites [20, 21, 28], creating short-circuits and crosstalk [27, 29, 30], or causing electrode site material to detach [28, 31]. Both ceramics [19, 31] and polymers [20, 21, 26–30] are vulnerable to degradation and no material has yet established itself as immune to degradation.

While most studies focused on chemical mechanisms, relatively few have examined the effects of mechanical stress on neural electrode materials failure. A study by Schmitt et al compared the reliability of several insulation strategies in saline solution [32]. The authors used a wet etch to fabricate devices with recessed (buried) traces, and found that these devices lasted five times longer than non-recessed devices with identical insulation material. The authors noticed delamination of insulation materials over non-recessed traces and theorized that the raised topography of the non-recessed traces concentrated the intrinsic stresses generated during fabrication and accelerated materials degradation through a process called stress corrosion cracking. A different study by Kozai et al looked at material failures in NeuroNexus (Ann Arbor, MI, USA) silicon microelectrodes implanted in mice for 19–27 weeks [19]. The authors reported cracking and corrosion of insulation materials over the traces, especially near the electrode sites. Mechanical modeling of extrinsic stresses (from device movement relative to the brain) showed that these areas also experienced up to three times higher stresses due to the combined effects of raised traces and proximity to stiff iridium electrode sites. Although these issues may be specific to the design of NeuroNexus electrodes, it nevertheless supports the idea that mechanical stress may influence the longevity of insulation materials.

Here, we present a fabrication technique similar to Schmitt et al, but employing a dry etch, which is easier to implement. We successfully incorporated the technique into our fabrication process for functional probes, similar to those we have used extensively in long-term animal studies [12, 13]. We previously described our method in a short conference publication [33]. In this report, we provide greater detail on the method, perform finite element modeling to show the predicted effect on intrinsic stress, and provide extensive electrochemical validation to show that recessed devices have recording and stimulation capabilities comparable to an established non-recessed device design.

2. Methods

2.1. Wafers and photolithography

As shown in figure 1(a), the process began with four-inch-diameter silicon-on-insulator wafers with 1 μm wet-grown thermal oxide on both sides (Ultrasil, Hayward, CA, USA). These wafers had a ‘device’ silicon layer 80 μm thick, a ‘buried oxide’ thermal oxide layer 2 μm thick, and a ‘handle’ silicon layer 350 μm thick. Silicon-on-insulator wafers were used for functional devices, while regular oxidized silicon wafers were used for test samples. In figure 1(b1), AZ 5214E-IR photoresist from Merck (Darmstadt, Germany) was patterned using a standard image reversal lithography protocol. Traces were 10 μm wide and 10 μm apart, with 5 μm wide curved features around electrode sites.

Figure 1.

Overview of the fabrication process with emphasis on the electrode site. Not to scale. A side-view cross section near the tip of a device is depicted; the rest of the shank and the bond pad areas are off to the right and not shown. (a) Initial oxidized silicon-on-insulator wafer. (b1)–(b4) Recessed traces process, including (b1) photolithography, (b2) reactive ion etching (recessed traces only), (b3) trace metal deposition, and (b4) lift-off and plasma cleaning. This was followed by (c) deposition of insulation layers, (d) opening of vias, (e) sputter deposition of electrode site metal, (f) etching the shape of the shanks, (g) backside thinning, and (h) manual release. The critical difference in the two processes is the recessed traces etch step b2 which results in the trace metal being positioned inside the thermal silicon dioxide.

2.2. Reactive ion etching to pattern trenches

This step is depicted in figure 1(b2). Wafers were etched in an NLD-570 inductively-coupled plasma RIE (ULVAC Technologies, Inc., Methuen, MA, USA) with 90 sscm argon, 10 sscm octafluoropropane, 3 mTorr pressure, 1 100 W coil power, and 227 W platen power, at 5 °C. The chamber was O₂-cleaned for 20 min and the etch was run for 5 min on a blank wafer as preconditioning before etching. This recipe had an etch rate of 410 nm min⁻¹ and a selectivity of approximately 2:1 for silicon dioxide vs. photoresist.

2.3. Metal deposition

As shown in figure 1(b3), an electron beam evaporator (Denton Vacuum, LLC, Moorestown, NJ, USA) with throw distance approximately 50 cm was used to deposit a metal stack of 30 nm titanium, 20 nm platinum, 300 nm gold, and optionally an additional 50 nm titanium at rates of 1.0, 1.5, 2.0, and 1.0 Å s⁻¹, respectively. Samples were positioned in the center, directly facing the source, with rotation turned on. For functional devices, a metal stack of 30 nm titanium, 20 nm platinum, and 300 nm gold was subsequently deposited on the bond pads only.

2.4. Lift-off, cleaning, and argon etching

As depicted in figure 1(b4), samples were immersed in acetone for at least 1.5 h. The samples were then transferred to fresh acetone, sonicated for 5 min, and rinsed with isopropanol and water. Next, an oxygen plasma barrel asher (SCE 106, Anatech Ltd., Sparks, NV, USA) was used to remove remaining polymeric residues for 5 min at 150 W, 40 sscm, and 435 mTorr. An optional argon etch in the ULVAC NLD-570 ICP RIE was performed at 5 °C, 3 mTorr, 600 W coil power, 145 W platen power, 100 sscm argon to improve yield of devices near the edges of the wafer. Finally, less than 30 min before deposition of insulation layers, samples were cleaned by dipping into a solution of 100 ml water, 20 ml 29% NH₄OH, and 20 ml 30% H₂O₂ for 5 s then rinsed in water.

2.5. Insulation

As shown in figure 1(c), eight layers of silicon nitride (N) and silicon dioxide (O) were deposited in the order NONONONO to a total thickness of 1.85 μm using a parallel electrode PECVD reactor (SPTS Technologies Ltd, Newport, UK). The recipes used 300 °C, 900 mTorr, and the high frequency generator at 20 W for silicon nitride and 30 W for silicon dioxide. The gas flows were 35 sscm SiH₄, 55 sscm NH₃, and 1960 sscm N₂ for silicon nitride, and 10 sscm SiH₄, 1420 sscm N₂O, and 392 sscm N₂ for silicon dioxide.

2.6. Functional device fabrication

Figure 1(d) shows the etching of vias by RIE, which opened the electrode sites (shown) and bond pads (not shown). After this, electrode site metal was deposited by sputtering titanium at 200 W DC for 8 min 20 s (approximately 50 nm) followed by iridium at 100 W DC for 30 min (approximately 200 nm) with rotation on (figure 1(e)). The pressure was 4 mTorr and gas flow was 15 sscm argon. Next, the shapes of the shanks were defined by first using RIE to etch through the PECVD insulation and the thermal SiO₂. Then, Bosch-process deep reactive ion etching (DRIE) was performed in a Rapier™ DRIE (SPTS Technologies Ltd, Newport, UK) (figure 1(f)). The buried oxide in the silicon-on-insulator wafer served as the etch stop. To free the devices from the handle wafer, the 4″ wafers were adhered face-down to a 6″ oxidized silicon wafer using a thermally-conductive paste (Cool-Grease™, AI Technology, Princeton Junction, NJ, USA) then etched from the backside using an SF₆-based etch in the Rapier™ DRIE for approximately 30 min (figure 1(g)). The buried oxide was also then etched from the backside using RIE. Finally, the devices were released using forceps (figure 1(h)). This process represents the current evolution of a process initially developed by Han et al [13]. Finished microelectrodes were then epoxied onto custom printed circuit boards (PCBs), wire bonded, and over-coated with EPO-TEK® 301 epoxy (Epoxy Technology, Inc., Billerica, MA, USA). The electrode sites were activated to iridium oxide in phosphate buffered saline (PBS) by applying a 0.25 Hz 50% duty cycle square wave from −0.65 to 0.9 V until the increase in the cathodic charge storage capacity (CSC_c) measured by cyclic voltammetry (see section 2.7) began to plateau.

2.7. Physical characterization

Scanning electron microscopy (SEM) images were collected using 2–5 kV accelerating voltage and either the in-lens or in-chamber secondary electron detectors in a Hitachi (Chiyoda, Tokyo, Japan) SU8230 SEM. Profilometry was performed with a DektakXT® stylus profilometer (Bruker, Inc., Billerica, MA, USA) with 12.5 μm stylus tip. Focused ion beam (FIB) cross section analysis was performed using a ZEISS (Oberkochen, Germany) Crossbeam with gallium ion source.

2.8. Finite element modeling

Finite element modeling was carried out in COMSOL Multiphysics®’s structural mechanics module (COMSOL, Inc. Burlington, MA, USA). 2D cross sections of shanks with non-recessed or recessed traces were drawn with accurate dimensions. The model used isotropic material properties from COMSOL’s MEMS material library. Based on characterization data, the PECVD silicon dioxide was given −140 MPa (compressive) intrinsic stress and PECVD silicon nitride +330 MPa (tensile) intrinsic stress. Based calculations and literature values [34], the thermally-grown silicon dioxide was given −300 MPa (compressive) intrinsic stress, titanium −275 MPa (compressive) [35], platinum +314 MPa (tensile) [35], and gold +90 MPa (tensile) [36]. The outer boundaries were free and no external forces were applied.

2.9. Electrochemical validation

An Autolab PGSTAT128N potentiostat/galvanostat (Metrohm AG, Herisau, Switzerland) was used to acquire AC electrochemical impedance measurements in room-temperature PBS using a large platinum counter electrode, an Ag/AgCl reference electrode, and 10 mV peak-to-peak sinusoids from 0.1 to 10 000 Hz. The CSC_c from cyclic voltammograms was acquired using the same system sweeping between −0.6 and 0.8 V at 50 mV s⁻¹. Stability of charge injection capacity was evaluated using one million consecutive charge-balanced, cathodic-first current pulses with 150 μs pulse width, 4 nC per phase, 25 μs interphase interval, and 400 Hz repetition rate from a PlexStim™ stimulator (Plexon, Inc., Dallas, TX, USA). Voltage transients in response to 72 μA current pulses were measured before and after one million cycles using a PicoScope® 2000 USB oscilloscope (Pico Technology, St. Neots, UK). Statistical comparisons were made using unpaired, homoscedastic, two-tailed Student’s t-tests.

Neural recording capability was tested using pseudo extracellular voltage signals in PBS using a Plexon Headstage Tester Unit (figure 2). A source waveform was previously collected from cat sensorimotor cortex six weeks post-implantation and high-pass filtered (see supplementary materials (available online at https://stacks.iop.org/JNE/17/056003/mmedia)) [37]. This file was played by Windows Media Player (Microsoft, Inc. Redmond, WA, USA) at the maximum audio output volume and fed into a ball electrode (CONMED, Inc., Utica, NY, USA). Signals were then picked up from two adjacent recessed electrode sites on one probe approximately 3 cm away from the signal source, differentially amplified, high-pass filtered, and recorded using a Plexon OmniPlex® Neural Data Acquisition System. Gain was automatically configured for each channel. The recordings were analyzed in Plexon Offline Sorter™.

Figure 2.

Experimental setup for recording pseudo extracellular signals. A pre-recorded biological neural signal recording was played between the ball electrode and platinum counter electrode, producing voltage gradients within the PBS that could then be detected on two adjacent sites on the recording microelectrode.

3. Results

3.1. Physical characterization

Figures 3(a) and (b) show optical images of non-recessed and recessed devices. The traces are visible through the transparent insulation. The devices appear very similar except for increased contrast along the edges of non-recessed traces and slightly different overall colors of the shanks, likely due to slightly reduced thermal silicon dioxide substrate thickness from the brief argon etch. To quantify the degree of flatness, stylus profilometry was performed on both types of devices. N = 6 measurements taken at various places on a non-recessed wafer showed the traces were 341 ± 7 nm above the wafer surface, in contrast to N = 10 measurements of recessed traces which were 15 ± 7 nm below the wafer surface (figure 3(c)). The devices were next examined using SEM. At low magnification, the raised topography of insulation covering non-recessed traces was easily visible (figure 3(d)), while recessed traces were flat enough as to be invisible (figure 3(e)). To understand the interior structure of the traces, high-magnification SEM images of FIB cross sections were obtained (figures 3(f) and (g)). The contrast between the repeating layers of silicon dioxide and silicon nitride insulation revealed how the insulation curves sharply upward over non-recessed traces but is nearly flat over recessed traces. These images also confirmed the plausibility of our finite element model geometry (see section 3.2). Completed devices were then wire bonded and epoxied onto custom PCBs (figure 3(h)).

Figure 3.

(a) Light micrograph of a non-recessed device. The middle of a shank is shown. The traces are visible through the transparent insulation. The dashed line indicates the path along which the profilometer measured the heights of the traces. (b) Light micrograph of a recessed device. The device appeared nearly identical to the non-recessed device except for less contrast on the edges of the traces and a slightly different insulation color. (c) Stylus profilometry along the dashed lines in the previous panels. The non-recessed traces were approximately 350 nm tall, corresponding to the 350 nm thick metal stack, whereas the recessed traces were flush with the wafer surface within approximately 15 nm. Note that height is exaggerated approximately 100-fold for visibility. (d) and (e) The raised topography of the non-recessed traces was easily visualized by SEM, while the traces on recessed devices were nearly invisible at this magnification. (f) and (g) FIB cross sections revealed the internal structure of a non-recessed and recessed trace. The images are false-colored to assist in interpretation. The insulation layers curve sharply up and over the non-recessed trace, but are nearly flat over the recessed trace. Dashed line indicates wafer surface. Dark areas are charging artifacts. (h) A device wire-bonded and epoxied onto a custom printed circuit board for electrochemical testing.

One issue encountered during fabrication warranted further investigation. After metal deposition and lift-off, small metal ‘fences’ were found towards the outer 50% of the wafer, and only on specific sides of the features corresponding to the direction of deposition. The probable mechanism of fence formation is illustrated in figure 4. In an electron beam evaporator, metal is evaporated in a crucible some distance (here, approximately 50 cm) away from the wafer. The evaporated metal then showers onto the wafer in nearly straight line trajectories. Since the spot where the metal is evaporated by an electron beam is very small, the metal essentially comes from a point source 50 cm from the wafer. Therefore, in the center, the trajectory is nearly vertical, and in this area no fences were formed (figures 4(a)–(c)). Meanwhile, towards the edges, the trajectory is slightly angled, creating a widened gap on one side and fences on the other side (figures 4(d)–(f)). The angle would have been 2.9° at 1” from the center and 5.7° at the edge of the wafer. SEM inspection of a recessed trace immediately after metal deposition revealed that the fences formed without actually bridging the photoresist’s undercut (figure 4(g)). This rules out the possibility that fences were due to poor lift-off, which can happen if photoresist thickness and/or undercut is insufficient (causing metal to bridge the gap and create torn-off structures when physically separated).

Figure 4.

Likely mechanism of fence formation. (a) In the center of the wafer, metal is deposited vertically and lands in the middle of the trench. (b) Lift-off removes metal everywhere besides the trench. (c) After lift-off, SEM shows the metal was squarely centered in the trench and had no fences. (d) In contrast, towards the edges of the wafer, metal is deposited at a slight angle, resulting in a widened gap on one side and fences on the other. (e) After lift-off, the fences remain. (f) SEM image of a trace near the edge of the wafer. Asterisks denote polymer residues, which were present alongside traces all over the wafer, but could be successfully cleaned off by oxygen plasma. (g) A recessed trace near the edge of the wafer immediately after metal deposition. This 90° corner feature reveals the direction-dependent nature of the fences: fences appeared only along edges corresponding to the direction of metal deposition. Furthermore, the fences did not connect to the metal on top of the photoresist, which would have indicated poor lift-off.

3.2. Finite element modeling

To confirm whether recessed traces could be expected to reduce stress concentrations, finite element modeling was performed. Figure 5 shows von Mises stress in the vicinity of a non-recessed and a recessed trace. For the non-recessed trace, each of the interior corners of the PECVD silicon dioxide/silicon nitride layers show much higher stress than the surrounding areas. In the recessed trace, these stress concentrations are absent, however the stress does change slightly (higher for silicon dioxide, lower for silicon nitride) over the metal trace, most likely due to the change in thickness of thermal silicon dioxide. Some high stresses are also present in the lowermost SiN_x insulation layer at the boundary of the metal trace.

Figure 5.

Von Mises stress near a non-recessed (top) and a recessed trace (bottom), with geometry similar to the actual device profiles shown in figures 3(f) and (g). For the non-recessed trace, the interior corners of the PECVD silicon dioxide/silicon nitride layers (arrow) show higher stress than the surrounding areas.

3.3. Electrochemical validation

Finally, it was important to determine the potential impact of recessed traces on initial device performance. Electrochemical impedance spectroscopy (figure 6(a)) and cyclic voltammetry (figure 6(b)) showed very little difference between three representative equally-sized (2000 μm²) electrode sites each on a non-recessed and a recessed device. The average impedances at 1 kHz were 14.6 ± 0.6 kΩ for non-recessed sites and 14.1 ± 0.5 kΩ for recessed sites. The average CSC_cs were 14.7 ± 0.3 mC cm⁻² for non-recessed sites and 15.5 ± 0.3 mC cm⁻² for recessed sites. The differences were not statistically significant. The stimulation capabilities of the two types of electrodes were also very similar and were stable before and after one million pulses, as evidenced by the close similarity of representative voltage transients shown in figure 6(c). This is considered a form of active testing of a device as opposed to passive soaking (which takes a much longer time). The recording capability of recessed electrodes was tested by performing differential recording of pseudo extracellular voltage signals in PBS (figure 2). The microelectrode was able to detect high signal-to-noise ratio signals (figure 6(d)) and clusters of spikes after sorting (figure 6(e)).

Figure 6.

Electrochemical validation of a recessed device vs. a non-recessed device. (a) Impedance spectra were similar both in magnitude and phase angle shift. (b) Cyclic voltammograms were also similar, with common iridium-oxide-specific peaks. (c) After one million stimulation pulses, the voltage transients were similar to each other and to their original shape. (d) A high signal-to-noise ratio pseudo extracellular recording was detected by the recessed device in PBS. (e) A sample unit cluster obtained using Plexon Offline Sorter™.

4. Discussion

Topography is formed when metal traces are patterned on a polished wafer surface, hence the vast majority of conventional microelectrode devices have some degree of raised topography. Here, we have demonstrated a simple technique that allows traces to be recessed (buried) within a substrate, greatly reducing the size of that topography. The technique does not require any additional masks, alignment, or polishing steps, only dry etching steps, and does not interfere with the functionality of the device. Our technique is potentially applicable to other neural microelectrode designs where the conducting traces are sandwiched between two insulating layers. Recessing the electrode sites (not just the traces) could have the additional benefit of reducing the edge effect of charge accumulation during stimulation.

We believe that the degree of flatness achieved with this technique is more than adequate for the purposes of reducing stress concentrations. Insulation layers are typically at least 1 μm thick, so 15 nm represents only 1% of their total thickness. The remaining source of error is mainly due to the variability of the etch step. If better planarity is desired, the technique could be improved by measuring the depth of the trench after the etch and then making fine adjustments to the deposition thickness. Alternatively, a slow oxide etch, metal etch, or argon etch could be used to make corrections after metal deposition.

One potential limitation of this technique is the presence of fences towards the edges of the wafer. Perfect, fence-free traces could only be found in the center 2″ of the 4″ wafer. It is possible that these imperfections (which are much smaller than the height of the traces) have no effect on chronic reliability, but until this can be shown, we plan to adopt the conservative strategy of only using devices from the center 2” of the wafer. If it is shown they do have an effect, it would be desirable to explore techniques to mitigate the formation of fences. Increasing the throw distance (distance between metal crucible and wafer) would help by making the angle of deposition more vertical. Preserving more photoresist undercut would also help, though this would also create a slightly larger gap between metal and trench sidewall. Another tactic would be to try to remove the fences after they form. We attempted this by swabbing and sonicating in acetone and using an argon RIE, but these were only partly successful. High-pressure solvent cleaning or aggressive scrubbing could be explored.

An alternative to our technique is chemical-mechanical polishing (CMP), which is the industry standard for planarization (used for example in the popular dual-Damascene process). Our technique’s advantages over CMP are its simplicity and its availability to cleanrooms lacking CMP equipment. To accomplish the same effect using CMP, insulation would need to be deposited at least as thick as the trace. Then, CMP would remove material until the raised topographies over the traces were eroded. Finally, additional insulation would be deposited on top of the planar surface.

Finite element modeling showed that non-recessed traces are likely to create intrinsic stress concentrations that recessed traces do not. Intrinsic stresses are formed due to the different coefficients of thermal expansion of different materials when they are deposited at high temperatures then cooled to room temperature. Our findings add new support to Schmitt et al’s hypothesis that reduced concentrations of intrinsic stresses were responsible for the improved performance of recessed traces in their study [32]. Our model’s accuracy could be improved with more accurate geometry and more precise estimates of intrinsic stresses. We did not model extrinsic stresses (stresses due to externally-applied forces) because this aspect was already explored in the study by Kozai et al, which showed that raised, non-recessed traces tended to concentrate extrinsic stresses [19].

In recent decades, a wide variety of polymer-based neural electrodes have been developed [38–44]. The appeal of polymers is that their mechanical properties can be orders of magnitude softer than silicon or metals, reducing the device’s ‘mechanical mismatch’ with neural tissue. It is unclear at this point whether stress concentrations occur as a result of topography in these probes, or whether they contribute to device failure, but if they do, our technique could be adapted for polymer probes as well.

The array of electrochemical tests conducted in this study, including impedance spectoscopy, cyclic voltammetry, and voltage transient recording, showed that the properties of recessed devices closely matched those of non-recessed devices and were stable after million-cycle pulsing. One million cycles at the 400 Hz stimulation frequency translates to approximately 40 min of continuous stimulation. If there is a faulty feature in the device, this is long enough to detect failure. For example, one may observe an extending polarization in the voltage transient, tilting in the CV curve, or drastically lower impedance values by the end of the test. None of these were seen in this study. To put this in context, for applications where the electrodes are only used for passive neural recording, this test would be deemed rigorous. For high-demand stimulation applications such as deep brain stimulation, which may require 24/7 stimulation, this duration would be rather short. For other need-based or closed-loop stimulation applications where only limited durations of stimulation per day suffice, such as bladder micturition, this may be adequate for days to weeks of operation. Our future efforts may involve higher numbers of cycles of pulsing or pulsing while soaking at high temperatures. For now, the obtained properties are in agreement with previously successful in vivo studies using microelectrodes of similar design [12, 13, 45]. Recording of pseudo neural waveforms in PBS was also encouraging. While this in vitro test does not completely duplicate the in vivo condition, we believe it is an appropriate validation of recording ability. (We obtained a similar result with a commercial Plexon sound file (not shown)). Together, these data show that recessed devices are likely to perform at least as well as non-recessed devices in vivo.

The next step in this work will be to test whether our recessed traces withstand degradation better than non-recessed traces in accelerated soak tests and in vivo. If they do, our technique represents a simple and broadly-applicable approach for improving the reliability of neural interfaces and MEMS in general [46].

5. Conclusion

A technique for recessing the conducting traces of a neural microelectrode within the substrate in order to reduce stress concentrations was described in detail. The technique requires no extra masks and allows the insulation layers to be flat within approximately 15 nm. The improved flatness is expected to increase the chronic reliability of neural electrodes, a hypothesis that will be tested in future in vivo studies. In this study, in vitro electrochemical tests confirmed that recessed traces had robust recording and stimulation capabilities that were comparable to an established non-recessed device design.