A 6-Transistor Ultra-Low Power CMOS Voltage Reference with 0.02%/V Line Sensitivity

Abstract

This work presents a technique for design of ultra-low power (ULP) CMOS voltage references achieving extremely low line sensitivity while maintaining state-of-the-art temperature insensitivity through the use of a 6-transistor (6T) structure. The proposed technique demonstrates good performance in sub-100 nm CMOS technologies. The 65-nm CMOS implementation occupies only 840 μm² of area and consumes 28.6 pA from a 0.5 V supply. Measurements from 6 samples from the same wafer show an average line sensitivity of 0.02 %/V, a 10X improvement over previous 65 nm implementations, and an average temperature coefficient of 99.2 ppm/°C.

I. Introduction

Increasing interest in ultra-low power (ULP) sensor nodes motivates design of picowatt voltage references with process, voltage, and temperature (PVT) invariance. As ULP nodes are often powered using energy harvesting, the references must (a) accommodate a wide range of supply voltages, and (b) operate from low supply voltages [1] [2]. Finally, the low cost of ULP nodes and targeted sub-mm dimensions imply that PVT invariance must be achieved with small silicon area.

State-of-the-art ULP voltage references can be categorized broadly into (a) band-gap references [3], (b) hybrid designs [4], and (c) integrated CMOS references [5]–[7]. The high VDD and relatively high power consumption of band-gap references render them unsuitable for energy-harvested applications. While hybrid designs provide temperature and process invariance, they also require high supply voltages, are typically high area and are not supported in many CMOS technology nodes. Fully-integrated CMOS references can provide low power consumption and low cost due to integration with the sensor node. However, it is challenging to ensure acceptable performance without extensive calibration. This challenge is exacerbated in sub-100-nm CMOS technology nodes due to the impact of supply variation on the nominal value and temperature characteristic of the voltage reference. Notably, ULP sensor node technology choice can be based on high frequency/digital circuit performance, and therefore improved voltage-reference design approaches in sub-100-nm technology nodes are attractive for several applications. Fig. 1 summarizes the existing state-of-the-art in voltage references across power and technology, highlighting the need for low-power voltage references in advanced CMOS nodes.

Fig. 1.

Summary of current state-of-the-art voltage references; metric used is Temperature Coefficient (ppm/°C) × Line Sensitivity (%/V).

In this work, a 6-transistor (6T) ULP CMOS voltage reference in 65 nm technology is presented that improves supply variation without compromising performance across temperature. The proposed architecture also addresses the challenge of high supply variation in short-channel-length technologies. This design achieves an average line sensitivity of 0.02%/V while maintaining an average temperature-coefficient (TC) of 99.2 ppm/°C and consuming only 14.3 pW from a 0.5 V supply in 65-nm CMOS. The proposed architecture and its applicability for design in sub-100-nm CMOS nodes are described in Sec. II; the specific 65-nm CMOS implementation is detailed in Sec. III; measurement results are summarized in Sec. IV; and, summary and future work are discussed in Sec. V.

II. 6T Voltage Reference Design

CMOS voltage references using low transistor count promise low power consumption and small area. Four-transistor (4T) and two-transistor (2T) voltage references are demonstrated in [6]. Fig. 2(a) shows the standalone 2T voltage reference, where the careful selection of $\frac{W_1/L_1}{W_2/L_2}$ ensures low variance across temperature with 89ppm/°C to 118ppm/°C TC for 240 pW power consumption in the 65-nm CMOS implementation of [6]. The design is extended to a 4T structure to achieve a higher reference voltage (~0.5V) with slight degradation in TC. While the 2T design addresses varying temperature, the line sensitivity exceeds 0.3 %/V, limiting its use in ULP nodes with varying supply voltage. This is particularly important in advanced nodes, where the line sensitivity of a 2T structure goes from 0.3 %/V to >12.8 %/V from 65-nm CMOS to 22-nm FinFET implementations.

Fig. 2.

(a) 2T topology. (b) Schematic of proposed 6T voltage reference. Reference voltage outputs are denoted as V_REF,2T and V_REF,6T for 2T and 6T respectively.

The temperature and voltage variance can be concurrently addressed in the proposed 6T circuit shown in Fig. 2(b), which uses a coarse voltage reference (V_REFA,6T) set by M₃, M₄, M₅, and M₆ as the supply for the 2T structure, M₁ and M₂.

Temperature Variation:

In order to maintain the desired TC at both V_REFA and V_REF in the 6T design, the sizing of M₆ must change to account for the change in load at V_REFA,6T. For the individual optimization of V_REFA, I₃ = I₄. However, with the addition of M₁ and M₂ in the 6T reference, W₅ must be increased or W₆ must be decreased to account for the additional current I₅. Fig. 3(a) compares the simulated V_REF,2T (Fig. 2(a)) and V_REF,6T (Fig. 2(b)) across temperature at the nominal process corner with 0.7V VDD. Fig. 3(b) shows how the TC changes across VDD for the 2T and 6T case. While there is a shallow optimum where the standalone 2T is marginally better than the 6T structure for temperature, at higher VDD values the 6T structure gives a consistently better TC.

Fig. 3.

(a) Simulated effect of V_REFA,6T on V_REF,6T with properly sized M₅ and M₆ across temperature at 0.7V. Note the small change in temperature characteristic due to V_REFA,6T. This change can be observed in (b) which presents simulated TC across VDD.

Supply Variation:

The supply voltage dependence of V_REF,2T and V_REF,6T topologies can be reduced to the first order by maintaining a constant I_D,M1 and I_D,M2. For a given I_D, the gate-source voltage, V_GS and hence V_REF can be related using the sub-threshold transistor model (assuming V_DS >> V_T) as

$$I_{DS}=\mu C_{OX}\frac{W}{L}\left(m-1\right)V_T^{2}e\frac{V_{GS}-V_{TH}}{m{V}_T}$$ (1)

which promises VDD independence to the first order. However, V_TH is a function of drain voltage. Fig. 4(a) shows the normalized variation of V_TH,M1 in 65-nm CMOS. As shown in Fig. 4(b), the V_TH,M1 variation translates to a V_REF,2T variation of 0.15 %/V. In the 6T case, the buffered voltage provided by V_REFA,6T leads to a nearly constant V_DS,M1,6T across variation in VDD. The reduction in V_TH,M1,6T variation improves the simulated line sensitivity by > 10x to 0.01 %/V.

Fig. 4.

(a) Simulated variation of V_THM1 across VDD for 2T and 6T, (b) resulting variation in V_REF for 2T and 6T demonstrates improved line sensitivity for 6T.

A. Extension to 22-nm FinFET

In addition to improving line sensitivity, the 6T structure can improve the TC for voltage references in deep submicron technologies by using the V_REFA,6T temperature characteristic to compensate for limitations in optimization of the 2T temperature characteristic. V_REFA,6T can have a complementary to absolute temperature (CTAT) or a proportional to absolute temperature (PTAT) characteristic based on the ratios $\frac{W_3}{W_4}$ and $\frac{W_5}{W_6}$, providing an additional degree of design freedom to achieve low TC for the output V_REF,6T. This is particularly beneficial in technologies, such as 22 nm, where manufacturability limitations constrain channel length and width to discrete steps.

Fig 5 demonstrates this approach through simulation in a 22-nm FinFET node. M₃, M₄, M₅ and M₆ can be selected are sized to achieve PTAT V_REF,A,6T, as shown in Fig 5(a). This compensates CTAT behavior from M₁,M₂ (blue in Fig 5(b)) leading to low TC for V_REFA,6T (orange in Fig 5(b)). The channel length used in this design is 160 nm, which causes extreme short channel effects, resulting in line sensitivities of >10 %/V for a 2T reference. However, this high VDD sensitivity also enables the approach shown in Fig 5 as more of the temperature characteristic of V_REFA,6T is carried through to V_REF,6T. In simulation, the 6T structure improves the optimal TC by more than 2X to 18ppm/°C as compared to an optimized standalone 2T structure, while improving the line sensitivity by 28X to 0.45 %/V.

Fig. 5.

In 22-nm FinFET a PTAT V_REFA,6T, shown in (a), is used to compensate a CTAT standalone 2T (blue) improving the TC for the 6T structure (orange) as shown in (b).

III. 65-NM CMOS DESIGN METHODOLOGY

To demonstrate the improvements that this design offers for sub-100-nm CMOS, a 6T implementation was designed and fabricated in 65-nm CMOS. In this implementation, TC cancellation for M₁ and M₂ can be achieved by appropriate sizing without creating additional compensation through intentional variation of V_REFA,6T. Therefore, M₃, M₄, M₅ and M₆ are optimized for V_REFA,6T to have a flat TC. Widths were first optimized separately for the set of M₃,M₄,M₅,M₆, and set of M₁, M₂, to achieve low TC leading to W₁ = 2 μm, W₂ = 2.4, μm, W₃ = 4 μm, W₄ = 2 μm, W₅ = 2 μm and W₆ = 1.6 μm. Device lengths were fixed at 20 μm, allowing for low W/L ratios leading to ultra-low power consumption.

Fig. 3(b) shows the simulated TC across VDD. It can be noted that the optimal VDD for the 2T reference is 0.7 V. While 0.7 V is optimal, it sets a high minimum value for VDD. In this design, V_REFA,6T was chosen to allow a VDD as low as 0.5 V, slightly degrading the TC in order to improve line sensitivity at low VDD values. This optimization resulted in reducing the size of W₆ from 2 μm to 0.8 μm.

IV. Measurement Results

The proposed 6-Transistor voltage reference was fabricated in a 65-nm CMOS process. Fig. 6 shows a micrograph of the fabricated design, which occupies 840 μm² and consumes, on average, 28.6pA from a 0.5 V supply at 25 °C. Fig. 7(a,b) shows the current consumption of the 6T reference across VDD and temperature respectively. The mean reference value is 257.5 mV with a σ/μ of 0.3 % across 6 samples measured at 0.5 V, 25 °C. Measurements were performed using a Keithley 4200-SCS semiconductor characterization system with an input impedance greater than 10 T Ω. This measurement setup allowed for a measurement accuracy of 130 μV with ≤10 μV precision. In order to reduce supply noise, a battery was used as VDD for all measurements. Fig. 8 shows the temperature characteristic of 6 samples measured from 0 °C to 100 °C demonstrating an average temperature coefficient of 99.2ppm/°C; the minimum and maximum TC are 78.4ppm/°C and 113.5 ppm/°C, respectively. Fig. 9 shows the measured line sensitivity, which ranges from 0.010 %/V to 0.025 %/V with a mean line sensitivity of 0.02 %/V for a VDD range of 0.5 V to 1.8 V.

Fig. 6.

Chip micrograph in 65-nm CMOS.

Fig. 7.

Measured power consumption across (a) voltage (at 25 °C) and (b) temperature (at 0.5 V).

Fig. 8.

Measured V_REF,6T, across temperature for 6 different samples at 0.5V.

Fig. 9.

Measured V_REF,6T, across voltage for 6 different samples at 25 °C

Fig. 10 shows a comparison with previously published designs. This work shows comparable with state-of-the-art TC for 65-nm CMOS implementations, while improving sensitivity for 65-nm CMOS by more than 15X. A mean line sensitivity of 0.02 %/V shows state-of-the-art line sensitivity while consuming 10X less power and occupying 5X less area than previously reported ULP voltage references with equal line sensitivity [4].

Fig. 10.

Comparison with prior state-of-the-art untrimmed ULP voltage references.

V. Conclusion

This work proposes a 6-transistor ULP voltage reference to provide extremely low (0.02%/V) line sensitivity while maintaining state-of-the-art temperature variation for ULP 65-nm CMOS (78.35 ppm/°C to 113.49 ppm/°C). An extension is shown to applications in sub-65 nm technologies, where fixed low channel lengths and fixed-interval device sizing limit design optimizations in previous works. The proposed 6T voltage reference supply insensitivity extends the feasibility of ULP voltage references to wirelessly powered and battery-less applications, where high supply noise and wide-ranging supply values are expected.