Reliable multilevel memristive neuromorphic devices based on amorphous matrix via quasi-1D filament confinement and buffer layer

Abstract

Conductive-bridging random access memory (CBRAM) has garnered attention as a building block of non–von Neumann architectures because of scalability and parallel processing on the crossbar array. To integrate CBRAM into the back-end-of-line (BEOL) process, amorphous switching materials have been investigated for practical usage. However, both the inherent randomness of filaments and disorders of amorphous material lead to poor reliability. In this study, a highly reliable nanoporous–defective bottom layer (NP–DBL) structure based on amorphous TiO₂ is demonstrated (Ag/a-TiO₂/a-TiO_x/p-Si). The stoichiometries of DBL and the pore size can be manipulated to achieve the analog conductance updates and multilevel conductance by 300 states with 1.3% variation, and 10 levels, respectively. Compared with nonporous TiO₂ CBRAM, endurance, retention, and uniformity can be improved by 10⁶ pulses, 28 days at 85°C, and 6.7 times, respectively. These results suggest even amorphous-based systems, elaborately tuned structural variables, can help design more reliable CBRAMs.

The structural approach enables reliable multilevel memristor devices for neuromorphic computing system development.

INTRODUCTION

Various resistance-switching memristors have been demonstrated as nonvolatile memory and bioinspired neuromorphic applications (1–4). There are diverse mechanisms that explain a change of device resistance (5–7). A filamentary switching mechanism, which involves the formation and disruption of a nanoscale conductive filament (CF), has been extensively studied. Oxide-based resistive random access memory (RRAM) and conductive-bridging random access memory (CBRAM) are two representative examples operated via filamentary switching; however, varying resistances originate from anion vacancies in RRAM, while they do in active metal cations [e.g., copper (Cu) or silver (Ag)] in CBRAM (8, 9). Therefore, they exhibit different characteristics such as the on/off current ratio, endurance, retention, reliability, and switching speed (10).

CBRAM’s strengths compared with RRAM are large on/off ratio, fast switching speed, and low power consumption, which are essential characteristics for neuromorphic applications, owing to the high mobility of metal cations compared with oxygen anions (11, 12). Thus, CBRAM is an attractive candidate for a biomimicking artificial synapse with tunable conductance (13). However, despite these advantages, CBRAM has reliability issues that prevent its integration into a large-scale array (14, 15) and the formation of high-density features required to reproduce the high connectivity characteristic of the biological synapse system (16). For instance, the set/reset voltage is highly variable because of stochastic metal cation transport through an amorphous three-dimensional (3D) switching medium. In addition, the endurance and retention of CBRAM are generally worse than those of oxide-based RRAM because of direct (metal-metal) contact with the active metal electrode [e.g., copper (Cu) or silver (Ag)] and an inert counter electrode. This is prone to irreversible breakdown, known as set stuck effect (17, 18). Moreover, continuous metal filament breaks up into a sphere-like shape as time goes on because of the high surface tension between active metal and switching medium known as “Rayleigh instability” (19–21).

To solve these problems in CBRAM, several researchers have explored how oxide-based RRAM has made meaningful progress to enhance device variation, endurance, and retention from both material and structural perspectives. In general, oxide-based RRAM can enhance reliability through localized switching, which reduces the uncontrollable 3D random filament growth and rupture process (12, 22, 23). Similarly, recent studies have shown the remarkable stability of CBRAM using confined filaments through various methods (4, 24–26). Previously, the 1D channel formation by using intrinsic dislocation of epitaxially grown SiGe on Si exhibited an exceptionally low variation, and it can be used as the confined pathway of CF to improve the CBRAM performance, which is known as epitaxial random access memory (epiRAM) (4). However, epitaxial layer growth requires a high temperature and epitaxial seed layer, which is difficult to apply to the back end of line (BEOL) process to integrate the EpiRAM on the complementary metal-oxide semiconductor (CMOS) circuit vertically for high-bandwidth communication. Therefore, an amorphous switching medium is highly recommended for further development of CBRAM-based non–von Neumann architectures and neuromorphic systems. Another approach is that the reliability including endurance and retention can be enhanced by introducing an additional thin layer that acts as a buffer layer to regulate filament overgrowth (27–32). Although there are positive effects by preventing set stuck effect, most of the devices still have a large variation. In table S1, detailed characteristics are compared.

In this study, we propose a highly reliable device structure that has approximately 10-nm-diameter nanopores with a sub–10 nm defective bottom layer (DBL) (see fig. S1 for the detailed process). The pores were formed simultaneously with the oxidation process of Ti and facilitated localized filament growth via 1D pores to achieve highly reliable switching in both dc I-V characteristics and pulse measurement with stable retention. Consequently, the CF is confined in a 1D predefined path and exhibits stable multilevel memory properties with a high on/off ratio (>10³). This pore-assisted switching was identified as having low variation, and it was further verified by observing the retention properties as an aspect ratio of the pore size. Furthermore, the thin and defective layer beneath the pore successfully improved the device endurance by efficiently regulating filament overgrowth with on/off ratio tunability. Thus, this first attempt to accommodate both confined filaments and a thin DBL with BEOL compatibility will pave the way for the optimal amorphous-based CBRAM structure to construct a highly reliable large-scale array.

RESULTS

Synthesis and structural characteristics of anodic TiO₂

Anodization is an oxidation method that uses electrochemical reactions, and it has garnered notable attention because of its versatility and convenience (33, 34). When the metal film is anodized, the quality of the oxide can be easily controlled by various parameters such as the type of electrolyte, temperature, potential, and time. In our experiment, we adopted an ethylene glycol (EG)–based electrolyte and Ti thin film to construct nanoporous (NP) TiO₂ by adding NH₄F [0.3 weight % (wt %)] as an etching agent to the solution (see the details in Materials and Methods).

As shown in Fig. 1A, the three distinctive states (I, II, and III) based on the stoichiometries of the bottom layer are synthesized by different anodization times with almost identical pore shapes. These were started with a 40-nm-thick Ti film deposited on the bottom electrode (BE) and went through common steps but ended at different times during the anodization process. These steps were known as “oxidation,” “pore formation,” and “metal thinning.” A schematic of the changes and detailed explanation during the process is precisely described in fig. S1. These figures and sequences were confirmed by previous studies and clarified by the repetitive I-t curve of the potentiostatic (constant voltage) anodization process in Fig. 1B (35–37). At the beginning stage of anodization regarded as oxidation, the total thickness increased, as some of the Ti thin films were oxidized to the initial TiO₂ layer from the surface under an applied electric field between the anode and cathode; therefore, the current was substantially decreased as shown in Fig. 1B. Next, the current increased from the etching process of tiny dimples on the surface of TiO₂ by the F⁻ ions in the electrolyte. The etching process was strengthened near the tiny dimples because the electric field between the electrolyte and Ti was stronger across the pores (33, 38). As shown in Fig. 1C, tiny dimples become an approximately 10-nm-sized hollow NP structure. In this process, the pore size is mainly affected by the amplitude of the anodization voltage, because a large number of fluorine anions are attracted by a high magnitude of anodizing voltage to the surface of the sample and contribute to the etch process to widen pore size (33). In terms of pore density, it was estimated to be approximately 3 × 10¹¹/cm², which suggested that the device can be scaled down to sub–30 nm dimensions even considering the nonuniform distribution of pores (see fig. S2 a for detailed scalability analysis). When the bottom of the tiny pores is etched, the oxygen anions can react with Ti under the initial TiO₂. Therefore, the oxidation and the etching process occur at the same time and make the pore deeper. To be more specific, oxidation of Ti to TiO₂ (decreases current) and etching of TiO₂ by fluoride anions (increases current) proceed in electrochemical equilibrium. As Ti metal consumes, the current finally starts decreasing again. When the remaining Ti was completely consumed, the anodizing process slowed down and eventually stopped because no material can supply currents or electrons to keep the reaction, which was essential for the electrochemical anodizing process.

Fig. 1. Structural characteristics of anodic TiO₂ memristor with NP-DBL.

(A) Schematics of the three states of nanoporous–defective bottom layer (NP-DBL) (I, II, and III). Each state was divided by the amount of oxygen vacancies in the DBL. (B) Current-time curve of anodic NP TiO₂. Three points are selected for verifying the effect of anodizing time (I, II, and III). (C) Plain-view SEM image of pore. (D) Cross-sectional TEM image of the close-ended porous structure showing clear NP and DBL. DBL corresponds to the barrier layer of the anodization process. (E) TOF-SIMS depth profiles of O (oxygen) element for three anodization states (I, II, and III). The x axis of all samples is converted to a normalized sputter time divided by each specific time in which the BE peak appears. a.u., arbitrary units.

Last, the anodization process ends with a close-ended structure, as shown in Fig. 1D, and there is an oxide layer known as the “barrier layer” (39, 40). The properties of the remaining bottom layer (barrier layer) between the pore and BE can be controlled by modifying the anodization time. The three bottom layers [defective state (I), intermediate state (II), and stoichiometric state (III)] formed under the same conditions, except anodization time, were extensively scrutinized using electron microscopies [scanning electron microscopy (SEM) and transmission electron microscopy (TEM)] and time-of-flight secondary ion mass spectroscopy (TOF-SIMS) analysis. TOF-SIMS analysis characterizes the distribution and amount of oxygen in the DBL, a yellow-colored shallow region, as depicted in Fig. 1E. As the reaction speed slowed as it approached the BE, there was a deficiency in the degree of oxidation along the vertical direction, which can be identified by the transparent gradient of the oxygen intensity of I and II in the bottom layer region. This gradient was mitigated by a sufficient anodization time (I→II→III). In particular, for sample III, which had the longest anodizing time, we found that the oxygen content was almost similar to typical radio frequency (RF) sputtered TiO₂ near the BE (see fig. S3). Briefly, a defective (high content of oxygen vacancy) TiO_x bottom layer was formed if there was only a short time after the metal “thinning” stage of the I-t curve, but stoichiometric TiO₂ was formed by a sufficiently long anodization time. Thus, the shape of the pores and stoichiometries of the bottom layer can be easily engineered using diverse combinations of various anodizing parameters. These advantages enable the fabrication of reliable resistance-switching devices through structural modifications in the switching medium.

Performance of memristive anodic NP-DBL device

Figure 1A and fig. S4A show a cross-sectional image of a two-terminal memristor stack. We used silver (Ag) as an active top electrode (TE), which formed a resistance-switching metal filament, and heavily doped p-type silicon (<0.005 ohm·cm) as a common BE. By anodizing 40-nm-thick Ti until the defective state (I), the red circle point of the universal I-t curve in Fig. 1B, a 65-nm-thick NP TiO₂ with a DBL was formed as a switching medium. Eventually, the Ag(TE)/TiO₂(NP)/TiO_x(DBL)/p-Si(BE) bilayer switching medium was sandwiched between the two electrodes. It is noteworthy that, currently, p-Si is used as a BE, but fig. S4B shows that a similar shape of pores can be formed with the replacement of the inert Pd metal BE.

To demonstrate that the low variation property originated from the vertically formed nanopores, we compared an anodic TiO₂ NP-DBL memristor with a typical RF-sputtered TiO₂ memristor. Except for the switching medium, all conditions, such as the stack and thickness of the device, were identical. The electroforming voltage of the sputtered device, the voltage required to form the conductive path first, is ~1.8 times higher than that of the NP-DBL device (see fig. S5). These data implied that surface diffusion facilitated the migration of Ag ions through a 1D path rather than the bulk diffusion. In other words, the diffusivity of Ag along with the pores was enhanced compared to the bulk diffusivity (25, 41, 42). After the electroforming step, 90 dc sweeps were executed to compare the temporal variations of the devices. Notably, in dc operation, not only does the NP-DBL device exhibit remarkably stable resistive switching over 90 cycles with slight variation (σ/μ), 2.7%, but it also has a uniform resistance in both high-resistance state (HRS) and low-resistance state (LRS) compared to the sputtered device (Fig. 2B and fig. S7). Unlike the NP-DBL device, the variation (σ/μ) deteriorated at 18.2% over 90 cycles for sputtered TiO₂ (fig. S6). These are because the Ag ions preferentially migrate with the confinement effect via predefined pores rather than stochastic bulk diffusion, which is similar to the molecular dynamics of Ag diffusion in amorphous Al₂O₃ with pores (25). To support our claim, we made a comparison about device performance with other nanopore-based CBRAMs including a variation of the devices in table S2. The identical HRS and LRS in the NP-DBL device imply that the formation and rupture of the CF during consecutive cycles are highly uniform. The temporal uniformity originates from the finely formed pores, as shown in the TEM and SEM images (Fig. 1D and fig. S4, respectively). On the basis of the improved uniformity, our NP-DBL device has a large readable margin (on/off ratio) of approximately 270, whereas the sputtered device has a small margin of approximately 44.4 (fig. S7). Moreover, it is important to have a low conductance update variation with any potentiation and depression pulses applied to accomplish a practical array operation. Therefore, 300 potentiation pulses and 300 depression pulses were applied 100 times, unprecedentedly low at 1.29% (σ/μ) (see Fig. 2C).

Fig. 2. Electrical characteristics of anodic TiO₂ memristor device with NP.

(A) I-V characteristic of NP-DBL device in semilogarithmic scale. The numbers and direction indicate switching sequence and polarity. Inset: Positive voltage regime of dc I-V curve in linear scale. (B) Distribution of temporal set voltage for 90 I-V curves. The set voltage was measured where the current reached 0.6 mA during the set process. Inset: Histogram of set voltage distribution. (C) Low variation conductance update curve depicted by average and SD of 300 potentiation/300 depression pulse trains for 100 cycles (read pulse: 0.8 V, 0.8 ms). (D) Stable retention performance (read pulse: 1 V, 1 ms) in on-state [low-resistance state (LRS)] over 9 hours at 125°C. (E) Retention property (read pulse: 1 V, 1 ms) for 600 s with various compliance currents of NP-DBL device. The bottom row represents high-resistance state (HRS). (F) Vanishing nonlinearity with increasing compliance current (0.2, 0.4, 0.5, 0.7, 0.8, 0.9, and 1 mA). Inset: Measured nonlinearity at each compliance current. Nonlinearity is measured as the ratio of current values at the read voltage (1 V) to the current values at half of the read voltage (0.5 V). (G) Consecutive 32 analog pulse cycles (19,200 pulses) from the entire endurance test (fig. S16).

Although NP-DBL demonstrated stable analog conductance updates, it still has nonlinear response to the linear pulse number. To minimize the nonlinearity factor, we inspected the relation between the on/off ratio and linearity by increasing the number of potentiation/depression pulses from 50 to 1500. As a result, the nonlinearity factor can be improved from 2.79 to 1.64 based on the potentiation part, but sacrificing the on/off ratio from 4.10 to 1.61, and analog conductance updates curves and extracted nonlinearity factors are provided in fig. S8 (43). In the case of spatial variation among unit cells, the device-to-device variation was somewhat higher than the cycle-to-cycle variation (see fig. S9). We believe the larger spatial variation might be related to variations in the anodization process. The electric field driving the electrochemical reactions depended on the distance of each cell from the counter electrode, and it was differed by cell to cell because of the rod shape of the Pt cathode. If the distance is kept constant across entire cells to have an identical electric field, then it is expected that reduced spatial variation might be accomplished by having more uniform pores and the same degree of anodization. In conclusion, stable cycle-to-cycle electrical measurement results in both the dc and ac modes support the confinement effect of the filament through vertically formed pores rather than inherent stochastic behavior.

For typical CBRAMs, the growth of CFs in the closely packed bulk switching medium provoked mechanical stress in a switching medium and naturally decayed into an HRS by the relaxation of stress (21, 44). Therefore, it was predicted that retention might be sacrificed in the general case of CBRAM, and RF sputtered TiO₂ device also retains its data only for 300 s at room temperature (see fig. S10). However, in general, the nanopore-based devices have an improved retention time (see table S2), and especially NP-DBL devices can maintain an LRS at 125°C over 9 hours because of pore-assisted switching, which provides sufficient room for accommodation and stress relaxation of Ag metal atoms. In addition, extrapolation based on the activation energy from the Arrhenius plot estimates that NP-DBL memristor can maintain 10-year retention at temperatures exceeding room temperature (see fig. S11). On the basis of the improved retention, the NP-DBL device can hold several conductance states, which is extremely difficult in other CBRAM devices. There was already sufficient room for minimizing the strain field near the CF and accommodating diverse dimensions of CF by confinement in the pore. Figure 2E represents that at least 10 conductance levels were identified and preserved for 600 s in about 10³ on/off ratio.

Notably, the inset of Fig. 2A represents that the current of the device in the LRS does not show linear dependence to the applied voltage in contrast to the other studies using the heavily doped silicon as a BE (27, 45). Such nonlinear on-state is necessary for constructing a reliable passive crossbar array by minimizing sneak current, which disturbs reading a designated cell. In Fig. 2F, the degree of nonlinearity (I_on at V_read/I_on at V_read/2) increased from 2 (linearity) to 6 as the compliance current decreased from 1 to 0.2 mA. These nonlinearities might come from the defective TiO_x layer beneath the pores, consistent with previous studies about nonlinearity through the TiO_x layer when stacking the oxide layers (7, 46). Currently, approximately five times nonlinearity is not sufficient for constructing a large-scale array (2), but DBL has the potential to improve the nonlinearity by engineering the Schottky barrier (47) and defect chemistry (48). Furthermore, the “set stuck” effect can be eliminated by keeping the two metallic components (Ag and p-Si) apart. As shown in Fig. 2F, the bottom layer effectively controls the overgrowth of the filament, maintaining DBL-induced nonlinearity when the compliance current is kept as low as 600 μA. At high compliance currents greater than 600 μA, which represents a large filament dimension (44), the filament could penetrate into the DBL and have the potential to be directly linked to the BE, resulting in a linear dependency. The effect of DBL was properly demonstrated as high endurance up to 1.2 × 10⁶ pulse trains in which each cycle consisted of 300 potentiation pulses and 300 depression pulses in succession to show the reliable analog operation of the device in fig. S16. In the case of Fig. 2G, consecutive 32 pulse cycles (19,200 pulses) exhibit highly stable and reproducible conductance updates. These remarkable characteristics originate from the device nanopores and the DBL. Each effect was systematically analyzed individually.

Confinement effect of various diameter NP on the device

In most general bulk CBRAMs, the growth of CFs within the switching medium results in asymmetric stress, leading to spontaneous dissolution into clusters, thereby making it difficult to retain great retention and multilevel cell operation (21, 24). In the case of RF sputtered TiO₂ memristor, CF is ruptured in 1500 s abruptly with several conductance drops in fig. S12A. Two conductance drops indicated as curved arrows might originate from partial clusterings, and the filament suddenly breaks off at the end. This phenomenon can be interpreted as a result of atomic clustering to minimize surface energy because of strong surface tension in 3D directions in the bulk (19, 49, 50). However, as shown in Fig. 2 (D and E), our NP-DBL device exhibits excellent retention even with multilevel conductance. As previously mentioned, pores can effectively relieve stress across the switching medium. In addition, depending on the pore size, the retention characteristics differed notably. To verify this phenomenon, we used identical thickness of the devices with various anodization voltages (5, 10, and 15 V) to observe the effect of the diameter or aspect ratio. Figure 3 (A to C) shows magnified surface SEM images of the anodic NP TiO₂ and the inset of the enlarged SEM image of the pores. The pore size, denoted by the yellow dotted line, became more prominent as the anodization voltage increased from 82 to 177 nm². The distributions of the pore sizes in the SEM images are shown in Fig. 3 (D to F). In general, the Gaussian distribution is well followed, and the sizes of the pores gradually increase with the anodization voltage.

Fig. 3. Effects of NP size on the retention of the device.

(A to C) Plain-view SEM images of NPs with varying anodization voltages: 5 (small pore), 10 (intermediate pore), and 15 V (large pore), respectively. Inset: Magnified images and areas. (D to F) Distribution of pore diameter captured by MATLAB code (58, 59). The greater the anodization voltage, the larger the pore diameter. (G) The change of conductance (G_final − G_initial) divided by initial conductance (G_initial) to pore size at various compliance currents. To accelerate measurement, the read pulse is set to −1 V, 10 ms for inducing thermal agitation. (H) Schematic of reduced confinement effect of Ag clusters depending on the pore diameter.

To investigate the relation between the pore size and retention property, we measured the change in conductance (∆G = G_final − G_initial) in 1 hour after the set voltage was applied with a specific compliance current (100, 300, and 900 μA). The change in the conductance was normalized by the initial conductance (G_initial) to observe the tendency of the change regardless of the initial dimension of the filament. It is worth mentioning that our NP-DBL device retained over 10 years of retention at room temperature (see fig. S11); thus, an acceleration test would be required to detect the conductance change in 1 hour. Thus, we set the read voltage to −1 V, the direction of the reset process, rather than 1 V, which was used in another retention test (Fig. 2D), and the read pulse as 10 ms to cause thermal agitation of the filament by joule heating. The higher the compliance current, the thicker the filament and the lower the conductance drop (∆G), as shown in fig. S12B (44, 51). In addition, we found that ∆G/G_initial decreased as the pore diameter increased regardless of the compliance currents in Fig. 3G. In other words, for the same time, the decrease in conductance increased as the pore size increased (as the aspect ratio decreased). Considering the confinement characteristics of the pores, these results can be interpreted as pores, which were excessively wide, providing extra space for the CF to be diffused away if it was far exceeding the dimension of CF. To support the experimental result of Fig. 3G, the temperature-dependent retention measurement was performed from 125° to 185°C, and the retention time was measured with the devices in the cases of small (5 V), intermediate (10 V), and large pore (15 V) sizes to extract activation energies. Figure S13 shows that the retention time is longer when the pore size is small, and extracted activation energies from Arrhenius plots are 1.29, 1.16, and 1.15 eV for small (5 V), intermediate (10 V), and large pore (15 V) sizes, respectively. Moreover, the reduction of retention time at elevated temperatures implies that the dissolution of filament might be caused by the diffusion of Ag atoms (52, 53). These results can support our claim, as shown in Fig. 3G, that extra space from wide pores, larger than the dimension of CF, makes the Ag atoms diffuse away and decrease conductance. On the basis of this, the schematic of this phenomenon is depicted in Fig. 3H. The larger the pore size, the longer the possible diffusion length denoted by the red arrow inside the pore, which exerts a reduced confinement effect on CF. For the porous device, it might be possible to grant tunability in the retention property depending on the type of applications by adjusting the pore size (54, 55). Furthermore, it is meaningful because it has been experimentally shown that resistive switching is due to the pores rather than by the bulk.

Stoichiometries of the DBL on the device

As shown in Fig. 1E, the stoichiometry of the bottom layer varied according to the time parameter of anodization. To identify the most reliable stoichiometries of the bottom layer, we selected points I, II, and III on the I-t curve of Fig. 1B for further investigation. Figure 4 (A to C) shows 15 consecutive I-V curves, depending on the anodization time. Although all conditions except for the anodizing time were identical, as time increased, the conductance of the off-state decreased. These data imply that the stoichiometry of the bottom layer below the pore gradually changed from defective TiO_x (I) to stoichiometric TiO₂ (III), such as the sputter case through the intermediate state (II). These results regarding the oxygen content were in line with the TiO₂ content measured by TOF-SIMS (see fig. S3B). Figure 4D shows that as the anodization time increases from I to III, the TiO₂ content also increases. However, the mean of the off-state conductance, represented by blue circles, notably decreases from 1.4 × 10⁻⁷ to 4.6 × 10⁻¹¹ S. Simultaneously, Fig. 4 (E and F) displays a widened set/reset voltage distribution and a larger variation in the LRS/HRS current level along with an increase in TiO₂ content. This implies that as the layer below the pore (DBL) gradually changes to stoichiometric TiO₂ by extending the anodization time, it acts as a source of stochastic filament formation. In other words, to fully use the confinement effect of the filament by the porous structure, there must be a conductive (defective) layer under the pores.

Fig. 4. Effects of DBL structure on the characteristics of the device.

(A to C) Fifteen consecutive dc sweeps for each state (I, II, and III) on the I-t curve of Fig. 1B. (D) Off-state current and its variation (95% confidence interval for the means of each point) depending on the anodizing time corresponding to the content of TiO₂ near the BE verified by TOF-SIMS depth profiles. Normalized TiO₂ intensity is read at 0.95 of normalized sputter time. (E) Set and reset voltage distribution of (A) to (C). (F) Current variation in LRS and HRS. Current values are read at 0.5 V for LRS and HRS; the whisker and box range signifies minimum to maximum, from 25 to 75% of current values, respectively. (G) Different temperature dependencies of the current depending on compliance current.

Furthermore, as an additional requirement, switching should be conducted with a sufficiently low compliance current. As previously mentioned, the NP-DBL device had nonlinear characteristics in the on-state (LRS) when the compliance current was maintained as low as 600 μA. However, the gradual increase in the compliance current up to 1 mA caused incremental changes to have a linearly dependent I-V curve. As mentioned previously, in the case of a low compliance current, the filament did not penetrate the DBL, and it conducted current indirectly through oxygen vacancies in TiO_x, which has inherent nonlinearity. However, in the case of a high compliance current, the filament could penetrate the DBL and contact the BE, deteriorating device reliability known as set stuck (see fig. S14). These characteristics are supported by the measured current in the LRS from 315 to 346 K, in which high and low compliance current cases are compared in Fig. 4G. At a low compliance current, the conductance increased as the temperature increased, which represented semiconductor-like behavior because of the TiO_x layer (DBL) below the pore. In figure S15, it shows that Mott’s variable range hopping model might be a dominating conduction mechanism because of the linear relationship between ln I and T^−1/4 (56, 57). However, in the case of a high compliance current, the metallic behavior was measured because of a direct connection between the CF and BE.

Moreover, to fully exploit these characteristics even in pulse mode other than the dc mode, the set pulse width should be reduced compared to the reset pulse to minimize the dimension of the filaments. Consequently, we obtained an excellent endurance of more than 10⁶ pulses by regulating the overgrowth of the filament with a sub–10 nm DBL, as shown in fig. S16. Briefly, designing a bottom layer with a shallow defective layer enhances the variation and endurance of the CBRAM.

DISCUSSION

In this study, we first performed a systemic analysis of the pore confinement effect and the stoichiometries of the bottom layer that affect the memristor reliability through anodization. Because of the porous structure in the switching medium, the retention characteristic is enhanced to maintain multilevel conductance, and it can be easily controlled by increasing or decreasing the size of the pore with a low temporal variation. These findings provide compelling evidence for pore-assisted resistance switching, which is the key to reducing unwanted variations. In addition, changing the stoichiometries of the inserted layer below the pore (DBL) facilitates the adjustment of the on/off ratio and endurance despite having a somewhat tradeoff relation with a variation. Moreover, DBL-induced nonlinearity can be used for array operation with the help of self-rectifying behavior. These results suggest a general framework for optimizing device performance by structural modifications depending on diverse applications. Last, this amorphous-based NP-DBL device can be integrated and commercialized using the BEOL process for monolithic 3D integration and constructing non–von Neumann architectures because the entire fabrication process was performed at a low temperature.

MATERIALS AND METHODS

Synthesis of vertically formed NP-DBL TiO₂ arrays

Anodization was carried out on the basis of EG electrolytes (purity >99%; Sigma-Aldrich) with 0.3 wt % NH₄F (powder, purity >98%; Sigma-Aldrich) to the solution. To stabilize the solution, it was stirred at room temperature for at least 3 days to completely dissolve NH₄F with a magnetic bar. Then, to further increase stability, the solution was saturated to the equilibrium state by anodizing thick titanium foil (0.127 mm, purity 99.7%; Sigma-Aldrich) for 6 hours instead of the target sample immediately. After that, actual anodization experiments using 40-nm-thick Ti film deposited on the heavily doped silicon (<0.005 ohm·cm) were conducted using two electrodes by applying a constant voltage range from 5 to 15 V by dc power supply (Maynuo Electronic, M8811). Ti film was suspended with a metal tong and connected with the anode and the platinum rod (counter electrode) with the cathode, respectively. The temperature was also controlled strictly at 20°C by using a 500-ml jacketed beaker connected to the chiller (Huber Minichiller 600).

Memristor device fabrication

The NP-DBL memristive device was fabricated on a commercial dry-oxidized SiO₂ (100 nm)/Si substrate. First of all, Cu (100 nm) was deposited by a thermal evaporator (Korea Vacuum Tech) at the backside of the wafer to prevent backside SiO₂ to be etched when opening the active region with buffered oxide etch (6:1) solution at the next stage. If not, then backside silicon was revealed and unnecessarily reacted during the anodizing process. After that, the active regions that define actual device size was patterned and completely etched by the conventional photolithography method and wet etching process (80 s with a buffered oxide etch), which vary from 3 × 3 to 50 × 50 μm². High-quality Ti (40 nm) was deposited by an electron beam evaporator (Young Hi-Tech) with a pressure of less than 5 × 10⁻⁷ torr. After deposition, the samples were dipped into a copper etchant (Microresist, mr-Rem 700) for a day to get rid of backside copper without damaging on frontside Ti. The next stage was the anodization process with specific voltage and time. To complete the device operated the electrochemical metallization way, active metal Ag (80 nm) and protection metal Pd (30 nm) were deposited in situ and formed by a liftoff process. Sequentially, Ti (10 nm)/Au (100 nm) was deposited for contact pads by a liftoff process. Last, the device was immersed in a buffered oxide etch to get rid of the backside SiO₂ using contact pads as an etching mask. The device was flipped, and Ti (10 nm)/Au (100 nm) was deposited again to form an ohmic contact with heavily doped silicon, which serves as a global BE.

TOF-SIMS analysis

The TOF-SIMS measurements (IONTOF GmbH, TOF-SIMS5) were conducted to identify the composition, stoichiometry, and quantity of components of the DBL, which is near the silicon BE. A Cs⁺ (1-keV) ion gun for sputtering and a primary ion Bi⁺ (30 keV) for analysis were used as the measurement parameter. Considering the thinness of the DBL, the sputter rate was slowed down to get more data points by enlarging the cesium raster area to 500 × 500 μm². It is noteworthy that the sputter rate was calculated and normalized by the appearance of the Si peak on each batch of the sample (BE). Although typical sputter TiO₂ and anodic NP-DBL TiO₂ have the same thickness, the sputter rate differed by approximately 0.4 and 0.8 Å/s, respectively, because of porosity.

Cs-corrected STEM and FESEM

Cs-corrected scanning TEM (STEM) (JEOL, JEM-ARM200F) samples were preprocessed by Focused Ion Beam (FEI, Helios 450 F1) to capture a cross-sectional image of the NP-DBL device. Field-effect SEM (FESEM) (FEI, Magellan 400) was used as both the cross-sectional mode for capturing the shape of pore and the thickness of switching medium as well as the top view mode for the size of pore. The accelerating voltage was set to 5 kV, and the emission current was set to 0.1 nA.

Electrical measurement

To measure the electrical performances of the two-terminal device, the semiconductor parameter analyzer (Keithley 4200A-SCS) was used with the probe station. The top electrode was connected to the source/measure unit through an Au pad for applying a bidirectional voltage, which switches a device set or reset state, and the other terminal (the BE) was connected to a different source/measure unit for ground. The step size of dc sweeping was 0.05 V, and compliance current ranged from 0.2 to 1 mA. In the case of pulse measurement for analog conductance update and retention, data were measured by a customized measurement system using DAQ (National Instruments, USB-6363) and current preamplifier (DL Instruments, Model 1211).

Set/reset voltage definition

We adopted a widely accepted MOS field-effect transistor (MOSFET) threshold voltage definition (constant-current method) in a similar manner. Each compliance current was selected as a standard of constant current, and the first voltage to be reached was the set voltage. However, in the case of measure reset voltage, there was not any compliance current. So, a certain constant-current was selected as a criterion.

Supplementary Materials

This PDF file includes:

Figs. S1 to S16

Tables S1 to S2