A 2.5 V, 2.56 ppm/°C Curvature-Compensated Bandgap Reference for High-Precision Monitoring Applications

Abstract

This work presents a high-precision high-order curvature-compensated bandgap voltage reference (BGR) for battery monitoring applications. The collector currents of bipolar junction transistor (BJT) pairs with different ratios and temperature characteristics can cause greater nonlinearities in ΔV_EB. The proposed circuit additionally introduces high-order curvature compensation in the generation of ΔV_EB, such that it presents high-order temperature effects complementary to V_EB. Fabricated using a 0.18 µm BCD process, the proposed BGR generates a 2.5 V reference voltage with a minimum temperature coefficient of 2.65 ppm/°C in the range of −40 to 125 °C. The minimum line sensitivity is 0.023%/V when supply voltage varies from 4.5 to 5.5 V. The BGR circuit area is 382 × 270 μm², and the BMIC area is 2.8 × 2.8 mm².

1. Introduction

The battery management system (BMS) guarantee the working performance and service life of the battery, and provides new energy management for various applications such as electric vehicles (EVs), energy storage system, and aerospace satellites. Battery monitoring (including voltage, current, temperature, State of Charge (SOC), State of Health (SOH)) is the most basic and core application of the BMS. In typical BMS, it is necessary to constantly evaluate various parameters pertaining to Li-ion battery packs. Monitoring precision is the fundamental guarantee for the reliability and performance of EVs. Figure 1 presents the structure of the proposed BMS.

Figure 1.

The structure of the proposed BMS.

“One master, many slaves” architecture is used for our BMS. The master unit (MU) mainly measures the total voltage, total current, pressure and collision information of the battery pack, calculates the SOC and SOH values, and controls multiple slave units (SUs). The SUs mainly sense the voltage of each battery cell and the temperature of several points in the BMS box. Communication between MU and SUs is through a controller area network (CAN) interface. The battery monitoring integrated circuit (BMIC) is the most significant device used in the BMS slave unit. It connects directly to the battery pack and is designed to monitor multiple cell voltages and temperatures [1,2]. Figure 2 presents the structure of the proposed BMIC.

Figure 2.

The structure of the proposed BMIC.

In order to achieve a high-integration and low-power BMS design as much as possible, a multiplexer structure is used in the BMIC to expand the number of measurable battery cells, and then a high-precision reference circuit and ADC are used to ensure the measurement accuracy. In this structure, the monitoring error mainly comes from the error on the multi-channel sensing channel, the ADC error and the reference error. The accuracy of the voltage reference is the most important criterion that determines the precision of battery monitoring, and it is also an indispensable part in other precision sensors or applications [3,4,5].

Bandgap voltage reference (BGR) is the mainstream temperature- and voltage- insensitive reference used in the field. In high-precision BGR applications, the use of only first-order linear compensation [6,7,8,9,10,11,12] is insufficient for achieving the required temperature coefficient (TC). Effective and simple high-order temperature compensation methods have thus become the norm for optimized circuit design. The curvature-compensation methods reported in the literature [13,14,15,16,17,18,19,20,21,22] further offset the temperature nonlinearity of the emitter–base voltage (V_EB). The topologies in [13] combine opposing curvature characteristics produced by the two BGR cores to achieve the reference voltage. However, even with high-order temperature compensation, the output voltage inevitably drifts owing to factors such as process spread, device aging, and stress. Therefore, the on-chip calibration or trimming structure after production is important to ensure accuracy. The BGR circuits in [14,16] were designed specifically for battery management applications; specifically, the switched-capacitor bandgap reference in [14] and its high-order compensation are achieved by replacing the analog circuitry with a more sophisticated digital correction algorithm [15]. The internal temperature sensor and a lookup table will incur additional cost. The topologies in [16] have piecewise exponential curvature compensation such that good temperature characteristics can be obtained over a wide temperature range, however, the compensation structure is slightly complicated. A zero TC biased MOSFET compensation method is used in [17], but the untrimmed reference voltage is greatly affected by process spread. The circuit in [18] is an ultra-low-power BGR structure, but the TC of the reference voltage is extremely large.

This paper presents a V_EB-based high-order curvature- compensated BGR with a low TC over a temperature range of −40 to 125 °C. The designs in [19] exploit different collector currents to enable logarithmic curvature compensation of ΔV_EB. Based on the idea, a new ΔV_EB generation structure is also proposed. The remainder of this paper is organized as follows. Section 2 illustrates the principle of the proposed BGR, and Section 3 presents the experimental results; the conclusions are presented in Section 4.

2. Principles of the Proposed BGR

2.1. Basic BGR Topologies

The V_EB of a bipolar junction transistor (BJTs) (or V_BE for an NPN transistor) is a complementary-to-absolute-temperature (CTAT) parameter with a TC of about −1.6 mV/°C, and the temperature dependence of V_EB [23] can be expressed as

$${\mathrm{V}}_{\mathrm{E}\mathrm{B}}\left(\mathrm{T}\right)={\mathrm{V}}_{\mathrm{G}0}\left({\mathrm{T}}_{\mathrm{r}}\right)-\underset{\mathrm{linear}}{\underbrace{\left[{\mathrm{V}}_{\mathrm{G}0}\left({\mathrm{T}}_{\mathrm{r}}\right)-{\mathrm{V}}_{\mathrm{E}\mathrm{B}0}\left({\mathrm{T}}_{\mathrm{r}}\right)\right]\mathrm{T}/{\mathrm{T}}_{\mathrm{r}}}}-\underset{\mathrm{nonlinear}}{\underbrace{{\mathrm{V}}_{\mathrm{T}}\left(\mathsf{\eta }-\mathsf{\theta }\right)\ln \left(\mathrm{T}/{\mathrm{T}}_{\mathrm{r}}\right)}},$$ (1)

where V_G0(T_r) is the extrapolated bandgap voltage at a reference temperature T_r, η is a temperature-insensitive parameter [24], and θ is the temperature dependence order of the collector current. Figure 3 shows two widely used BGR structures based on the first-order temperature compensation.

Figure 3.

Schematic of the widely used BGR structures: (a) voltage-mode; (b) current-mode.

The bandgap voltage V_bgr of the voltage-mode BGR [6] in Figure 3a is given by

$${\mathrm{V}}_{\mathrm{b}\mathrm{g}\mathrm{r}}={\mathrm{V}}_{\mathrm{E}\mathrm{B}}+\frac{{\mathrm{R}}_2}{{\mathrm{R}}_1}\Delta {\mathrm{V}}_{\mathrm{E}\mathrm{B}}={\mathrm{V}}_{\mathrm{E}\mathrm{B}}+\frac{{\mathrm{R}}_2}{{\mathrm{R}}_1}\cdot \frac{\mathrm{k}\mathrm{T}}{\mathrm{q}}\ln \left(\mathrm{N}\right),$$ (2)

and the V_bgr of the current-mode BGR [7] in Figure 3b is given as

$${\mathrm{V}}_{\mathrm{b}\mathrm{g}\mathrm{r}}={\mathrm{R}}_3\left(\frac{{\mathrm{V}}_{\mathrm{E}\mathrm{B}}}{{\mathrm{R}}_2}+\frac{\Delta {\mathrm{V}}_{\mathrm{E}\mathrm{B}}}{{\mathrm{R}}_1}\right)=\frac{{\mathrm{R}}_3}{{\mathrm{R}}_2}{\mathrm{V}}_{\mathrm{E}\mathrm{B}}+\frac{{\mathrm{R}}_3}{{\mathrm{R}}_1}\cdot \frac{\mathrm{k}\mathrm{T}}{\mathrm{q}}\ln \left(\mathrm{N}\right),$$ (3)

where V_T = kT/q is the thermal voltage with a TC of about 85 μV/°C, k is the Boltzmann constant, q is the electron charge, and N is the emitter-area ratio of Q₂ to Q₁.

First-order compensation can only decrease the TC of V_ref to about 13 ppm/°C in the presence of nonlinearity [6,7,8,9,10,11,12]. In high-precision battery monitoring, it is necessary to detect voltage changes below 3 mV, and the TC of the reference voltage must be less than or equal to 6 ppm/°C [16]. Therefore, further reduction of the TC requires compensation of the higher-order terms related to Tln(T) in V_EB.

2.2. Insertion of Nonlinear Compensation in ΔV_EB

The current-mode or voltage-mode BGRs primarily use the proportional-to-absolute-temperature (PTAT) characteristic of ΔV_EB, where ΔV_EB is expressed as

$$\Delta {\mathrm{V}}_{\mathrm{E}\mathrm{B}}={\mathrm{V}}_{\mathrm{E}\mathrm{B}1}-{\mathrm{V}}_{\mathrm{E}\mathrm{B}2}=\frac{\mathrm{k}\mathrm{T}}{\mathrm{q}}\ln \left(\mathrm{N}\cdot \frac{{\mathrm{I}}_{\mathrm{c}1}}{{\mathrm{I}}_{\mathrm{c}2}}\right).$$ (4)

If the collector currents I_c1 and I_c2 of the PNP BJT pair (Q₁ and Q₂) have the same temperature characteristics, and ΔV_EB is a more easily controllable linear compensation term. However, if the TC of collector currents are different, then a nonlinear term is introduced into ΔV_EB through the logarithm function.

Therefore, based on the conventional BGR structures in Figure 3, the principle of the curvature-compensated BGR in this work is shown in Figure 4. Based on the original bias current I_x of Q₁ and Q₂, the current I_y is introduced and drawn to form the difference in the collector currents of the BJT pair. I_x and I_y have different temperature characteristics, which lead to an increase in the nonlinearity of ΔV_EB. Hence, ΔV_EB is rewritten as

$$\Delta {\mathrm{V}}_{\mathrm{E}\mathrm{B}}={\mathrm{V}}_{\mathrm{T}}\cdot \ln \left(\mathrm{N}\right)+{\mathrm{V}}_{\mathrm{T}}\cdot \ln \left(\frac{1+{\mathrm{I}}_{\mathrm{y}}/{\mathrm{I}}_{\mathrm{x}}}{1-{\mathrm{I}}_{\mathrm{y}}/{\mathrm{I}}_{\mathrm{x}}}\right).$$ (5)

Figure 4.

Principle of the proposed curvature compensation BGR.

Assuming that I_y/I_x is a temperature-dependent function, i.e., x(T) = I_y/I_x. The natural logarithm has the Maclaurin series

$$\ln \left(1+\mathrm{x}\right)={\left(-1\right)}^{\mathrm{n}+1}{\displaystyle \sum _{\mathrm{n}=1}^{\infty }\frac{{\mathrm{x}}^{\mathrm{n}}}{\mathrm{n}}}=\mathrm{x}-\frac{{\mathrm{x}}^2}{2}+\frac{{\mathrm{x}}^3}{3}\cdots +{\left(-1\right)}^{\mathrm{n}+1}\cdot \frac{{\mathrm{x}}^{\mathrm{n}}}{\mathrm{n}},$$ (6)

which converges for |x| < 1. The logarithmic term in ΔV_EB can thus be calculated as

$$\ln \left(\frac{1+\mathrm{x}}{1-\mathrm{x}}\right)=2\left(\mathrm{x}+\frac{{\mathrm{x}}^3}{3}+\frac{{\mathrm{x}}^5}{5}+\frac{{\mathrm{x}}^7}{7}+\cdots +\frac{{\mathrm{x}}^{2\mathrm{n}-1}}{2\mathrm{n}-1}\right).$$ (7)

From the Taylor expansion results, it is evident that the logarithmic function can compensate for the third-order term at least. It is worth noting that |x| < 1 is a necessary condition, so it must be guaranteed during circuit design. To simulate the compensation effects of (7) on the nonlinear term Tln(T) in V_EB, construct the temperature-related functions F₁(T) and F₂(T) for the ideal calculations. F₁(T) and F₂(T) are expressed as

$$\{\begin{array}{l}{\mathrm{F}}_1(\mathrm{T})=-{\mathrm{r}}_0\cdot \mathrm{T}\cdot \ln \left(\frac{\mathrm{T}}{{\mathrm{T}}_{\mathrm{r}}}\right)\\ {\mathrm{F}}_2(\mathrm{T})={\mathrm{r}}_0\cdot \mathrm{T}\cdot \ln \left(\frac{1+\mathrm{h}\cdot \mathrm{T}}{1-\mathrm{h}\cdot \mathrm{T}}\right)\end{array},$$ (8)

where r₀ is a constant, and h is a coefficient that ensures hT < 1. F₁(T) and F₂(T) were combined in different proportions to obtain the predicted compensation results shown in Figure 5.

Figure 5.

Ideal results calculated for the proposed curvature compensation.

It is observed that the deviation between the maximum and minimum values of F₁(T) after compensating for F₂(T) is only 4% of that before compensation, which better suppresses the nonlinear term in V_EB and realizes curvature compensation.

In Figure 4, after obtaining the ΔV_EB with high-order compensation effect, the ΔV_EB with the coefficient R₂/R₁ is obtained through R₁, R₂, M₁ and M₃, and it is added to the V_EB of Q₃ to obtain the compensated bandgap voltage V_bgr. In order to further obtain the required reference voltage, the final reference voltage V_ref is obtained through the negative feedback structure composed of R₃, R₄, R_t1 and the amplifier. V_ref can be expressed as

$${\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}}=\frac{{\mathrm{R}}_3}{{\mathrm{R}}_3+{\mathrm{R}}_4+{\mathrm{R}}_{\mathrm{t}1}}\cdot {\mathrm{V}}_{\mathrm{b}\mathrm{g}\mathrm{r}}=\frac{{\mathrm{R}}_3}{{\mathrm{R}}_3+{\mathrm{R}}_4+{\mathrm{R}}_{\mathrm{t}1}}\cdot \left({\mathrm{V}}_{\mathrm{E}\mathrm{B}}+\mathrm{a}\cdot \frac{{\mathrm{R}}_2}{{\mathrm{R}}_1}\Delta {\mathrm{V}}_{\mathrm{E}\mathrm{B}}\right),$$ (9)

where the parameters a is the size ratio of M₁ and M₃.

2.3. Implementation of the Proposed Circuit

According to the ideal results obtained above, the main design goal is to introduce a nonlinear ΔV_EB in the BGR core circuit. Figure 6 presents the implementation of the proposed circuit, including a start-up circuit, a nonlinear ΔV_EB-based curvature-compensated BGR core circuit, a temperature-independent current generating structure, and a final reference voltage output.

Figure 6.

Schematic of the proposed curvature-compensated BGR circuit.

The R₅ and NMOS M₁₂, M₁₃, M₁₄ constitute a start-up circuit to drive the reference circuit out of the degenerate bias point when the supply voltage V_DD is turned on. When V_DD rises, M₁₂ and M₁₃ are turned on, and the gate voltage of the PMOS current mirrors is pulled down. After the whole circuit is started, M₁₄ is turned on, and M₁₂ and M₁₃ are turned off.

The traditional scheme of ΔV_EB generation uses currents with the same temperature characteristics to drive a pair of BJTs. The main difference in the proposed nonlinear ΔV_EB generation unit is that two sets of currents with different temperature characteristics are used to drive two sets of BJTs (Q₁ and Q₃, Q₂ and Q₄). The ΔV_EB of the proposed BGR is then given as

$$\Delta {\mathrm{V}}_{\mathrm{E}\mathrm{B}}={\mathrm{V}}_{\mathrm{E}\mathrm{B}1}+{\mathrm{V}}_{\mathrm{E}\mathrm{B}2}-{\mathrm{V}}_{\mathrm{E}\mathrm{B}3}-{\mathrm{V}}_{\mathrm{E}\mathrm{B}4}=2{\mathrm{V}}_{\mathrm{T}}\cdot \ln \left(\mathrm{N}\right)+{\mathrm{V}}_{\mathrm{T}}\cdot \ln \left(\frac{{\mathrm{I}}_{\mathrm{c}3}}{{\mathrm{I}}_{\mathrm{c}1}}\right)+{\mathrm{V}}_{\mathrm{T}}\cdot \ln \left(\frac{{\mathrm{I}}_{\mathrm{c}4}}{{\mathrm{I}}_{\mathrm{c}2}}\right),$$ (10)

where the emitter area ratios of Q₃ to Q₁ and Q₄ to Q₂ are both N = 24. Analyzing the collector current of each BJT, Q₁ and Q₃ are biased from the classic PTAT current (I_R1 = ΔV_EB/R₁). However, the collector currents of Q₂ and Q₄ are mainly the temperature-insensitive current I₀ mirrored by M₆, which are changed by the compensation currents I_co1 and I_co2. Thus, the high-order temperature characteristics of ΔV_EB are changed.

The voltage V_fb is equal to V_ref because of the effects of the amplifier and NMOS source follower M₉. The temperature-insensitive current I₀ can be expressed as

$${\mathrm{I}}_0\left(\mathrm{T}\right)=\frac{{\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}}}{{\mathrm{R}}_{\mathrm{t}\mathrm{b}}\left(\mathrm{T}\right)}=\frac{{\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}}}{{\mathrm{R}}_{\mathrm{t}\mathrm{b}}\left({\mathrm{T}}_{\mathrm{r}}\right)\cdot \left[1+\mathsf{\alpha }\left(\mathrm{T}-{\mathrm{T}}_{\mathrm{r}}\right)\right]},$$ (11)

where the temperature also affects the resistance, the current obtained is not strictly temperature-independent.

I_co1 and I_co2 are obtained by mirroring I_R1, and are written as

$$\{\begin{array}{l}{\mathrm{I}}_{\mathrm{c}\mathrm{o}1}={\mathrm{y}}_1\cdot {\mathrm{I}}_{\mathrm{R}1}=\frac{{\left(\mathrm{W}/\mathrm{L}\right)}_{10}}{{\left(\mathrm{W}/\mathrm{L}\right)}_9}\cdot \frac{{\left(\mathrm{W}/\mathrm{L}\right)}_7}{{\left(\mathrm{W}/\mathrm{L}\right)}_1}\cdot {\mathrm{I}}_{\mathrm{R}1}+{\mathrm{z}}_{\mathrm{t}\mathrm{r}\mathrm{i}\mathrm{m}1}\cdot {\mathrm{I}}_{\mathrm{R}1}\\ {\mathrm{I}}_{\mathrm{c}\mathrm{o}2}={\mathrm{y}}_2\cdot {\mathrm{I}}_{\mathrm{R}1}=\frac{{\left(\mathrm{W}/\mathrm{L}\right)}_8}{{\left(\mathrm{W}/\mathrm{L}\right)}_1}\cdot {\mathrm{I}}_{\mathrm{R}1}-{\mathrm{z}}_{\mathrm{t}\mathrm{r}\mathrm{i}\mathrm{m}2}\cdot {\mathrm{I}}_{\mathrm{R}1}\end{array},$$ (12)

where y₁ and y₂ are the size ratios between the corresponding metal-oxide semiconductors. The parameters z_trim1 and z_trim2 are set by the trimming module in Figure 6, and the parameters y₁ and y₂ are adjusted to change the temperature drift of the output. Based on I_R1 and I₀, the corresponding I_c1, I_c2, I_c3, I_c4 and parameters are expressed as

$$\{\begin{array}{l}{\mathrm{I}}_{\mathrm{c}1}={\mathrm{I}}_{\mathrm{R}1}\\ {\mathrm{I}}_{\mathrm{c}3}=\mathrm{b}\cdot {\mathrm{I}}_{\mathrm{R}1}=\frac{{\left(\mathrm{W}/\mathrm{L}\right)}_3}{{\left(\mathrm{W}/\mathrm{L}\right)}_1}\cdot {\mathrm{I}}_{\mathrm{R}1}\\ {\mathrm{I}}_{\mathrm{c}2}={\mathrm{x}}_1\cdot {\mathrm{I}}_0-{\mathrm{I}}_{\mathrm{c}\mathrm{o}1}=\frac{{\left(\mathrm{W}/\mathrm{L}\right)}_2}{{\left(\mathrm{W}/\mathrm{L}\right)}_6}\cdot {\mathrm{I}}_0-{\mathrm{y}}_1\cdot {\mathrm{I}}_{\mathrm{R}1}\\ {\mathrm{I}}_{\mathrm{c}4}={\mathrm{x}}_2\cdot {\mathrm{I}}_0+{\mathrm{I}}_{\mathrm{c}\mathrm{o}2}=\frac{{\left(\mathrm{W}/\mathrm{L}\right)}_4}{{\left(\mathrm{W}/\mathrm{L}\right)}_6}\cdot {\mathrm{I}}_0+{\mathrm{y}}_2\cdot {\mathrm{I}}_{\mathrm{R}1}\end{array}.$$ (13)

The drain currents of M₃, M₈, M₁₀ and M₁₁ are obtained by mirroring M₁, those of M₂ and M₄ are mirrored from M₆, and the parameters b, x₁, x₂, y₁ and y₂ are the scale coefficients. By substituting (13) into (10), we obtain

$$\Delta {\mathrm{V}}_{\mathrm{E}\mathrm{B}}={\mathrm{V}}_{\mathrm{T}}\left[2\ln \left(\mathrm{N}\right)+\ln \left(\mathrm{b}\right)\right]+{\mathrm{V}}_{\mathrm{T}}\ln \left(\frac{{\mathrm{x}}_2\cdot {\mathrm{I}}_0+{\mathrm{y}}_2\cdot {\mathrm{I}}_{\mathrm{R}1}}{{\mathrm{x}}_1\cdot {\mathrm{I}}_0-{\mathrm{y}}_1\cdot {\mathrm{I}}_{\mathrm{R}1}}\right).$$ (14)

Assuming that x₂ = cx₁ and y₂ = cy₁, where c is a constant. (14) can be rewritten as

$$\begin{array}{ll}\Delta {\mathrm{V}}_{\mathrm{E}\mathrm{B}}& ={\mathrm{V}}_{\mathrm{T}}\left[2\ln \left(\mathrm{N}\right)+\ln \left(\mathrm{b}\right)+\ln \left(\mathrm{c}\right)\right]+{\mathrm{V}}_{\mathrm{T}}\ln \left(\frac{1+{\mathrm{y}}_1/{\mathrm{x}}_1\cdot {\mathrm{I}}_{\mathrm{R}1}/{\mathrm{I}}_0}{1-{\mathrm{y}}_1/{\mathrm{x}}_1\cdot {\mathrm{I}}_{\mathrm{R}1}/{\mathrm{I}}_0}\right)\\ & =\underset{\mathrm{linear}}{\underbrace{{\mathrm{V}}_{\mathrm{T}}\ln \left(\mathrm{b}\mathrm{c}{\mathrm{N}}^2\right)}}+\underset{\mathrm{nonlinear}}{\underbrace{{\mathrm{V}}_{\mathrm{T}}\ln \left(\frac{1+\mathrm{h}\cdot \mathrm{T}}{1-\mathrm{h}\cdot \mathrm{T}}\right)}}\end{array}.$$ (15)

In Equation (15), it can be seen that the curvature compensation term shown as F₂(T) in Equation (8) is introduced into ΔV_EB to compensate for the nonlinearity of V_EB. Once the desired ΔV_EB is obtained, I_R1 is mirrored by M₅, and the resulting V_bgr is expressed as

$$\begin{array}{ll}{\mathrm{V}}_{\mathrm{bgr}}& ={\mathrm{V}}_{\mathrm{E}\mathrm{B}}+\mathrm{a}\cdot \frac{{\mathrm{R}}_2}{{\mathrm{R}}_1}\Delta {\mathrm{V}}_{\mathrm{E}\mathrm{B}}\\ & ={\mathrm{V}}_{\mathrm{E}\mathrm{B}}+\mathrm{a}\cdot \frac{{\mathrm{R}}_2\left(\mathrm{T}\right)}{{\mathrm{R}}_1\left(\mathrm{T}\right)}\left[{\mathrm{V}}_{\mathrm{T}}\ln \left(\mathrm{b}\mathrm{c}{\mathrm{N}}^2\right)+{\mathrm{V}}_{\mathrm{T}}\ln \left(\frac{1+{\mathrm{y}}_1/{\mathrm{x}}_1\cdot {\mathrm{I}}_{\mathrm{R}1}/{\mathrm{I}}_0}{1-{\mathrm{y}}_1/{\mathrm{x}}_1\cdot {\mathrm{I}}_{\mathrm{R}1}/{\mathrm{I}}_0}\right)\right]\end{array}.$$ (16)

Substitute (16) into (9) to obtain the final reference voltage V_ref.

2.4. Process Variations and Trimming

The BJTs, resistances, and current mirrors in the proposed BGR circuit are the main sources of error owing to process variations and mismatches. BGR error sources are classified into two types: PTAT and non-PTAT errors. The errors caused by the spread of BJT saturation current and resistances R₁ and R₂ are mainly of the PTAT type. The BJT current gain spread, BJT base resistance, opamp offset, and BJT collector current mismatches mainly constitute the non-PTAT errors.

PTAT errors are easily eliminated; thus, non-PTAT errors often determine the achievable precision of the BGR and require additional structures to ensure circuit accuracy. The proposed circuit contains many current mirror structures to provide bias and compensation currents for different BJTs. To minimize mismatches in the current mirrors, cascode-type current mirrors are used in the circuit to improve precision. In addition, the non-PTAT errors caused by process changes affect the proposed high-order curvature compensation method. The proposed trimming structure is shown in Figure 7.

Figure 7.

Schematic of the proposed trimming structure in BGR circuit: (a) resistance R_t2 Trimming; (b) compensation current trimming.

Figure 7a is a 4-bit trimming resistance network [16] for I₀ scaling, which is mainly used to ensure that the I₀ change caused by the resistance spread does not affect the curvature compensation precision. At the same time, the change of I₀ will also change the parameters c in (16). Figure 7b also depicts a 4-bit trimming structure for scaling the compensation currents I_co1 and I_co2 in the proposed circuit. This trimming structure is connected to the two nodes A and B shown in Figure 6 to change the parameters y₁/x₁ in (16) and achieve curvature compensation trimming. The two trimming blocks ensure appropriate curvature compensations in the presence of process variations or different application requirements. There are also trimming resistance R_t1 connected to the output to adjust the reference voltage V_ref. All trimming signals are generated by a fuse module controlled by the digital unit in our BMIC chip.

3. Experimental Results

Firstly, the temperature characteristics of some key points are analyzed based on the simulation results. Figure 8a presents the simulation results of V_EB and ΔV_EB with temperature changes. The nonlinear ΔV_EB and V_EB present complementary slope trends in the range of −40 to 125 °C.

Figure 8.

Simulated results of (a) V_EB and ΔV_EB versus temperature; (b) the first-order and proposed compensation of V_bgr versus temperature.

The bandgap voltage V_bgr before and after curvature compensation is shown in Figure 8b. V_bgr-1order is a first-order compensation result achieved after removing nonlinear compensation. The simulated results reveal that the maximum and minimum differences in V_bgr are reduced from 2 mV (without curvature compensation) to 0.2 mV (with curvature compensation) in the range of −40 to 125 °C. The best-found TC of V_bgr is 0.7 ppm/°C in the simulation result shown in Figure 8b.

Figure 9 presents the 500 runs Monte Carlo (MC) simulation results of the proposed BGR with a 5 V supply voltage. The variation (σ/μ) of the reference voltage from MC results is 0.271% in Figure 9a. In Figure 9b, the statistical distribution of the TCs indicates that the average TC is 2.63 ppm/°C and the standard deviation is 1.48 ppm/°C. The MC simulation results show that the circuit is insensitive to mismatch.

Figure 9.

Statistics of untrimmed Vbgr from a 500-run Monte-Carlo simulation. (a) V_bgr @ 27 °C; (b) TC in ppm/°C of V_bgr.

Figure 10a presents the chip microphotographs of proposed high-precision BGR circuit in the designed BMIC, which was implemented in a 0.18 μm BCD process. The whole BMIC area is 2.8 × 2.8 mm², and the BGR circuit occupies a chip area of 0.38 × 0.27 mm². We designed a BMIC test circuit to test the temperature and other related characteristics of the reference voltage of the chip. In the test circuit, place the BMIC in a white circle whose size corresponds to the cover of the temperature controller, isolated from other power supply and control modules, as shown in Figure 10b. This is to independently test the BMIC while simulating rapid temperature changes, ensuring accurate testing. At the same time, on the PCB, the relevant signals are connected to the outside of the white circle to ensure that the reference voltage changes can be monitored without affecting the temperature test.

Figure 10.

(a) Chip microphotograph of the proposed BGR circuits; (b) Photo of the BMIC test platform.

Figure 11 presents the measured temperature dependence of the bandgap voltage V_bgr and the reference voltage V_ref from −40 to 125 °C for six chips. The untrimmed V_bgr results are shown in Figure 11a. Process deviations cause the BGR output voltage to exhibit a positive temperature sensitivity, with an average TC of 26.04 ppm/°C. Figure 11b presents the measured V_ref results after TC trimming and voltage magnitude trimming. The tested optimal and worst TCs were 2.56 and 4.75 ppm/°C, respectively, and the σ/μ of the reference voltage is 0.11% at room temperature. The untrimmed inaccuracy is about ±0.43% (the maximum and minimum difference of V_bgr is 10.3 mV) over a temperature range of 165 °C, which decreases to approximately ±0.05% (the maximum and minimum difference of V_ref is 2.4 mV) after trimming at ambient temperature.

Figure 11.

Measured TCs of six samples: (a) untrimmed V_bgr as a function of temperature; (b) trimmed V_ref as a function of temperature.

In Figure 12a, it can be seen that the V_ref remains stable by continuously reducing the input voltage from 5.5 V to 4.5 V. Figure 12b presents the variation of six reference voltages versus supply at room temperature. When the supply voltage is increased from 4.5 to 5.5 V, the average variation in V_ref is 0.58 mV. Therefore, the average line sensitivity is 0.023%/V.

Figure 12.

Measured reference voltage versus supply voltage: (a) oscilloscope monitoring results; (b) six chip measurement results.

Table 1 summarizes the performances of the proposed BGR and compares it with some state-of-the-art designs. Compared to other BGR circuits, the proposed design achieves excellent temperature insensitivity, with a TC of 2.56 ppm/°C in the range of −40 to 125 °C. The current consumption of BGR is 53 µA with a 5 V supply voltage, and the area of the fabricated BGR circuit is 0.103 mm².

Table 1.

Performance summary and comparison with other works.

	[17] TCASII	[16] TCASII	[14] TCASI	[13] TCASI	[21] TCASI	[22] JSSC	This Work
Tech (μm)	0.18	0.18	0.18	0.13	0.18	0.16	0.18
Year	2021	2019	2017	2015	2014	2011	2022
Supply Voltage (V)	1.2–2.4	3.5–5	5.2	1.2	1.2	1.8	5
Reference Voltage (V)	0.628	3.11	3.65	0.735	0.767	1.088	2.5
Temperature Range (°C)	−40~120	−40~130	−40~110	−40~120	−40~120	−40~125	−40~125
TC Range (ppm/°C)	2.5~5	4.6~7.6	±3@3σ	9.3	4.9	5~12	2.56~4.75
LS (%/V)	0.03	0.031	N/A	N/A	0.54	0.48	0.023
Power (μA)	64.2	108	750	120	36	55	53
PSRR (dB)	−91.4 *	−92 *	−127	N/A	−80	−74	−84 *
Area (mm2)	0.024	0.223	0.28	0.063	0.036	0.12	0.103

* Simulation results.

4. Conclusions

A 2.5 V, 2.56 ppm/°C high-order curvature-corrected BGR over a temperature range of −40 to 125 °C is presented herein and implemented using 0.18 μm BCD technology. The circuit is based on the classic BGR structure using currents of different ratios and TCs to bias two sets of BJT pairs, thereby introducing nonlinear terms with compensation effects in ΔVEB to achieve temperature-independent voltage. The proposed structure is suitable for high-precision battery monitoring applications, such as EVs, energy storage, etc. Furthermore, this circuit has been used in the designed BMIC.

Author Contributions

Conceptualization, G.Z. and Q.Z.; methodology, G.Z. and Q.Z.; software, G.Z.; validation, G.Z.; formal analysis, G.Z.; investigation, G.Z.; resources, G.Z. and Q.Z.; data curation, Z.F. and T.L.; writing—original draft preparation, G.Z.; writing—review and editing, G.Z.; Z.F. and Q.Z.; visualization, Z.F. and T.L.; supervision, Q.Z. and Y.Y.; project administration, G.Z. and Q.Z.; funding acquisition, Q.Z. and Y.Y. All authors have read and agreed to the published version of the manuscript.

Funding

This work was supported by the Key Research and Development Project of Shaanxi Province (No. 2017ZDXM-GY-001), and the Industry-University-Academy Cooperation Program of Xidian University-Chongqing IC Innovation Research Institute (No. CQIRI-2021CXY-Z01).

Conflicts of Interest

The authors declare no conflict of interest.