Mixed-Dimensional 1D/2D van der Waals Heterojunction Diodes and Transistors in the Atomic Limit

Abstract

Inverting a semiconducting channel is the basis of all field-effect transistors. In silicon-based metal-oxide-semiconductor field-effect transistors (MOSFETs), a gate dielectric mediates this inversion. Access to inversion layers may be granted by interfacing ultrathin low-dimensional semiconductors in heterojunctions to advance device down-scaling. Here we demonstrate that monolayer molybdenum disulfide (MoS₂) can directly invert a single-walled semiconducting carbon nanotube (SWCNT) transistor channel without the need for a gate dielectric. We fabricate and study this atomically thin one-dimensional/two-dimensional (1D/2D) van der Waals heterojunction and employ it as the gate of a 1D heterojunction field-effect transistor (1D-HFET) channel. Gate control is based on modulating the conductance through the channel by forming a lateral p–n junction within the CNT itself. In addition, we observe a region of operation exhibiting a negative static resistance after significant gate tunneling current passes through the junction. Technology computer-aided design (TCAD) simulations confirm the role of minority carrier drift-diffusion in enabling this behavior. The resulting van der Waals transistor architecture thus has the dual characteristics of both field-effect and tunneling transistors, and it advances the downscaling of heterostructures beyond the limits of dangling bonds and epitaxial constraints faced by III–V semiconductors.

Graphical Abstract

Inverting a transistor channel with the field effect modulates its conductance and gives rise to metal-oxide-semiconductor field-effect transistors (MOSFETs), which are the most ubiquitous electronic devices manufactured today. The MOSFET incorporates an electrically insulating gate dielectric to mediate electrostatic inversion in the transistor channel. However, the scaling of gate dielectrics is limited by gate tunneling currents that must be kept below 10 A cm⁻² in most circuit applications.^1,2 Improvements in MOSFET electrostatics to achieve the desired channel length scaling are being explored, among others, through 1D nanowire, gate-all-around architectures.^3,4 In this work, we explore field-effect transistors based on transport at the mixed-dimensional heterojunction (MDHJ) interface between a 2D gate, in the form of monolayer MoS₂, and a 1D channel, in the form of a semiconducting carbon nanotube (CNT). The conduction-band discontinuity formed at this heterojunction acts as a barrier to tunneling transport in reverse bias while mediating inversion of the underlying CNT channel. In this way, such devices have features in common with gallium arsenide–aluminum gallium arsenide (GaAs–AlGaAs) high-electron-mobility transistors (HEMTs) while enabling the fabrication of a 1D channel with high-quality van der Waals interfaces that do not require lattice matching and that mitigate issues associated with trap states introduced by dangling bonds at conventional gate-oxide interfaces in bulk materials.

Since the 1970s, it has been known that highly doped abrupt p–n heterojunctions support inversion layers at their material interface.^5,6 When the p–n heterojunction is reverse-biased, a minimum inversion voltage, V_i, can be defined, for which this layer always exists

$$V_{\text{i}}=\frac{kT}{q}\text{ln}\left(\frac{N_2}{N_1}\frac{1}{A\left(\text{Δ}{E}_i\right)}\right)$$ (1)

where k is the Boltzmann constant, T is the temperature, q is the electronic charge, N₁ and N₂ are the respective doping levels of the two materials, and A is a material constant dependent on the exact band offset at the junction, ΔE_i = (χ₁ + E_g1/2) – (χ₂ + E_g2/2), where χ₁ and χ₂ are the respective electron affinities and E_g1 and E_g2 are the respective band gaps. The condition for the formation of an inversion layer is then determined by ΔE_i < 0 eV.⁶ Modulation doping of this kind has been utilized for decades in III–V heterojunctions to form modulation-doped HEMTs for high-frequency switching and power electronics applications.^7,8 However, these material systems rely on the lattice-matched epitaxial growth of bulk semiconductors to provide the necessary interface quality in these transistor applications with lattice-matching requirements at the heterointerfaces.

MDHJs are an emerging class of nanoscale devices with many intriguing electrical and optical properties.^9–13 Stacked van der Waals heterojunctions allow for the flexible fabrication of such structures free of constraints imposed by heteroepitaxy^14–17 and of the dangling bonds characteristic of many heterointerfaces.^18–28 Synthetic van der Waals materials are therefore ideal candidates for realizing atomically abrupt highly doped p–n heterojunctions. Modulation-doped layers were already observed in multilayer heterostructures of MoS₂ and tungsten diselenide (WSe₂), where the estimated inversion layer thickness was <2 nm,²⁹ and were recently employed to create remotely doped 2D/2D field-effect transistors with improved electron mobilities due to reduced dopant-related scattering.³⁰ Solid-state tungsten oxyselenide has also been recently shown to efficiently dope graphene through direct charge transfer.³¹ Individual 1D metallic single-walled carbon nanotubes (SWCNTs), in turn, have been observed to electronically couple to 2D semiconductors in vertical van der Waals heterojunctions.^32–36 Meanwhile, a recent report has shown that an MDHJ consisting of a semiconducting multiwalled CNT and multilayer MoS₂ exhibits gate-tunable band-to-band tunneling (BTBT) in reverse bias.³⁷ A wrap-around gate architecture utilizing monolayer n-type MoS₂ as the gate for a p-type SWCNT channel is therefore expected to be electrostatically effective in creating strong inversion, as the electronic band gap of MoS₂ increases from 1.2 to >2 eV in the monolayer limit, creating large conduction and valence band discontinuities at the material interface.

Here we exploit such heterojunctions to create a 1D depletion-mode heterostructure field-effect transistor (1D-HFET) in which the formation of the inversion layer shuts the device off. Inverting the CNT with the MoS₂ gate creates a voltage-controlled migrating lateral p–n junction inside of the nanotube channel itself as the device is biased deeper into inversion. The n-type layer that begins to form at the source extends toward the drain and controls the flow of drain current by forming a reverse-biased p–n homojunction at the source terminal. At high gate-to-channel reverse biases, the gate begins to leak through BTBT. This injects holes into the inverted electron channel in the nanotube, and they diffuse to the source and drain terminals, producing a partitioned current flowing out of the source and drain, even at V_ds > 0 V.

RESULTS AND DISCUSSION

Atomic-Scale 1D/2D Heterojunction Fabrication and Characterization.

The 1D-HFET device is shown in Figure 1a. The constituent n-type MoS₂ and p-type SWCNT of the MDHJ are separately synthesized by distinct chemical vapor deposition (CVD) processes;^38,39 these steps are described in detail in the Methods and in Supporting Figure 1. We interface the two materials with a site-non-specific wet-transfer method, similar to a previously reported approach for 2D materials on SiO₂,⁴⁰ where we deposit the MoS₂ monolayers on top of the nanotubes on their native growth substrate. Because of the dense areal coverage of the MoS₂ flakes and the relatively long span of the individual nanotubes, this can yield several junctions per single nanotube. A closer look at a formed junction is presented in the electrostatic force microscopy (EFM) map in Figure 1b. Under no biasing, the as-formed MDHJ shows strong contrast from the underlying SiO₂ substrate and a slight variation in the phase offset between the MoS₂ flake area and the overlap area with the SWCNT, similar in magnitude to those observed in EFM for MoS₂/pentacene heterojunctions,⁴¹ suggesting a localized change in the surface potential due to charge transfer at the interface. The atomic force microscopy (AFM) height maps in Supporting Figure 2 reveal that the SWCNT lifts the edge of the MoS₂ flake off the substrate by several nanometers while the monolayer semiconductor wraps around the nanotube, creating a protruding ridge on the surface. Figure 1c is a representative scanning electron micrograph (SEM) showing the formed MDHJs following the transfer process, with more examples presented in Supporting Figure 3. When compared with typical 2D/2D van der Waals heterojunctions, which can be thousands of squared microns in area, for example, WSe₂/MoS₂,⁴² our 1D/2D contact areas are five orders of magnitude smaller, with an average overlap area of 0.018 μm², as extracted across MDHJs from three different CNT growth substrates.

Figure 1.

Mixed-dimensional 1D/2D van der Waals heterojunction platform. (a) Illustration of the van der Waals 1D-HFET architecture with the three electrical terminals outlined. (b) EFM phase map of an as-made MDHJ at no applied bias across the device, showing the relative change of surface potential across the junction. (c) Large-area SEM demonstrating the typical morphology of the junction areas following the transfer procedure. In many cases, a single nanotube is contacted with multiple MoS₂ flakes. (d) Raman spectra of monolayer MoS₂ on the bare flake (blue) and in the MDHJ region (green). (e) Raman spectra of the SWCNT on the bare nanotube (purple) and in the MDHJ region (green). (f) Photoluminescence spectra of monolayer MoS₂ from a bare flake region (red) and from the MDHJ region (green).

Figure 1d shows the change to the Raman signal of the as-grown monolayer MoS₂ (blue) in the region of the MDHJ interface (green). In the heterojunction area, both the in-plane (E′) and out-of-plane ($A_1^{\prime }$) Raman modes of MoS₂ experience significant intensity quenching. In addition, the 2LA(M) mode at ~450 cm⁻¹ is also substantially quenched. The intensity decrease is expected as the dielectric screening environment of MoS₂ at the MDHJ changes significantly, and similar Raman quenching has also been observed in other layered semiconductor heterojunctions.^16,23,29 The positions of both characteristic peaks shift from 383.8 to 384.3 cm⁻¹ for the E′ mode and from 403.0 to 403.3 cm⁻¹ for the $A_1^{\prime }$ mode. The upshift in both peaks has previously been associated with electron withdrawal from MoS₂.⁴³ This is in agreement with the expected charge transfer occurring at the formed p–n heterojunction interface, which has also recently been indirectly probed with electrical measurements in multilayer MoS₂/multiwall CNT junctions.³⁷

In the same vein, Figure 1e shows the Raman spectrum of the G band of a semiconducting SWCNT.⁴⁴ Relative to the as-synthesized SWCNT (purple), the peak intensity in the MDHJ region (green) decreases substantially, accompanied by noticeable broadening and an upshift of the peak position from 1593.1 to 1595.1 cm⁻¹. This shift of the G band has previously been reported for the noncovalent functionalization of SWCNTs with donor molecules.⁴⁵ The upshift in the peak position following electron acceptance in SWCNTs is theoretically expected for donor concentrations of up to ~10¹³ cm⁻², beyond which the G peak begins to downshift.⁴⁶ In our case, the unidirectional 2 cm⁻¹ upshift is thus likely caused by direct electron transfer from the MoS₂ to the CNT. This strong interlayer charge transfer in thin van der Waals materials has recently been shown to also invert n-type MoS₂ to p-type when interfaced in a p–n heterojunction with WSe₂.⁴⁷

Figure 1f shows the photoluminescence (PL) spectrum of monolayer MoS₂ taken from the same flake in the non-overlapped area (orange) and from the MDHJ area (green). A notable decrease in the PL yield is observed in the heterojunction-containing area, as significant nonradiative recombination now occurs due to charge transfer at the junction. This has also been reported for other MDHJs containing layered semiconductors or SWCNTs.^{9,11,26,30,48} A small downshift to the direct-recombination A exciton energy is also observed (from 1.85 to 1.83 eV), whereas the integrated contribution of the spin–orbit split B exciton is more significant in the heterojunction region. This suggests a more complex interplay between photogenerated excitons and built-in charges at the junction, which warrants a dedicated study. We present additional Raman and PL data sets from other MDHJ samples, including peak fitting and discussion, in Supporting Figure 4.

Mixed-Dimensional van der Waals p–n Diode.

We proceed with the discussion of the measured temperature-dependent I–V characteristics of the atomic-scale p–n MDHJ diode (illustrated in Figure 2a and shown in the colored SEM image in Figure 2b). Figure 2c presents the two-terminal I–V characteristics of the diode taken at various temperatures between 300 and 20 K. Positive (negative) voltages signify nominal forward (reverse)-bias functionality; that is, the CNT is at a high potential relative to the MoS₂ in forward bias. The band alignment at the hybrid 1D/2D heterojunction is expected to produce a Type I heterojunction, that is, a straddling gap, which was also recently reported in a coaxial 1D CNT–MoS₂ heterostructure with a boron nitride spacer⁴⁹ and in multiwalled CNT/multilayer MoS₂ devices.³⁷ Note that the van der Waals gap is explicitly omitted here. The electron affinities of the two materials (χ_MoS2 = 4.2 eV, χ_CNT = 4.3 to 4.5 eV) and the electronic band gaps (E_g,MoS2 = 2.15 eV, E_g,CNT ≈ 0.6 eV) result in significant conduction and valence band discontinuities (ΔE_C and ΔE_V, respectively), forming inversion layers at the interface in a manner analogous to GaAs–AlGaAs p–n heterojunctions.⁵⁰ Because the materials used here are extremely thin, the high electric field established by applying an external voltage will heavily bend the bands at the 1D/2D interface, strongly modulating the charge transport across the heterojunction. Supporting Figure 5 shows expected heterojunction band diagrams before layers are contacted and in equilibrium without external bias.

Figure 2.

Temperature-dependent I–V characteristics of the 1D/2D p–n heterojunction diode. (a) Sketch of the two-terminal atomic-scale diode. (b) False-colored SEM of the tested device. Scale bar, 2 μm. (c) Temperature-dependent I–V characteristics of the SWCNT–MoS₂ device measured at V_bg = 0 V, with the bias conventions illustrated in the insets on the plot. The band diagram insets conceptualize the transport behavior across the heterojunction in each region of the sweep.

In forward bias, the device current increases rapidly at first when V < 1 V, dominated by low-bias direct tunneling. Because of the large band gap of the MoS₂ monolayer, thermionic hole transport from the CNT to the MoS₂ is limited in this region. As the voltage on the CNT is increased, a weakly temperature-dependent plateau of ~3 V is traversed until significant thermionic hole conduction begins to take over at room temperature, as the CNT bands are bent down by the strong electric field. Because these are thermally generated carriers, their contribution is strongly suppressed at cryogenic temperatures, extending the voltage plateau to >6 V below 77 K. In reverse bias, the device is initially in a strong thermionic regime, where the current can be modulated by over two orders of magnitude between room temperature and 20 K. This is due to minority carrier transport across the interface barrier from the CNT to the MoS₂, which is heavily dependent on thermal activation. Because the depletion region in this atomically thin p–n junction is vanishingly thin,⁵¹ any minority carriers generated within the diffusion length of the 1D/2D interface will be swept across the vertical space-charge region, resulting in substantial reverse-bias saturation currents. At high temperatures, the contributions of this generation current and that of BTBT to the total current are convoluted together. At 20 K, it is more clearly observed that BTBT begins to dominate transport in reverse bias at approximately −2 V. At this point, tunneling of electrons from the valence band of the CNT to the conduction band of the MoS₂ begins to dominate carrier transport across the junction, and it is largely temperature-independent.³⁷ This tunneling breakdown is reversible and indicates a Zener-like mechanism, as the critical voltage⁵² necessary for BTBT here is <4E_g/q = 5.16 V, when considering the lower band gap of the CNT at E_g ≈ 0.6 eV. We remark here that device-to-device variation during fabrication can result in these regimes existing over different voltage ranges, although the key features of BTBT and the reverse-bias generation current persist. (See the Supporting Figure 6 for I–V data of six more devices with different channel lengths.) We suspect that much of this variation is the result of recombination–generation centers introduced at the van der Waals interface during the wet-transfer procedure.

The I–V response of the MDHJ diodes changes considerably when V_bg is applied to control the carrier density in the heterostructure. As seen from the linear and semilog scale plots of another device (Figure 3a,b), increasing V_bg suppresses the junction conductance in reverse-bias, as was also found for multiwall CNT/multilayer MoS₂ devices.³⁷ Interestingly, this trend is opposite to that seen for ensemble SWCNT–MoS₂ networks,⁵³ suggesting that junction geometry is the governing factor for individual MDHJ devices. The observed suppression of reverse-bias conductance may thus be attributed to an increased doping offset between the bare CNT portion and the part of the nanotube that is covered by the MoS₂ flake. As shown in the Raman results, the CNT readily accepts electrons from the MoS₂ and becomes n-doped. With increasing positive V_bg, this inversion deepens in the covered CNT region, developing a more rectifying p–n homojunction within the CNT itself. This raises the diode rectification ratio from 9.5 at V_bg = 0 V to 3.4 × 10⁴ at V_bg = 10 V. Eventually, as the CNT fully inverts at very high positive back-gate voltages, an effective n–n⁺ heterojunction is formed,⁵³ and the diode rectification ratio decreases. This forward-bias rectification effect is more pronounced for monolayer MoS₂ flakes than multilayer flakes³⁷ due to reduced electrostatic screening, granting the monolayer-based architecture an advantage in terms of the conductance tunability. The negative V_bg rectification trend is explained analogously; in this case, a p–p⁺ heterojunction forms as the MoS₂ is depleted by the highly negative gate voltage, forming a backward-rectifying junction with the enhanced p-type CNT.³⁷

Figure 3.

Gate tunability of the MDHJ diode. (a,b) Gate tunability of the diode I–V characteristics on linear and semilog scales, respectively. The colors correspond to the magnitude of the applied back-gate bias mapped to the color bars next to the panels. The inset of panel a shows the rectification ratio extracted at V_ds = ±5 V as a function of V_bg. (c) Gate curve of the p–n heterojunction (L_ch = 4 μm), exhibiting an antiambipolar response and two distinct off-states. Inset shows the back-gate transfer curve of a SWCNT on the same chip.

The back-gated transfer characteristics of the individual junction devices demonstrate a clear antiambipolar window behavior that was previously also observed in ensemble SWCNT–MoS₂ junctions^18,53 and was recently employed to make proof-of-concept 1D/2D tunneling FETs.³⁷ The off states seen in the transfer curve correspond to transition regions on either side of the back-gate-dependent n–n⁺/p–p⁺ diode formation. The CNT-controlled majority-hole side of the gate sweep dominates the device response at negative V_bg, likely due to the easier depletion of the thinner MoS₂ monolayer by the back gate. Additional evidence of electron transfer between the MoS₂ and the CNT can be obtained from changes to the secondary electron yield, that is, work function contrast in the SEM. In some devices, we observed the MoS₂ areas near the CNT junction turning significantly darker than the rest of the flake under the same imaging conditions. (See Supporting Figure 7.) In the following sections, we focus on utilizing the reverse-bias regime of the 1D/2D heterojunction, which causes inversion in the CNT to create HEMT-like transistor action.

1D Heterojunction Field-Effect Transistor.

As shown in Figure 4a, reverse-biasing the gate junction beyond the threshold voltage, V_i, allows for an n-type region to form in the nanotube. We note that in the case of V_gs ≈ 0 V, for a typical drain bias of V_ds = 1 V, an inverted n-type region already exists at the drain due to minority carrier injection at the gate–drain junction,⁵⁴ but it is not sufficient to turn the device off, resulting in depletion-mode transistor behavior. With increasing positive top-gate voltage, the gate heterojunction becomes more reverse-biased, and the n-type layer extends from the drain to the source, resulting in a reduced I_ds. The band diagram in Figure 4b shows how the inversion layer at the interface of the van der Waals MDHJ forms under reverse bias. The native electron doping levels for CVD-synthesized MoS₂ are on the order of 0.13 nm⁻²,⁵⁵ whereas the induced carrier density between MoS₂ and an individual CNT of diameter ~1.2 nm has been calculated at 0.39 nm⁻¹.³⁷ The diameters of SWCNTs used here are <2 nm, resulting in strong inversion at gate voltages exceeding V_i. Moreover, utilizing monolayer MoS₂ with its larger band gap increases the band offsets at the junction interface, making single-layer 2D semiconductor gates more favorable candidates for mediating inversion than their lower band gap multilayer counterparts.

Figure 4.

Mixed-dimensional heterojunction inversion field effect. (a) Illustration of the 1D-HFET device architecture when the gate junction is reverse-biased past V_i. An inversion layer begins to form in the carbon nanotube, which renders holes minority carriers in the device channel. (b) Associated band diagram of the heterojunction in reverse bias, visualizing the formation of the inversion layer. (c) TCAD-simulated space-charge heatmaps showing the formation of the p–n homojunction in the CNT channel. (d) TCAD-simulated top-gate (I_gs) and drain (I_d) currents as a function of the applied gate bias. Note that I_d here is explicitly current into the drain and not exclusively I_ds. (e) Experimentally recorded I_gs and I_d traces, showing the shifted onset of channel shut-off in the real device.

Figure 4c presents the TCAD-simulated space-charge distributions in the 1D-HFET device when the gate heterojunction is in nominal reverse bias, that is, V_gs > 0 V. As seen in the plots, inversion occurs in both the CNT channel and the MoS₂ gate due to the conduction and valence band discontinuities. This creates gate leakage characteristics that are the same as the I–V response of the two-terminal diode in Figures 2 and 3. (See the experimental I_gs–V_gs traces in Supporting Figure 8.) Figure 4d shows the TCAD-simulated drain (I_d) and top-gate (I_gs) currents as a function of the voltage applied to the MoS₂ gate. Simulations predict that the channel conduction in the CNT may be reduced by eight orders of magnitude before significant gate leakage currents flow through the 1D/2D gate junction. The formation of the internal p–n–p homojunction inside the CNT is also independent of current flow through the gate heterojunction. (See TCAD simulations with BTBT disabled in Supporting Figure 9.) This inversion-facilitated field-effect window is subsequently followed by a region of negative current flow into the drain when gate leakage becomes significant. The corresponding measured experimental performance is shown in Figure 4e. In contrast with the simulated results, the drain current characteristic has a much larger threshold voltage. As a result, significant tunneling current flows before the drain current can be fully turned off. In Supporting Figure 10, we show TCAD simulations that demonstrate how the electrostatics of the junction interface strongly affect the threshold voltage. As expected, a more conformal gate wrapping of the CNT leads to a much shorter screening length and threshold voltage. The tent-like structure achieved here experimentally likely introduces stray fields that require higher voltages to fully invert the CNT. (See the data from another device in Supporting Figure 11.) Coaxial wrapping in 1D van der Waals diodes^49,56 may be an attractive solution to eventually quench the tunneling current through appropriate work function and band-gap engineering.

1D-HFET Behavior for V_gs ≫ V_ds.

This condition, such that BTBT occurs at the gate, should be avoided in normal device operation. However, it is of interest to examine how the device behaves in this regime. Figure 5a shows linear-scale 1D-HFET I_d versus V_gs curves recorded at V_ds values of 0.1, 0.5, and 1.0 V. After inversion occurs and the drain current fully switches off, continuing the gate sweep to high voltages results in the drain current flowing out of the drain (or the current into the drain turning negative). This is marked by the blue negative static resistance region on the plot in Figure 5a, where more current flows out of the drain for a lower V_ds (see also the semilog scale plots in Figure 5b), with the gate leakage current now flowing from the gate to the drain, even though V_ds > 0 V, because in this case, V_gd > 0 V. In this bias regime, electrons from the valence band of the CNT tunnel into the conduction band of the MoS₂. This constitutes the high positive current flow into the gate terminal. In MOSFETs with ultrathin gate oxides, this large gate-to-channel current partitions into source and drain currents.^57–59 The notch of the gate leakage current trace in our devices is also observed to shift accordingly with the applied V_ds (see Supporting Figure 7), as expected from the drain-dominated partitioning model.⁵⁹ In the ultrathin body 1D-HFET, a consequence of the BTBT action localized at the gate junction is the injection of a high concentration of holes into the middle of the inverted CNT channel, which transport by both drift and diffusion to both the source and the drain.

Figure 5.

Operation of the 1D-HFET at high gate biases. (a) 1D-HFET transfer curves taken at different V_ds biases. Red circles mark the crossing point of I_d from positive to negative, where the device enters the negative static resistance region colored in blue. The device is shown in the image in the inset. (b) Same curves shown on a semilog scale. Note the reversed dependence of the current magnitude on the V_ds magnitude at high positive gate voltages. (c) Output characteristics of the 1D-HFET at increasing MoS₂ gate biases. For higher V_gs values, the device characteristics migrate deeper into the fourth quadrant of the I–V plane. (d) TCAD-simulated longitudinal electric-field distribution in the carbon nanotube after gate tunneling (V_gs = 22 V), showing the migration of charge carriers away from the center of the channel, where the CNT–MoS₂ gate junction is. (e) TCAD-simulated gate, drain, and source current traces as a function of V_gs. The gate current due to electron tunneling is balanced by hole current flowing out of the source and out of the drain.

In Figure 5d, the TCAD-generated electric-field vector maps in the CNT channel at V_gs = 22 V show current flow out both the source and drain terminals. In addition, in Figure 5e, we show the TCAD-simulated gate, drain, and source characteristics as a function of the applied V_gs. As I_d decreases initially before gate breakdown, the source current (which is of opposite sign to the drain current) is tracking I_d. When the gate tunneling current increases, the drain and source currents begin to be dominated by I_gs, with an observed increase in the source current, which also generates the observed negative resistance at the drain.

We remark here on the possible future routes of engineering this hybrid dimensional material system to utilize the modulation-doped 1D-HFET devices for circuit applications. As shown recently in remotely doped 2D/2D van der Waals heterostructures, modulation doping by direct charge transfer can improve the carrier mobility in quantum-confined transistor channels through the mitigation of charged impurity scattering.³⁰ Thus 1D/2D heterostructures may be well-positioned to enable the fabrication of high-mobility 1D transistors in the atomic limit. Ultimately, the fabrication of enhancement-mode devices is necessary, which might be achieved through the specialized contact engineering of CNTs^60,61 or the utilization of chemically doped 2D gates,³⁰ such that the CNT channel is normally off at V_gs = 0 V. In addition, further transport studies need to be performed to determine the nature of the formed 1D electron gas and to investigate the role of charged impurity scattering from the MoS₂ monolayer on carriers in the CNT channel.

CONCLUSIONS

In summary, we have reported an atomically thin van der Waals MDHJ diode whose electronic properties allow for the creation of a prototype dielectric-less transistor on the nanoscale. In many respects, the 1D-HFET is a 1D version of the standard HEMT device structure, taking full advantage of 1D/2D heterojunctions in the atomic limit. However, full control and understanding of the mechanisms of gate tunneling and junction quantum capacitance in these devices must still be explored. Moreover, future spectroscopic studies should focus on elucidating the nature of the charge transfer between 2D semiconductors and CNTs to allow for more controlled engineering of device physics at these MDHJs.

METHODS

Carbon Nanotube Synthesis.

SWCNTs were grown by alcohol catalytic chemical vapor deposition (ACCVD) in a quartz tube furnace with a 28 mm inner tube diameter. Cobalt thin films (~4 nm) were deposited on thermally oxidized (285 nm SiO₂) p⁺⁺ silicon substrates in an Angstrom Ultra High Vacuum EvoVac electron beam evaporator at a chamber pressure of ~2 × 10⁻ mbar. The substrates were partially masked with Kapton tape to define multiple Co areas on the chip. Prior to CNT growth, the tape was taken off, and the substrates were annealed for 10 min at 750 °C in air and for another 10 min under flowing Ar gas (120 sccm). CNT growth occurred at a temperature of 890 °C with a H₂/Ar gas flow (8.7 and 40 sccm, respectively) through an ethanol gas bubbler submerged in an ice bath. The total growth time was 60 min, after which the ethanol bubbler was diverted from the gas flow and the furnace was cooled to room temperature in ~15 min by fan.

Single-Layer MoS₂ Synthesis.

Solutions of sodium cholate growth promoter (10 mg mL⁻¹) and ammonium heptamolybdate (11 mg mL⁻) were spun onto precleaned 300 nm SiO₂/Si substrates. The samples were then inserted into the center of a 1 in. tube furnace (Thermo Scientific Lindberg/Blue M) and were flushed with N₂ gas (1000 sccm) at room temperature for 10 min. After flushing, the samples were heated under N₂ gas flow (400 sccm) at a rate of 70 °C min⁻¹ and then held at 750 °C for 15 min. Approximately 150 mg of sulfur powder was placed 22 cm away from the target substrates and heated to 180 °C during the growth process. The substrates were rapidly cooled to room temperature by opening the furnace to finish the synthesis.

Sample Transfer and Device Fabrication.

The transfer process is visualized in Figure S1. In brief, the SiO₂/Si chip containing the MoS₂ monolayers (approximately 1 cm × 1 cm) was spin-coated in a poly(methyl methacrylate) layer (PMMA A6, rpm = 4000). The resist was not baked so as not to adhere it too strongly to the SiO₂. The PMMA film was scratched off on the edges of the chip with a razor blade, and the chip was then floated on top of concentrated (~4 M) potassium hydroxide (KOH) solution overnight. The exposed SiO₂ edges were lightly dipped into the solution using tweezers, allowing for the chemical dissolution of the oxide layer, leaving the PMMA film containing the MoS₂ floating on the surface. Filter paper was held with tweezers and used to scoop the PMMA film out of the solution and into another beaker containing deionized (DI) water to clean off the KOH residue. This was done multiple times into successive clean DI water beakers. Finally, the target substrate containing the CNTs and predeposited electron-beam lithography (EBL) markers was held with tweezers and used to scoop the PMMA film out of the water. The sample was then dried off with a nitrogen gun and baked on a hot plate at 80 °C for 15 min to flatten the PMMA film and to promote MoS₂ adhesion to the target substrate. The PMMA film was then dissolved in acetone and washed in acetone/isopropyl alcohol (IPA)/water. Following SEM identification of the heterojunctions, electron beam lithography was performed using a bilayer resist process (bottom layer P(MMA-MAA 8.5%) copolymer and top layer PMMA A6), both spun at 4000 rpm and baked at 180 °C for 5 and 2 min, respectively. The exposure was performed at 80 keV using the Nanobeam nB4 system at a beam current of 40 nA and chamber pressure of ~10⁻ mbar. Development was done in a cold (4 °C) mixture of isopropanol/H₂O (3:1) for 60 s. Metallization was performed in the Angstrom Ultra High Vacuum EvoVac electron beam evaporator at a base pressure of <10⁻⁷ mbar, depositing 10 nm of Cr followed by 100 nm of Au. Liftoff was done overnight in room-temperature acetone, with no ultrasonication, followed by a wash in isopropanol and drying with a nitrogen gun.

Raman and Photoluminescence Spectroscopy.

Both Raman and PL measurements were taken on the same system (Renishaw inVia) using a 532 nm laser (spot size ~1 μm, grating = 1800 lines mm⁻¹, edge filter, 50× objective) with the power kept below 1 mW to avoid excessive heating of the samples. For the MDHJ area, an extended range Raman spectrum was acquired, confirming the existence of both MoS₂ and SWCNT peaks in the overlap region, before recording any PL spectra.

Atomic Force and Scanning Electron Microscopy.

AFM was performed on the Bruker Dimension FastScan system in tapping mode in air using cantilevers tuned to 256 kHz, with 512 lines per scan at a scan rate of 1 Hz. The EFM measurements were performed on the same system using a Si tip at the same frequency, with the tip biased to 4 V and the sample stage grounded. The lift-mode electrostatic force scan was carried out at 30 nm away from the sample surface following an initial standard tapping mode topography scan. The AFM/EFM results were analyzed using Gwyddion software. SEM imaging was performed on the Zeiss Sigma VP microscope at low beam energies (<4 keV) using the in-lens detector at a working distance of ~4 mm and a 30 μm aperture. The SEM images were analyzed using ImageJ software.

Electrical Measurements and TCAD Simulations.

Room-temperature electrical characterization was carried out in air with a semiconductor device parameter analyzer (Agilent B1500A) on a custom-built probe station with triaxial connectors. For any back-gating measurements, the chip containing the devices was placed on conductive carbon tape on a glass slide, and one of the probes was used to contact the tape. All sweeps were unidirectional, starting from negative voltages. The nominal source electrode was always grounded relative to the gate and drain. Following wire bonding, transport measurements at variable temperatures were performed in a CTI-Cryogenics model 22 refrigerator using a Keithley 2400 source meter. All of the collected data were analyzed using Python. TCAD simulations were performed using the Sentaurus Device package. For a detailed description of the material parameters used for the modeling, refer to the Supporting Information.