Skip to main content
NCBI home page
ACS AuthorChoice logoLink to ACS AuthorChoice
. 2022 Oct 27;4(11):5292–5300. doi: 10.1021/acsaelm.2c00771

Synergistic Approach of Interfacial Layer Engineering and READ-Voltage Optimization in HfO2-Based FeFETs for In-Memory-Computing Applications

Yannick Raffel †, Sourav De †,*, Maximilian Lederer †, Ricardo Revello Olivo †, Raik Hoffmann †, Sunanda Thunder †, Luca Pirro ‡, Sven Beyer ‡, Talha Chohan ‡, Thomas Kämpfe †, Konrad Seidel †, Johannes Heitmann
PMCID: PMC9686141  PMID: 36439397

Abstract

graphic file with name el2c00771_0008.jpg

This article reports an improvement in the performance of the hafnium oxide-based (HfO2) ferroelectric field-effect transistors (FeFET) achieved by a synergistic approach of interfacial layer (IL) engineering and READ-voltage optimization. FeFET devices with silicon dioxide (SiO2) and silicon oxynitride (SiON) as IL were fabricated and characterized. Although the FeFETs with SiO2 interfaces demonstrated better low-frequency characteristics compared to the FeFETs with SiON interfaces, the latter demonstrated better WRITE endurance and retention. Finally, the neuromorphic simulation was conducted to evaluate the performance of FeFETs with SiO2 and SiON IL as synaptic devices. We observed that the WRITE endurance in both types of FeFETs was insufficient Inline graphic to carry out online neural network training. Therefore, we consider an inference-only operation with offline neural network training. The system-level simulation reveals that the impact of systematic degradation via retention degradation is much more significant for inference-only operation than low-frequency noise. The neural network with FeFETs based on SiON IL in the synaptic core shows 96% accuracy for the inference operation on the handwritten digit from the Modified National Institute of Standards and Technology (MNIST) data set in the presence of flicker noise and retention degradation, which is only a 2.5% deviation from the software baseline.

Keywords: neuromorphic computing, Flicker noise, interface traps, FeFET, hafnium oxide, interface treatments

Introduction

The advent of neural networks (NN), especially the convolution neural network,1−3 brought a historical change in the field of computing, and machine learning became the bona fide choice for solving many tasks. However, the software-based artificial neural networks (ANN) implemented in traditional von Neumann computing systems face severe bottlenecks due to the latency engendered by the data transfer between segregated memory units and processing units. This bottleneck has become more vivid with the plethora of edge devices in recent times. Their real-time data have manifested the need to overcome latency and energy costs induced by the data transfer between the processing unit and memory in von Neumann architecture. Therefore, researchers showed interest in building an in-memory-computing (IMC) based alternative paradigm,4−8 where the computation is done inside the memory, reducing the latency and energy cost. The quintessential example of IMC is vector-matrix multiplication (VMM) with nonvolatile memories (NVMs), which is applied to solve many high-level applications such as neuromorphic computing and to solve computationally tricky problems.9−12 During the execution of VMM for neuromorphic computing, the memory unit must perform computations using single-instruction data sets. The memory element used for calculation must be able to encode the data in physically realizable parameters such as charge, current, or voltage with low latency and also must be compatible with the scaling trend.

Among many emerging memory technologies like resistive random access memory (ReRAM)13−15 and phase change memory (PCM),16−19 ferroelectric field effect transistors (FeFETs) seem to be the most promising ones. The pronunciation of ferroelectricity in a single-layer thin film of hafnium oxide (HfO2), fast switching, high on-current (ION) to off-current (IOFF) ratio Inline graphic, excellent linearity in synaptic weight updates, bidirectional operation, and good endurance are the key technological factors that make FeFET superior to other methods.20,23−30,21,22 However, the primary bottleneck in implementing the FeFET-based computing system lies in the intrinsic stochasticity owing to the polycrystalline nature of HfO2-based ferroelectric thin film, as well as inherent defect sites that may capture electrons or holes from the channel side (CS) or gate side (GS).31−33 Numerous efforts have been made to reduce the impacts of such nonidealities from the device process, and a circuit point of view.34−39,23,25 Previously, it has been reported how the quality of the interface and the READ-Voltage play a pivotal role in the performance of FeFETs, especially for low-frequency noise response, retention, and endurance.40,41,25,21,42−44 In this work, we aim to maximize the reliability and performance of FeFETs by adopting a synergistic approach of READ-voltage optimization and interfacial-layer engineering.

This paper begins with the fabrication and characterization of FeFET devices. We have fabricated FeFET devices with two different interfaces, SiON and SiO2. Low-frequency noise, endurance and retention characteristics are used to gauge the impact of IL of the performance of the FeFETs. The noise spectrum, in terms of output power spectral density (SID) and the input gate voltage noise (SvG), are used to characterize the low-frequency noise characteristics. Although we observed that FeFETs based on SiO2 show a wider memory window (MW) and better low-frequency noise response, FeFETs with SiON as IL outperform those with SiO2 as IL in terms of endurance and retention. This phenomenon is discussed in detail in the following sections.

The second part of this article assesses the impact of IL engineering on neuromorphic computing applications. An artificial neural network has two primary operations: (i) training and (ii) inference. The goal of the training operation is to obtain the best possible values for the synaptic weights to minimize the cost function. Therefore, synaptic weights are constantly updated during training operations, necessitating high WRITE endurance in synaptic devices for online training. The other plausible option is offline training of neural networks and carrying out the inference-only operations in the hardware. During offline training, the synaptic weights are optimized in the software and are subsequently written into the hardware. Therefore, stable data-retention capability and low READ variations are necessary for carrying-out inference operations on the hardware without repeated retraining. With the endurance to WRITE limited to 3 × 104 cycles, online training of the neural network (NN) becomes tricky with the synaptic devices manufactured in the synaptic core. Therefore, we have considered an inference-only operation after training the neural network offline for a single time. We observed that optimizing the READ voltage could reduce the impact of low-frequency noise, especially during a READ operation. However, the systematic degradation in long-term data retention becomes crucial for conducting an inference operation without retraining. Devices with SiON interface demonstrate high immunity to such variations and maintain an inference accuracy of over 96% without retraining for MNIST handwritten data sets in the presence of noise and retention degradation.

Experiments

Fabrication

The tested devices are FeFETs prepared on 300 mm bulk-Si wafers with CMOS-compatible industry-standard production tools. The size of the devices under consideration are 1 μm2 (W = 1 μm and L = 1 μm), with 2 nm thick interface material of SiO2 or SiON, and a 10 nm silicon-doped HfO2 (HSO) layer. The transmission electron microscopic (TEM) image in Figure 1 confirms the thickness of the interfacial and ferroelectric layers. The interfacial layer of SiO2 was grown by self-terminating chemical oxidation, and the SiON layer was formed by rapid thermal annealing (RTA). The quintessential process of preparing HfO2 thin film is atomic layer deposition (ALD). The ALD process involves the sequential deposition of a self-limiting monolayer of precursor molecules with an oxidizer. We used HfCl4 with SiCl4 as precursors and H2O as an oxidizing agent during ALD. The ALD of the 10 nm HSO layer was conducted at 300 °C. The cycling ratios for HfCl4 and SiCl4 were 16:1. The top electrode of titanium nitride (TiN) and amorphous silicon was deposited by physical vapor deposition (PVD) and chemical vapor deposition (CVD), respectively. The RTA for crystallization and dopant activation was conducted simultaneously at 1050 °C for 5 s. Figure 1 describes the detailed process flow of device fabrication.

Figure 1.

Figure 1

Open in a new tab

Schematic and process flow of the FeFET devices with a 10 nm Si:HfO2 layer. The inset shows the transmission electron microscopy image of the material stack.

Electrical Characterization

The electrical characterization was conducted using a B1500A Semiconductor Analyzer. The devices were subjected to wake-up cycling by 5 and −4.5 V pulses of 500 ns before READ-WRITE. The fabricated devices were programmed to binary levels using 500 ns pulses at the gate terminal. A positive pulse at the gate terminal of n-type FeFET programs the devices at a low threshold voltage (LVT) state, and the negative pulse programs the device at a high threshold voltage (HVT) state. Each WRITE pulse was preceded by a RESET pulse of 500 ns, which is −5 V for WRITE-1 and 4.5 V for WRITE-0. The drain, source, and bulk terminals were biased at 0 V during the WRITE operation. The WRITE-pulses, applied at the gate terminal, align the ferroelectric dipoles according to their polarity, which manipulates the surface charge density of the channel, the conductance of channel (Gch), and the threshold voltage (Vt). Each state’s Vt was extracted at a constant drain current of 100 nA. A nondisturbing direct current (DC) sweep from −0.5 to +2 V was applied at the gate terminal for the READ operation. The drain to source voltage (Vds) was 100 mV during the READ operation.

Noise and Reliability Characterization

Quintessentially, one observes the low-frequency or flicker noise as the aftermath of the dangling bonds at the semiconductor and gate dielectric interface and the defect states in the dielectric material. In FeFETs, during the READ operation of the FeFETs, the surface charge carriers of the semiconductor can be randomly trapped and detrapped inside the defect states of the dielectric, generating the flicker noise in the drain current. Flicker noise investigation and characterization were performed with a ProPlus noise measurement system along with the low noise amplifiers and the filtering of the system. For considering the ferroelectric influence and different noise behavior of the HVT and LVT states of the device, a more detailed description can be found elsewhere.37 Multiple operating points were set for various measurements focusing on the linear region. We have analyzed input referred or gate input noise (SvG) and output or drain current noise SID. SvG is an important Figure of merit, which provides crucial information regarding the choice of the optimal operating point. The analytical expression of it are given by the relationship Inline graphic.45,46 The parameter gm is the transconductance of the MOSFET and is defined by the change of drain current ID (device output current) to the change of the gate to source voltage Vgs (device input voltage). gm is mathematically represented by, Inline graphic. The output power spectral density represents the drain current change in the frequency domain. The change of the current in time is translated into the frequency domain by Fourier transformation. The power spectral density can be described as Inline graphic. The first term, SVfb, is the flat band voltage spectral density. μeff is the effective mobility, Cox is the effective oxide capacitance, and α is the Coulomb scattering factor. The SvG presentation is a powerful point of view to compare the input noise behavior for an equivalent gate voltage for different technologies and with different interface materials.46 The detailed method of low-frequency noise investigation is demonstrated in our previous work.37

Electric field cycling was applied for endurance measurement with amplitudes in the ±6 V range and a pulse width of 500 ns.

Neural Network Simulation

Finally, the impact of low-frequency noise and retention degradation on FeFETs on their system-level performance, especially for neuromorphic applications, was evaluated by Neurosim simulation platform.47 The experimentally calibrated conductance value with variation statistics was used to simulate the multilevel perception (MLP) neural network (NN) performance with the MNIST data set. The neural network’s architecture is illustrated in Figure 2a. The MLP architecture comprises three layers, which are 400 input nodes, 100 hidden nodes, and 10 nodes in the output layer. In this work, we have considered offline training scenarios of neural networks. Although it has been mentioned in many previous works of literature that online training in the neural network can alleviate the impact of conductance drift of FeFETs,48,49,26,40 it requires high endurance. It is power-hungry.25,50 Therefore, we focus on an inference-only operation with offline neural network training. The back-propagation algorithm with the optimizer Adam was adopted to minimize the cost function during offline training. We have considered the step function as an activation function during forward-propagation and the sigmoid function as an activation function during back-propagation. After offline training, the synaptic weights, in terms of channel conductance of FeFETs, were updated on the hardware using a single-shot programming pulse. The synaptic weights were normalized between the minimum value (Wmin) of −1 and the maximum value (Wmax) of 1. The IOFF of the FeFETs was mapped with Wmin, and the ION was mapped with Wmax. The FeFET-based synaptic core, shown in Figure 2b, is used to carry out the vector–matrix–multiplication operation. The output of the vector–matrix–multiplication is directly digitized by using a current-to-digital converter.47 An additional READ variation parameter simulated the impact of low-frequency noise with experimentally calibrated variation statistics. The impacts of retention degradation were simulated using the experimentally obtained channel conductance value with extrapolation up to 10 years. The cumulative impact was evaluated by turning on all sources of variations during inference operation. The results obtained from the experiments will be discussed in the following sections.

Figure 2.

Figure 2

Open in a new tab

(a) Schematic representation of the neural network architecture used for simulating the performance of FeFET-based synaptic devices. The input is an image of the hand-written digits. To simplify the hardware implementation task, the image is reshaped with a size of 20 × 20 pixels. Therefore, the neural network has 400 input layers, 100 hidden layers, and 10 output layers. (b) Memory array architecture shows the synaptic core used for simulating the inference operation.

Results and Discussion

Parts a and b of Figure 3 show the READ operation conducted after WRITE of the FeFETs with SiON and SiO2 interface. FeFETs with SiON interface show a higher memory window than those with SiO2. This trait can be attributed to the trapping and detrapping phenomena from the interface. Further analysis of the low-frequency noise provides a better insight into the root cause of memory window reduction in SiO2-based FeFETs. However, the device-to-device variation and on-state current (Ion) to off-state current (Ioff) ratio remain almost the same for both of the interfaces.

Figure 3.

Figure 3

Open in a new tab

(a) Transfer characteristics of FeFETs with SiON interface for programmed and erased states show an average memory window of 1.5 V, (b) while the devices with SiO2 interface have an average memory window of 1 V.

The spectral density of the drain current (SID) was measured with an operation point of 100 mV offset from Vt. In an erased and programmed state, the SID noise behavior for the 10 nm HSO SiO2 interface structure is demonstrated up to a frequency of 100 kHz in Figure 4a. In light blue, the single-device measurements are included. Two of these measurements have a low noise level, and a different slope compared to the other single die measurements of the SiO2 interface erases the state measurements; for these, the operating current for the used gate voltage was too low and reached the detection limit of the system. In Figure 4b, SID is shown for the 10 nm HSO SiON structure. For both states, ER and PG, the noise behavior does not show differences in the two states. Compared to dielectric devices in 22 nm technology (investigation on 22 nm FDX device was presented elsewhere45), the noise behavior in the lower frequency area for the PG-state is similar. For the higher frequencies, a difference of two magnitudes can be observed. For the SiO2 interface structure, the noise level reaches higher frequencies than the system limit.

Figure 4.

Figure 4

Open in a new tab

(a) Power spectral density (SID) noise behavior of the 10 nm HSO and SiO2 interface structure. In blue the ferroelectric erase state (ER) and in red the programmed state (PG) are demonstrated. The operating point is set on Vt with an offset of 100 mV. (b) SID noise behavior of the 10 nm HSO and SiON interface structure. ER and PG state are on the same noise level. (c) Current normalized noise behavior with two different structures (one structure with SiON and the other with SiO2 interface material) The noise level change for different operating points is demonstrated for a frequency of 100 Hz in erase state. (d) Equivalent input gate voltage noise (SvG) with two different structures (one structure with SiON and the other with SiO2 interface material) The noise level change for different operating points is demonstrated for a frequency of 100 Hz.

Figure 4c shows the noise current (SID) for different operating points and different interface materials (SiON, SiO2). In direct comparison to the threshold voltage (Vt) operating point, the SiON structure has a higher noise level than the SiO2 structure. The SiON structure shows a decrease in noise level with increasing gate voltage Vg, while for FeFETs with SiO2 interface, the noise level remains the same for different values of Vg.

On the other hand, Figure 4d shows the equivalent input gate voltage noise for different operating points and interface materials. SiON structure shows a continuous decreasing trend with increasing Vg as in the normalized SID, and the SiO2 interface structure has the same level of SvG for different operating points. The difference between SiON and SiO2 for lower Vg operation points is similar in SvG and SID. The change for higher Vg voltages differs. The gate input for higher operating voltage is, for the SiON interface, lower than the total noise level of this structure. For SiO2, an increase in the operating voltage does not influence both.

In HSO-based FeFETs,51,37 a modification of the interface layer has been shown to improve reliability, especially the device’s resistance. Figure 5a visualizes the cycling endurance of FeFETs based on FeFETs based on SiO2 and SiON for a stress voltage amplitude of 6 V. Although continuous degradation of the MW is observed for the SiO2 interface layer, resulting in complete closure at approximately 3 × 104 cycles, the device based on SiON exhibits a stable and comprehensive MW up to 104 cycles. Although there have been several demonstrations of improvement of endurance in HfO2 based ferroelectric films,52,53 the WRITE-endurance of our devices are comparable with the 28 nm HKMG FeFETs from GlobalFoundries’.27 At a higher number of cycles, a walkout of the low Vt state to the high Vt state is observable, most likely caused by trapped charges. Still, an MW exceeding 700 mV remains at 3 × 104 cycles. In the case of retention (see Figure 5b), stable Vt states are observed for both programmed and erased conditions in the case of the SiON-based devices. However, initial detrapping is observable. A back-switching trend is present for devices based on SiO2, as indicated by the green arrow.

Figure 5.

Figure 5

Open in a new tab

(a) Endurance characteristics of SiO2 and SiON-based HSO FeFETs for a stress voltage amplitude of 6 V. (b) Retention of the high- and low Vt state of HSO FeFETs with SiO2 and SiON interface layer.

The origin of improved retention in SiON-based FeFETs can be related to the depolarization field change. Due to the higher relative permittivity of SiON compared to SiO2, the depolarization field is reduced.51 However, (de)trapping behavior for these is not understood in detail. The Flicker noise results here, however, clearly indicate an increased noise level for the SiON devices, close to Vt. This indicates increased trapping and detrapping of charges. As a result, charges can detrap faster after the writing pulse, resulting in an already open MW after writing in the case of SiON interface, whereas the SiO2-based devices show this pronounced detrapping effect. The strong back-switching trend afterward can be explained by the displacement field as mentioned above and additional charge-trapping from the other interface at the electrode, which cannot be detrapped easily due to the presence of the electron pocket in the band structure (see Figure 6).

Figure 6.

Figure 6

Open in a new tab

Schematic illustration of the band structure of a SiO2- (a) and a SiON- (b) based FeFET. An electron pocket is observed at the ferroelectric–insulator interface.

In the case of endurance, a similar origin can be deduced. As for retention, charges are trapped inside the electron pocket in the band structure. As observed in the retention case where an opening of the MW is observed for SiO2-based devices due to initially trapped charges, repeated cycling results in a similar effect, only that, with extensive cycling, many more charges are trapped. As they cannot easily detrap, compared to SiON, a memory closure is observable, as these charges will pin domains and shift the internal bias field. This effect has recently been explored as well for fluorinated interfaces,37 reporting consistent results with the here presented data.

Finally, the cumulative impact of device variation, flicker noise, and retention degradation of FeFETs on neural network applications have been evaluated. We consider inference operations on MLP-NN with MNIST data sets. Only the READ operation is performed during the inference operation. In this case, the retention of the data and the low-frequency noise-induced READ variation become crucial. The software baseline for the inference operation was 98.5%. Figure 7 shows the device-to-device variation (D2D), with the impact of low-frequency noise and retention degradation on the inference accuracy. The high on-current to the off-current ratio in FeFETs with SiON-based IL engenders better inference accuracy in NNs built with them. Low-frequency noise originates from intrinsic defects in the interface and ferroelectric layer, and each defect site has a different ionization energy [TSA_2]. This is why we observe a dependence of noise current and inference accuracy on the bias voltage. However, device variations and low-frequency noise impact are marginal in NNs with a synaptic core built with any type of FeFETs. The retention degradation causes closure of the MW in FeFETs with SiO2IL, which is the pivotal reason behind the failure of them to operate as synaptic devices after aging. We have evaluated the cumulative impact of device variation, low-frequency noise, and retention degradation in the inference accuracy degradation, which shows that MLP-NN built with FeFETs with SiON-based IL shows excellent immunity to all three sources of variations and maintains accuracy over 96% after 10 years of programming without retraining.

Figure 7.

Figure 7

Open in a new tab

Inference accuracy shows that the systematic variation due to retention degradation has a higher impact on the inference operation than the random variation caused by low-frequency noise during the READ operation. The higher on-current to off-current ratio ensures better inference accuracy for MLP-NN built with SiON interfacial layer-based FeFETs as synaptic devices.

Conclusion

We have fabricated FeFET devices with silicon-doped hafnium oxide as a ferroelectric layer. Fabrication was carried out in two different splits with SiO2 and SiON as the interfacial layer between the semiconductor and the ferroelectric layer. Although the FeFET devices with the SiO2 interface demonstrated excellent noise immunity, FeFET with the SiON interface showed a one order increase in the write endurance, without retention penalty. This improvement paved the way for this device to be implemented as the synaptic cells in inference engine applications.

Acknowledgments

The research leading to these results has received funding in part from the European Union’s ECSEL Joint Undertaking under Grant Agreement No. 826655—Project TEMPO and German Bundesministerium für Wirtschaft (BMWi) and the State of Saxony in the frame of the Important Project of Common European Interest (IPCEI), and in part by the ECSEL Joint Undertaking Project ANDANTE, in collaboration with the European Union’s Horizon 2020 Framework Program for Research and Innovation under Grant H2020/2014-2020 and National Authorities under Grant No. 876925.

Author Contributions

Yannick Raffel, Sourav De, and Maximilian Lederer contributed equally to this work.

The authors declare no competing financial interest.

References

  1. LeCun Y.; Boser B.; Denker J. S.; Henderson D.; Howard R. E.; Hubbard W.; Jackel L. D. Backpropagation Applied to Handwritten Zip Code Recognition. Neural Computation 1989, 1, 541–551. 10.1162/neco.1989.1.4.541. [DOI] [Google Scholar]
  2. LeCun Y.; Bottou L.; Bengio Y.; Haffner P. Gradient-based learning applied to document recognition. Proceedings of the IEEE 1998, 86, 2278–2324. 10.1109/5.726791. [DOI] [Google Scholar]
  3. LeCun Y.; Bengio Y.; Hinton G. Deep learning. Nature 2015, 521, 436–444. 10.1038/nature14539. [DOI] [PubMed] [Google Scholar]
  4. Davies M.; Srinivasa N.; Lin T.-H.; Chinya G.; Cao Y.; Choday S. H.; Dimou G.; Joshi P.; Imam N.; Jain S.; Liao Y.; Lin C.-K.; Lines A.; Liu R.; Mathaikutty D.; McCoy S.; Paul A.; Tse J.; Venkataramanan G.; Weng Y.-H.; Wild A.; Yang Y.; Wang H. Loihi: A Neuromorphic Manycore Processor with On-Chip Learning. IEEE Micro 2018, 38, 82–99. 10.1109/MM.2018.112130359. [DOI] [Google Scholar]
  5. Akopyan F.; Sawada J.; Cassidy A.; Alvarez-Icaza R.; Arthur J.; Merolla P.; Imam N.; Nakamura Y.; Datta P.; Nam G.-J.; Taba B.; Beakes M.; Brezzo B.; Kuang J. B.; Manohar R.; Risk W. P.; Jackson B.; Modha D. S. TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2015, 34, 1537–1557. 10.1109/TCAD.2015.2474396. [DOI] [Google Scholar]
  6. Wan W.; Kubendran R.; Schaefer C.; Eryilmaz S. B.; Zhang W.; Wu D.; Deiss S.; Raina P.; Qian H.; Gao B.; Joshi S.; Wu H.; Wong H.-S. P.; Cauwenberghs G. A compute-in-memory chip based on resistive random-access memory. Nature 2022, 608 (7923), 504–512. 10.1038/s41586-022-04992-8. [DOI] [PMC free article] [PubMed] [Google Scholar]
  7. Jung S.; Lee H.; Myung S.; Kim H.; Yoon S. K.; Kwon S. W.; Ju Y.; Kim M.; Yi W.; Han S.; Kwon B.; Seo B.; Lee K.; Koh G. H.; Lee K.; Song Y.; Choi C.; Ham D.; Kim S. J. A crossbar array of magnetoresistive memory devices for in-memory computing. Nature 2022, 601 (7892), 211–216. 10.1038/s41586-021-04196-6. [DOI] [PubMed] [Google Scholar]
  8. De S.; Müller F.; Laleni N.; Soliman T.; Shrivastava A.; Yadav N.; Abdulazhanov S.; Lederer M.; Mojumder S.; Vardar A.; Ali T.; Kirchner T.; Liang F.-X.; Le H.-H.; Baig M. A.; Lu D.; Seidel K.; Kämpfe T. First Demonstration of Ultra-High Precision 4Kb 28nm HKMG 1FeFET-1T Based Memory Array Macro Deep Learning Applications. techrxiv 2022, 1–2. 10.36227/techrxiv.19491212.v1. [DOI] [Google Scholar]
  9. Thunder S.; Pal P.; Wang Y.-H.; Huang P.-T. Ultra Low Power 3D-Embedded Convolutional Neural Network Cube Based on -IGZO Nanosheet and Bi-Layer Resistive Memory. 2021 International Conference on IC Design and Technology (ICICDT) 2021, 1–4. 10.1109/ICICDT51558.2021.9626489. [DOI] [Google Scholar]
  10. De S.; Baig M. A.; Qiu B.-H.; Müller F.; Le H.-H.; Lederer M.; Kämpfe T.; Ali T.; Sung P.-J.; Su C.-J.; Lee Y.-J.; Lu D. D. Random and Systematic Variation in Nanoscale Hf0.5Zr0.5O2 Ferroelectric FinFETs: Physical Origin and Neuromorphic Circuit Implications. Frontiers in Nanotechnology 2022, 3, 1–10. 10.3389/fnano.2021.826232. [DOI] [Google Scholar]
  11. Yin X.; Qian Y.; Imani M.; Ni K.; Li C.; Zhang G. L.; Li B.; Schlichtmann U.; Zhuo C. Ferroelectric Ternary Content Addressable Memories for Energy Efficient Associative Search. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2022, 1–1. 10.1109/TCAD.2022.3197694. [DOI] [Google Scholar]
  12. Annamalai L.; Ramanathan V.; Thakur C. S. Event-LSTM: An Unsupervised and Asynchronous Learning-Based Representation for Event-Based Data. IEEE Robotics and Automation Letters 2022, 7, 4678–4685. 10.1109/LRA.2022.3151426. [DOI] [Google Scholar]
  13. Choi B. J.; Jeong D. S.; Kim S. K.; Rohde C.; Choi S.; Oh J. H.; Kim H. J.; Hwang C. S.; Szot K.; Waser R.; Reichenberg B.; Tiedke S. Resistive switching mechanism of TiO2 thin films grown by atomic-layer deposition. J. Appl. Phys. 2005, 98 (3), 033715. 10.1063/1.2001146. [DOI] [Google Scholar]
  14. Linn E.; Rosezin R.; Kügeler C.; Waser R. Complementary resistive switches for passive nanocrossbar memories. Nat. Mater. 2010, 9 (5), 403–406. 10.1038/nmat2748. [DOI] [PubMed] [Google Scholar]
  15. Wedig A.; Luebben M.; Cho D.-Y.; Moors M.; Skaja K.; Rana V.; Hasegawa T.; Adepalli K. K.; Yildiz B.; Waser R.; Valov I. Nanoscale cation motion in TaOx, HfOx and TiOx memristive systems. Nat. Nanotechnol. 2016, 11 (1), 67–74. 10.1038/nnano.2015.221. [DOI] [PubMed] [Google Scholar]
  16. Cheng H.-Y.; Carta F.; Chien W.-C.; Lung H.-L.; Brightsky M.-J. 3D cross-point phase-change memory for storage-class memory. J. Phys. D: Appl. Phys 2019, 52, 473002. 10.1088/1361-6463/ab39a0. [DOI] [Google Scholar]
  17. Sebastian A.; Le Gallo M. L.; Burr G. W.; Kim S.; Brightsky M.; Eleftheriou E. Tutorial: Brain-inspired computing using phase-change memory devices. J. Appl. Phys. 2018, 124 (11), 111101. 10.1063/1.5042413. [DOI] [Google Scholar]
  18. Kau D.; Tang S.; Karpov I. V.; Dodge R.; Klehn B.; Kalb J. A.; Strand J.; Diaz A.; Leung N.; Wu J.; Lee S.; Langtry T.; Chang K. W.; Papagianni C.; Lee J.; Hirst J.; Erra S.; Flores E.; Righos N.; Castro H.; Spadini G. A stackable cross point phase change memory. 2009 IEEE International Electron Devices Meeting (IEDM) 2009, 1–4. 10.1109/IEDM.2009.5424263. [DOI] [Google Scholar]
  19. Qiao B.-W.; Feng J.; Lai Y.-F.; Cai Y.-F.; Lin Y.-Y.; Tang T.-G.; Cai B.-C.; Chen B. Phase-change memory device using Si-Sb-Te film for low power operation and multibit storage. J. Electron. Mater. 2007, 36 (1), 88. 10.1007/s11664-006-0024-1. [DOI] [Google Scholar]
  20. Müller J.; Böscke T. S.; Schröder U.; Mueller S.; Bräuhaus D.; Böttger U.; Frey L.; Mikolajick T. Ferroelectricity in Simple Binary ZrO2 and HfO2. Nano Lett. 2012, 12, 4318–4323. 10.1021/nl302049k. [DOI] [PubMed] [Google Scholar]
  21. De S.; Baig M. A.; Qiu B.-H.; Le H.-H.; Lee Y.-J.; Lu D. Neuromorphic Computing with Fe-FinFETs in the Presence of Variation. 2022 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2022, 1–2. 10.1109/VLSI-TSA54299.2022.9771015. [DOI] [Google Scholar]
  22. Ali T.; Polakowski P.; Kühnel K.; Czernohorsky M.; Kämpfe T.; Rudolph M.; Pätzold B.; Lehninger D.; Müller F.; Olivo R.; Lederer M.; Hoffmann R.; Steinke P.; Zimmermann K.; Mühle U.; Seidel K.; Müller J. A Multilevel FeFET Memory Device based on Laminated HSO and HZO Ferroelectric Layers for High-Density Storage. 2019 IEEE International Electron Devices Meeting (IEDM) 2019, 28.7.1–28.7.4. 10.1109/IEDM19573.2019.8993642. [DOI] [Google Scholar]
  23. Ali T.; Olivo R.; Kerdils S.; Lehninger D.; Lederer M.; Sourav D.; Royet A.-S.; Sünbül A.; Prabhu A.; Kühnel K.; Czernohorsky M.; Rudolph M.; Hoffmann R.; Charpin-Nicolle C.; Grenouillet L.; Kämpfe T.; Seidel K. Study of Nanosecond Laser Annealing on Silicon Doped Hafnium Oxide Film Crystallization and Capacitor Reliability. 2022 IEEE International Memory Workshop (IMW) 2022, 1–4. 10.1109/IMW52921.2022.9779281. [DOI] [Google Scholar]
  24. De S.; Lederer M.; Raffel Y.; Müller F.; Seidel K.; Kämpfe T.. Roadmap for Ferroelectric Memory: Challenges and Opportunities for IMC Applications. In Internation SoC Conference 2022; pp 1–2.
  25. De S.; Müller F.; Le H.-H.; Lederer M.; Raffel Y.; Ali T.; Lu D.; Kämpfe T. READ-Optimized 28nm HKMG Multibit FeFET Synapses for Inference-Engine Applications. IEEE Journal of the Electron Devices Society 2022, 10, 637–641. 10.1109/JEDS.2022.3195119. [DOI] [Google Scholar]
  26. De S.; Qiu B.-H.; Bu W.-X.; Baig M. A.; Su C.-J.; Lee Y.-J.; Lu D.. Neuromorphic Computing with Deeply Scaled Ferroelectric FinFET in Presence of Process Variation, Device Aging and Flicker Noise. arXiv 2021; abs/2103.13302, pp 1–4; https://arxiv.org/abs/2103.13302.
  27. Trentzsch M.; Flachowsky S.; Richter R.; Paul J.; Reimer B.; Utess D.; Jansen S.; Mulaosmanovic H.; Müller S.; Slesazeck S.; Ocker J.; Noack M.; Müller J.; Polakowski P.; Schreiter J.; Beyer S.; Mikolajick T.; Rice B. A 28nm HKMG super low power embedded NVM technology based on ferroelectric FETs. 2016 IEEE International Electron Devices Meeting (IEDM) 2016, 11.5.1–11.5.4. 10.1109/IEDM.2016.7838397. [DOI] [Google Scholar]
  28. De S.; Le H.-H.; Qiu B.-H.; Baig M. A.; Sung P.-J.; Su C.-J.; Lee Y.-J.; Lu D. D. Robust Binary Neural Network Operation From 233 K to 398 K via Gate Stack and Bias Optimization of Ferroelectric FinFET Synapses. IEEE Electron Device Lett. 2021, 42, 1144–1147. 10.1109/LED.2021.3089621. [DOI] [Google Scholar]
  29. Lederer M.; Kämpfe T.; Ali T.; Müller F.; Olivo R.; Hoffmann R.; Laleni N.; Seidel K. Ferroelectric Field Effect Transistors as a Synapse for Neuromorphic Application. IEEE Trans. Electron Devices 2021, 68, 2295–2300. 10.1109/TED.2021.3068716. [DOI] [Google Scholar]
  30. Jerry M.; Chen P.; Zhang J.; Sharma P.; Ni K.; Yu S.; Datta S. Ferroelectric FET analog synapse for acceleration of deep neural network training. 2017 IEEE International Electron Devices Meeting (IEDM) 2017, 6.2.1–6.2.4. 10.1109/IEDM.2017.8268338. [DOI] [Google Scholar]
  31. Dünkel S.; Trentzsch M.; Richter R.; Moll P.; Fuchs C.; Gehring O.; Majer M.; Wittek S.; Müller B.; Melde T.; Mulaosmanovic H.; Slesazeck S.; Müller S.; Ocker J.; Noack M.; Löhr D.-A.; Polakowski P.; Müller J.; Mikolajick T.; Höntschel J.; Rice B.; Pellerin J.; Beyer S. A FeFET based super-low-power ultra-fast embedded NVM technology for 22nm FDSOI and beyond. 2017 IEEE International Electron Devices Meeting (IEDM) 2017, 19.7.1–19.7.4. 10.1109/IEDM.2017.8268425. [DOI] [Google Scholar]
  32. Alam M. N. K.; Kaczer B.; Ragnarsson L.-Å.; Popovici M.; Rzepa G.; Horiguchi N.; Heyns M.; Van Houdt J. On the Characterization and Separation of Trapping and Ferroelectric Behavior in HfZrO FET. IEEE Journal of the Electron Devices Society 2019, 7, 855–862. 10.1109/JEDS.2019.2902953. [DOI] [Google Scholar]
  33. Bersuker G.; Sim J. H.; Park C. S.; Young C. D.; Nadkarni S. V.; Choi R.; Lee B. H. Mechanism of electron trapping and characteristics of traps in HfO2 gate stacks. EEE Transactions on Device and Materials Reliability 2007, 7, 138–145. 10.1109/TDMR.2007.897532. [DOI] [Google Scholar]
  34. De S.; Qiu B.-H.; Bu W.-X.; Baig M. A.; Sung P.-J.; Su C.-J.; Lee Y.-J.; Lu D.-D. Uniform Crystal Formation and Electrical Variability Reduction in Hafnium-Oxide-Based Ferroelectric Memory by Thermal Engineering. ACS Appl. Electron. Mater. 2021, 3 (2), 619–628. 10.1021/acsaelm.0c00610. [DOI] [Google Scholar]
  35. Ali T.; Kühnel K.; Olivo R.; Lehninger D.; Müller F.; Lederer M.; Rudolph M.; Oehler S.; Mertens K.; Hoffmann R.; Zimmermann K.; Schramm P.; Metzger J.; Binder R.; Czernohorsky M.; Kämpfe T.; Seidel K.; Müller J.; Van Houdt J.; Eng L. M. Impact of the Ferroelectric Stack Lamination in Si Doped Hafnium Oxide (HSO) and Hafnium Zirconium Oxide (HZO) Based FeFETs: Toward High-Density Multi-Level Cell and Synaptic Storage. Electronic Materials 2021, 2, 344–369. 10.3390/electronicmat2030024. [DOI] [Google Scholar]
  36. Lederer M.; Bagul P.; Lehninger D.; Mertens K.; Reck A.; Olivo R.; Kämpfe T.; Seidel K.; Eng L. M. Influence of Annealing Temperature on the Structural and Electrical Properties of Si-Doped Ferroelectric Hafnium Oxide. ACS Appl. Electron. Mater. 2021, 3, 4115–4120. 10.1021/acsaelm.1c00590. [DOI] [Google Scholar]
  37. Raffel Y.; Olivo R.; Lederer M.; Müller F.; Hoffmann R.; Ali T.; Mertens K.; Pirro L.; Drescher M.; Beyer S.; Kämpfe T.; Seidel K.; Eng L. M.; Heitmann J.; et al. Endurance improvements and defect characterization in ferroelectric FETs through interface fluorination. 2022 IEEE International Memory Workshop (IMW) 2022, 1–4. 10.1109/IMW52921.2022.9779277. [DOI] [Google Scholar]
  38. Ali T.; Mertens K.; Olivo R.; Lehninger D.; Lederer M.; Müller F.; Rudolph M.; Oehler S.; Kühnel K.; Hoffmann R.; Schramm P.; Czernohorsky M.; Kämpfe T.; Seidel K. Impact of Stack Structure Control and Ferroelectric Material Optimization in Novel Laminate HSO and HZO MFMIS FeFET. 2022 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2022, 1–2. 10.1109/VLSI-TSA54299.2022.9771003. [DOI] [Google Scholar]
  39. De S.; Bu W.-X.; Qiu B.-H.; Su C.-J.; Lee Y.-J.; Lu D. D. Alleviation of Charge Trapping and Flicker Noise in HfZrO2-Based Ferroelectric Capacitors by Thermal Engineering. 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2021, 1–2. 10.1109/VLSI-TSA51926.2021.9440091. [DOI] [Google Scholar]
  40. De S.; Lu D. D.; Le H.-H.; Mazumder S.; Lee Y.-J.; Tseng W. C.; Qiu B.-H.; Baig A.; Sung P.-J.; Su C.-J.; Wu C. T.; Wu W. F.; Yeh W.-K.; Wang Y.-H.. Ultra-Low Power Robust 3bit/cell Hf0.5Zr0.5O2 Ferroelectric FinFET with High Endurance for Advanced Computing-In-Memory Technology. In IEEE 2021 Symposia on VlSI Circuits and Technology; 2021; pp 11–12.
  41. Tan A. J.; Liao Y.-H.; Wang L.-C.; Shanker N.; Bae J.-H.; Hu C.; Salahuddin S. Ferroelectric HfO2Memory Transistors With High- Interfacial Layer and Write Endurance Exceeding 1010 Cycles. IEEE Electron Device Lett. 2021, 42, 994–997. 10.1109/LED.2021.3083219. [DOI] [Google Scholar]
  42. Raffel Y.; Thunder S.; Lederer M.; Olivo R.; Hoffmann R.; Pirro L.; Beyer S.; Chohan T.; Huang P.-T.; De S.; Kämpfe T.; Seidel T.; Heitmann J. Interfacial Layer Engineering to Enhance Noise Immunity of FeFETs for IMC Applications. TechRxiv 2022, 1–4. 10.36227/techrxiv.19950497.v1. [DOI] [PMC free article] [PubMed] [Google Scholar]
  43. Zeng B.; Liao M.; Liao J.; Xiao W.; Peng Q.-X.; Zheng S.; Zhou Y. Program/Erase Cycling Degradation Mechanism of HfO2-Based FeFET Memory Devices. IEEE Electron Device Lett. 2019, 40, 710–713. 10.1109/LED.2019.2908084. [DOI] [Google Scholar]
  44. Peng H.-K.; Kao T.-H.; Kao Y.-C.; Wu P.-J.; Wu Y.-H. Reduced Asymmetric Memory Window Between Si-Based n- and p-FeFETs With Scaled Ferroelectric HfZrO and AlON Interfacial Layer. IEEE Electron Device Lett. 2021, 42, 835–838. 10.1109/LED.2021.3074434. [DOI] [Google Scholar]
  45. Raffel Y.; Seidel K.; Pirro L.; Lehmann S.; Hoffmann R.; Olivo R.; Kämpfe T.; Heitmann J. Impact of Channel Implant Variation on RTN and Flicker Noise. 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) 2020, 1–4. 10.1109/EUROSOI-ULIS49407.2020.9365296. [DOI] [Google Scholar]
  46. Haartman M.; Östling M.. Low-frequency noise in advanced MOS devices; Springer Science & Business Media: 2007. [Google Scholar]
  47. Chen P.-Y.; Peng X. C.; Yu S. NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures. 2017 IEEE International Electron Devices Meeting (IEDM) 2017, 6.1.1–6.1.4. 10.1109/IEDM.2017.8268337. [DOI] [Google Scholar]
  48. De S.; Baig M. A.; Qiu B.-H.; Lu D.; Sung P.-J.; Hsueh F. K.; Lee Y.-J.; Su C.-J. Tri-Gate Ferroelectric FET Characterization and Modelling for Online Training of Neural Networks at Room Temperature and 233K. 2020 Device Research Conference (DRC) 2020, 1–2. 10.1109/DRC50226.2020.9135186. [DOI] [Google Scholar]
  49. Baig M. A.; Le H.-H.; De S.; Chang C.-W.; Hsieh C.-C.; Huang X.-S.; Lee Y.-J.; Lu D. D. Compact model of retention characteristics of ferroelectric FinFET synapse with MFIS gate stack. Semicond. Sci. Technol. 2021, 37 (2), 1–7. 10.1088/1361-6641/ac3f22. [DOI] [Google Scholar]
  50. De S.; Thunder S.; Lehninger D.; Jank M. P. M.; Lederer M.; Raffel Y.; Seidel K.; Kämpfe T.. Low-Power Vertically Stacked One Time Programmable Multi-bit IGZO-Based BEOL Compatible Ferroelectric TFT Memory Devices with Lifelong Retention for Monolithic 3D-Inference Engine Applications. In 2022 European Solid-state Devices and Circuits Conference, 2022; ESSDERC: 2022; pp 1–4.
  51. Ali T.; Polakowski P.; Riedel S.; Büttner T.; Kämpfe T.; Rudolph M.; Pätzold B.; Seidel K.; Löhr D.; Hoffmann R.; Czernohorsky M.; Kühnel K.; Steinke P.; Calvo J.; Zimmermann K.; Müller J. High Endurance Ferroelectric Hafnium Oxide-Based FeFET Memory Without Retention Penalty. IEEE Trans. Electron Devices 2018, 65, 3769–3774. 10.1109/TED.2018.2856818. [DOI] [Google Scholar]
  52. Liu W.-Y.; Liao J.-J.; Jiang J.; Zhou Y.-C.; Chen Q.; Mo S.-T.; Yang Q.; Peng Q.-X.; Jiang L.-M. Highly stable performance of flexible Hf0.6Zr0.4O2 ferroelectric thin films under multi-service conditions. J. Mater. Chem. C 2020, 8 (11), 3878–3886. 10.1039/C9TC05157K. [DOI] [Google Scholar]
  53. Zhou P.; Zeng B.; Yang W.; Liao J.-J.; Meng F.; Zhang Q.; Gu L.; Zheng S.; Liao M.; Zhou Y. Intrinsic 90°charged domain wall and its effects on ferroelectric properties. Acta Mater. 2022, 232, 117920. 10.1016/j.actamat.2022.117920. [DOI] [Google Scholar]

Articles from ACS Applied Electronic Materials are provided here courtesy of American Chemical Society

RESOURCES