A 30% Efficient High-Output Voltage Fully Integrated Self-Biased Gate RF Rectifier Topology for Neural Implants

Abstract

This paper presents a fully integrated RF energy harvester (EH) with 30% end-to-end power harvesting efficiency (PHE) and supports high output voltage operation, up to 9.3V, with a 1.07 GHz input and under the electrode model for neural applications. The EH is composed of a novel 10-stage self-biased gate (SBG) rectifier with an on-chip matching network. The SBG topology elevates the gate-bias of transistors in a non-linear manner to enable higher conductivity. The design also achieves >20% PHE range of 12-dB. The design was fabricated in 65 nm CMOS technology and occupies an area of 0.0732-mm² with on-chip matching network. In addition to standalone EH characterization measurement results, animal tissue stimulation test was performed to evaluate its performance in a realistic neural implant application.

I. INTRODUCTION

RF Energy-harvesting has emerged as a viable option to support energy needs of implantable biomedical systems. It can enable applications otherwise not possible because it avoids the need for frequent invasive surgeries to replace batteries in otherwise battery operated implants. Some of these implantable medical devices (IMDs) are used to deliver electrical pulses to stimulate neural cells, such as for retinal prostheses and closed-loop epilepsy control [1], [2]. These devices also require smaller size, high-efficiency energy harvesting, and often a higher output voltage to support stimulation [3]. Specifically, maintaining a small size of the device is important to fit into animal or human tissue without damaging or displacing adjoining tissues. Furthermore, the power consumption of the device should not be higher than the safety limit dictated by the Federal Communications Commission (FCC). A high efficiency power conversion is essential to utilize the limited amount of available power in the application space. High output voltage sometimes is also preferred as more energy can be stored on a capacitor at the output of the device. The higher available charge is often necessary to activate neurons for the generation of action potentials.

Sufficient amount of charge transfer within a defined time window, known as the charge density [4], [5], is needed to generate action potentials. However, the amount of charge transfer relies heavily on the voltage and impedance of the tissue. With the impedance of the tissue often being uncertain and variable, the total delivered charge through the electrode cannot be accurately estimated. Researchers have addressed this problem using closed-loop supply control to automatically adjust the stimulation compliance voltage or the electrode current [6], [7]. Charge balancing techniques are also proposed in [8] for a safe biphasic stimulation.

Most proposed electrical stimulators adopt conventional rectifier or regulators as the backbone to provide high DC power for the electrode using a wireless link. Since the available RF power decreases rapidly with distance, it is desirable to design rectifiers that are able to operate with low incident power [9]-[13]. In [14], authors proposed the threshold compensated method to deal with the well known “dead zone” of rectifiers by lifting up the gate voltage of the pumping transistor from the subsequent node such that gate-to-source voltage is higher than the threshold voltage, however this also increases the leakage current when the transistor is reverse biased. Recent works [11], [13] optimized this compensation method by introducing extra biasing transistors in order to increase the forward current and reduce reverse leakage current. However, this biasing is achieved using forward biased MOS-diodes, which loads the rectifying stages. As the input power increases, the bias current also increases, leading to a reduced efficiency. These compensation techniques can only be optimized for a smaller range of input power and have a reduced high-PHE range. Body-biasing based threshold voltage compensation methods have also been proposed where negative body bias is introduced to improve diode’s conductivity [15], [16]. Reconfigurable rectifier architectures have also been proposed to deal with the wide input power range [10], [12]. Specifically, they have been used for maximum power tracking (MPT). However, the MOS-diode’s “dead-zone” issue still has to be addressed.

High-efficiency rectifiers suit the high integration needs for IMDs. However, they also require the matching network (MN) to be integrated on-chip. Large matching inductors or capacitors that consume large area cannot be easily integrated. A proper input impedance matching of the rectifier should be considered during the design of the rectifier while keeping area constraints in mind. Fig. 1 visualizes our envisioned wireless nano-scale neural implantable system [17]. It includes a magnetoelectric antenna (ME) antenna [18] (sized 30 μm 200 μm, input impedance of 88Ω), an on-chip matching network (MN), and a high-efficiency RF-DC rectifier for neural stimulation. To enable joint simulations of ME antennas and integrated circuits during the design process, we have created and validated an ME antenna model [19], [20]. The complete system can be realized with a small form-factor, minimizing surgical invasiveness and reducing the foreign body responses. And the integrated electrodes of the IMD often have a high impedance and require a high rectified voltage across to drive the current needed for neuromodulation.

Fig. 1:

Overview of the neural recording and RF energy harvesting application.

In this paper, we present a new self-biased gate (SBG) rectifier with a non-linear gate biasing technique. At lower power levels, the SBG rectifier drops the entirety of output voltage to create a higher gate bias. However, to address the issue of leakage at higher input power levels, the gate-biasing technique drops only a fraction of the output voltage. This approach helps to realize high efficiency across input power range. Our design also employs an on-chip matching network (MN). The fully integrated, high-efficiency SBG-based RF energy harvesting circuit can also provide a high output voltage of 9.3 V with a 30% end-to-end efficiency (PHE). Specifically, our work achieves high efficiency at higher output voltage in a multi-stage design, consuming a small area for neural implant applications.

II. Background

A conventional on-chip Dickson multiplier uses half-wave rectifiers implemented with MOS transistor diodes. A major issue with MOS transistor diodes is that they do not conduct well for input voltages less than V_TH and operate only partially in the forward conduction mode. This results in a “dead-zone” problem and reduces its efficiency. To address this issue, threshold voltage compensation methods have been employed [11], [13], [14], [21]. Fig. 2(a) shows the conceptual implementation of this method. A positive gate-bias voltage (V_B) is added between drain and gate of the half-wave stage. This introduces an additional DC voltage at the gate of the transistor that compensates the impact of V_TH. Fig. 2(c) shows how gate voltage (V_G) swings above V_B to improve the diode’s conductivity in forward conduction mode. Nonetheless, an ideal implementation of compensation voltage, as shown in Fig. 2(a) is not feasible. Designs often suffer from either higher compensation resulting into conduction in the reverse conduction mode, or from lower compensation resulting into poor conduction in the forward conduction mode.

Fig. 2:

Voltage compensation methods for rectifier operation.

In the earliest implementations of threshold compensation methods, the DC output level of next or later diode stages were used to bias the gate of the current half-wave stage [14], [22]. However, at higher power levels, this bias voltage becomes large, leading to conduction even in the reverse conduction phase. Adaptive biasing techniques have recently been employed to adjust biasing needs based on the input power level [11], [13]. However, these techniques require more complicated biasing structures and a quiescent current for biasing that is derived from the output of rectifying stages. A non-linear biasing technique is needed to adjust biasing according to the input power to provide sufficient bias for lower power and overcome the leakage issue at higher power.

We present the SBG rectifier that employs a non-linear compensation voltage. Fig. 2(b) shows a simplified conceptual implementation of this SBG rectifier. A variable DC-biasing through a high-impedance structure is employed to realize non-linear biasing (Fig. 2d). The biasing voltage increases at lower input power but saturates at high input power to overcome the conduction issue in the reverse bias phase. The AC swing of the input is maintained over this variable bias using a bypass capacitor (C_B). It uses the gate-leakage current for biasing to enable both, high-impedance and extremely low quiescent current.

III. Self-biased Gate Rectifier

Fig. 3 shows the schematic of a single stage of the proposed SBG rectifier. The proposed topology is different from a classical Dickson-stage [23] rectifier with the most distinctive feature being the gate biasing of the pumping transistor M₁. The topology enhances the gate bias of transistor M₁ by DC-biasing it through the output. The gate voltage of M₁ (V₂) is AC-coupled to the input using the coupling capacitor C_F2, and the node 1 voltage (V₁) is in phase with input signal since C_F2,F1 are much larger than transistor’s parasitic capacitance. The DC level of V₂ is determined by DC_OUT through the back-to-back diode-connected transistors M₃ and M₄. This is a high impedance path such that the DC level of the gate of M₁ will slowly charge up through the small leakage current from DC_OUT. This small current does not increase the load current at the output. It also helps in dropping a fraction of the output voltage to the gate in order to maintain appropriate biasing. The effectiveness of this technique can be studied by analyzing the operating conditions as follows below.

Fig. 3:

Schematic of the proposed SBG rectifier.

A. Analysis of the SBG Stage

The gate-bias voltage V₂ is determined by the leakage current of M₃ and M₄ and the gate-leakage of transistor M₁. The gate leakage current density (J_G), using a semi-empirical formula [24], is given by

$$J_G=\frac{q^2}{8\pi hϵ{\varphi }_B}C\cdot e\{-\frac{8\pi \sqrt{2m}(q{\varphi }_B{)}^{\frac{3}{2}}}{3hq\mid E\mid }[1-(1-\frac{\mid V\mid }{{\varphi }_B}{)}^{\frac{3}{2}}]\}$$

where q is charge, h is Planck’s constant, ϵ is permitivity, ϕ_B is the tunneling barrier height, m is the carrier mass, V is the voltage, E is the electric field, and C is the correction factor to correct Schuegraf’s tunneling model [25], which is inversely proportional to t_ox and propotional to gate voltage. For our circuit ∣V∣ > 0 and E ≈ V/t_ox, where t_ox is the oxide thickness. Further, the binomial expansion of (1 + x)^3/2 is

$$(1+x{)}^{\frac{3}{2}}=1+\frac{3}{2}x+\frac{3}{8}{x}^2-\frac{1}{16}{x}^3+\frac{3}{128}{x}^4\dots$$ (1)

Using $x=-\frac{V}{{\varphi }_B}$ and ignoring the higher order terms because of the rapid increase in the> magnitude of denominator coefficients, the gate current I_G can be written as

$$I_G=\frac{q^{2}WL}{8\pi hϵ{\varphi }_B}C\cdot e\{-\frac{8\pi \sqrt{2m}(q{\varphi }_B{)}^{\frac{3}{2}}{t}_{ox}}{3hqV}[\frac{3}{2}\frac{V}{{\varphi }_B}-\frac{3}{8}(\frac{V}{{\varphi }_B}{)}^2]\}$$

which can be simplified and the gate current of M₄, I_G,M4 can be written as

$$I_{G,M4}=\frac{q^{2}WL}{8\pi hϵ{\varphi }_B}C\cdot e\{-\frac{4\pi \sqrt{2mq{\varphi }_B}{t}_{ox}}{h}[1-\frac{1}{4}\frac{V}{{\varphi }_B}]\}$$ (2)

The above equation translates to a gate leakage current that is inversely proportional to the oxide-thickness (t_ox) and gate oxide voltage V, both being expected outcomes. The sub-threshold leakage of M₃ and M₄ is needed to determine the bias voltage of M₁. The sub-threshold leakage current flowing through M₄ is exponentially dependent on its small gate-source voltage, and can be given approximately by

$$I_{D,M4}=I_S{e}^{(V_{GS,M4}-V_{TH})∕\eta V_t}(1-e^{-V_{GS,M4}∕V_t})$$

where the V_GS,M4 = V_DS,M4 condition was used for M₄. V_GS,M4 will be small, which leads to a simplified expression for the leakage current:

$$I_{D,M4}=I_S{e}^{(V_{GS,M4}-V_{TH})∕\eta V_t}$$ (3)

Since the same current flows through the gate of M₁ and drain of M₄ (i.e., I_D,M4 = I_G,M1), the following equality can be written based on the gate leakage current density:

$$\begin{gathered} \frac{q^{2}WL}{8\pi hϵ{\varphi }_B}C\cdot e\{-\frac{4\pi \sqrt{2mq{\varphi }_B}{t}_{ox}}{h}[1-\frac{1}{4}\frac{V}{{\varphi }_B}]\} \\ =I_S{e}^{(V_{GS,M4}-V_{TH})∕\eta V_t} \end{gathered}$$

$$-\frac{4\pi \sqrt{2mq{\varphi }_B}{t}_{ox}}{h}[1-\frac{1}{4}\frac{V}{{\varphi }_B}]\}=(V_{GS,M4}-V_{TH})∕\eta V_t+lnK$$

where K is given by

$$K=\frac{I_{S}8\pi hϵ{\varphi }_B}{q^{2}WL}$$ (4)

Further simplifying the equation by replacing V = V₂ and V_GS,M4 = V₄ − V₃, we obtain the following relationship:

$$V_2=A+\frac{4{\varphi }_B}{V_t}\cdot (V_4-V_3-\frac{V_{TH}}{V_t})$$ (5)

were A is given by

$$A=4\cdot {\varphi }_B(lnK-\frac{4\pi \sqrt{2mq{\varphi }_B}{t}_{ox}}{h})$$

Equation (5) relates the gate voltage of M₁ to voltage V₄ and V₃. We now need to find one more relationship between V₂, V₃, and V₄ owing to the leakage current of M₃. V_GS of M₃ is equal to zero for the DC operating condition as gate and source are tied together. I_D,M3 is given by

$$I_{D,M3}=I_S{e}^{(0-V_{TH})∕\eta V_t}(1-e^{-V_{DS,M3}∕V_t})(1+\lambda V_{DS,M3})$$ (6)

Since V_DS is expected to be higher than 100mV for high-voltage conditions, we can write I_D,M3 as

$$I_{D,M3}=I_S{e}^{-V_{TH}∕\eta V_t}(1+\lambda V_{DS,M3})$$ (7)

With I_D,M3 = I_D,M4 based on Kirchhoff’s current law, it follows from equations (4) and (9) that

$$I_S{e}^{(V_{GS,M4}-V_{TH})∕\eta V_t}=I_S{e}^{-V_{TH}∕\eta V_t}(1+\lambda V_{DS,M3})$$ (8)

which solves to

$$\frac{V_{GS,M4}}{\eta V_t}=ln(1+\lambda V_{DS,M3})$$ (9)

where we use long transistors for M₄ and M₃ (λV_DS << 1) together with ln(1 + x) ≈ x. Furthermore, using V_GS,M4 = V₄ − V₃ and V_DS,M3 = V₃ − V₂, it can be obtained that

$$V_4-V_3=\eta V_t\lambda (V_3-V_2)$$ (10)

Since λ is a small quantity, eq. (10) confirms that the gate-source voltage of M₄ is much smaller than the drain-source voltage of M₃. Furthermore, equations (10) and (5) show that V₂ is a linear function of V₄ and V₃, implying that both V₂ and V₃ are linearly dependent on the output voltage V₄. Therefore, we can write the gate voltage of M₁ as

$$V_2=\alpha \cdot V_4-\beta V_{TH}+\gamma$$ (11)

where α, β and γ can be obtained analytically but are not included here for brevity. Finally, eq. (11) reveals that gate voltage of M₁ is also linearly dependent on V₄ and V_Th. It should show a linear variation with V₄ and a normal process distribution due to V_TH. The negative coefficient for V_TH indicates that V₂ will decrease with an increase in threshold voltage, which is also an expected outcome owed to the decrease in leakage current.

Eq. (11) shows that V₂ is linearly dependent on V₄, i.e., the DC_OUT level despite of the exponential dependencies of the leakage currents. We simulated the DC operating condition for the SBG stage. Fig. 4 shows shows the gate voltage as a function of V₄ indicating a linear behavior. Furthermore, the difference between V₂ and V₄ is small for lower voltages, but increases at high voltage as expected from the analysis. Fig. 5 displays the temperature and process variation of V₂ at 0.5V DC_OUT and room temperature (27°C) respectively. At higher temperature, leakage increases exponentially and causes V₂ to increase. We anticipate smaller temperature variation for biomedical application. The process distribution of V₂ shows a normal distribution. This is because of the linear dependence of V₂ on V₄. The process variation is largely dominated by threshold voltage V_TH variation, which increases in technologies with shorter channel lengths [26]. Both simulation results confirm the above analysis. Further, we used a device size of 8μ/60n for M₁ (Fig. 3) whose gate settles through the leakage. The device size of M₁ presents a <10fF capacitive load to be charged through transistor leakage(s). Considering 100s of pA of leakage current through M₃ and M₄, and C_F2 = 208 fF, it will take approximately a few ms to several ms to charge the gate voltage to the steady state (Fig. 4, V₂) depending on the operating condition. The SBG topology has higher settling time to be more efficient in the steady state than Dickson or other forward V_TH compensation method. However, it starts with a behavior like a Dickson rectifier and its performance improves as the output voltage increases. Further, the settling time of the gate still remains lower or comparable to the overall settling time of the output voltage which sees a 25nF output capacitor. The SBG design improves over prior art by ensuring that a higher fraction of the output voltage drops at the gate for lower power levels, while dividing the drop to a lower fraction for higher power levels. This will improve the overall efficiency of the converter across a range of input power levels.

Fig. 4:

Simulation of the gate-voltage (V₂) and the difference (V₄ − V₂) vs. output voltage level (V₄).

Fig. 5:

Process and temperature variation of V₂ when simulated at V₄ = 500mV.

We compared the SBG architecture with the V_TH-compensation technique reported in [14]. Fig. 6 shows the simulation-based comparison of the SBG rectifier with the V_TH-compensation technique. Both designs are optimized and four stages are used because the V_TH-compensation technique requires at least two stages to utilize the high output voltage to bias the gates of the lower-stage diodes. The V_TH-compensation method directly drops the output voltage from the successive stages to the gate. Therefore, it improves the efficiency owing to the elevated bias. However, as the input voltage increases, the bias becomes large enough to keep the diode on even in the reversed bias phase, leading to degraded efficiency. In comparison, the SBG stage drops the output voltage non-linearly, i.e., when the output voltage is low, it drops almost all of it at the gate to elevate the bias. However, as the voltage increases, the bias appearing at the gate is divided due to the gate-leakage of the transistor, which helps in maintaining the appropriate bias at the gate of the diode. This aids to achieve the high efficiency of the SBG rectifier. Fig. 6 shows the simulation results of this comparison. The V_TH-compensation technique has higher efficiency for lower input voltage, but the efficiency drops as the input voltage increases.

Fig. 6:

Performance comparison of a 4-stage SBG design with a 4-stage, order-2 V_TH-compensated design as reported in [14].

We also conducted a simulated performance comparison of the SBG rectifier with a Dickson multiplier. Fig. 7 shows the simulated output voltage and efficiency improvement for different input power levels. Our SBG design achieves a 23% efficiency improvement (Δη = η_SBG − η_DCK) over a Dickson stage at 0 dBm. Fig. 8 shows the output voltage with a fixed 100kΩ load at a 900mV input swing. The gate voltage of the SBG has a DC bias that slowly ramps up creating a higher conductive path for the SBG diode. The Dickson stage gate voltage quickly charges but overall DC bias is higher for SBG stage. Fig. 8 shows the DC output voltage and the DC gate bias for both rectifiers at 100kΩ load. The SBG stage achieves a higher voltage and has a higher DC bias by over 100mV which significantly helps in improving its performance

Fig. 7:

Performance of the proposed SBG design vs. a classical Dickson multiplier.

Fig. 8:

Trasient response of 1-stage SBG and Dickson at 900mV input swing with 100kΩ output load showing output voltage and average DC bias of SBG and Dickson stage.

B. High Output Voltage Realization

Apart from the gate biasing technique described above, the pumping transistors (M₁, M₂) are implemented using deep N-well devices to isolate the substrate and to connect it to the lowest potential in each stage as shown in Fig. 3. In this work, we target a neural implantation application where a higher output voltage is more desirable for stimulation. In a multi-stage design, the high output voltage is directly imposed on the gate of M₁, which could cause reliability issue if the substrate is not tied to the lowest potential of each stage. For example, from our measurement, the output voltage reaches 9.3 V without load at 0 dBm. Hence, V₄ (DC_OUT) of the last stage is 9.3 V, and the gate voltages of M₁, M₃, and M₄ are maintained at the same level. The bulks of these transistors are connected to DC_IN, which is ~8.4 V, thus a lower voltage difference between the gate and bulk guarantees the safe operation of the transistors. The local connection of the bulk helps V_GB and other terminal voltages of the device to remain low, ensuring high reliability. It also prevents the V_TH of M₁ and M₂ to increase due to the body effect. C_F1 and C_F2 are metal-insulator-metal (MIM) capacitors that can tolerate high voltages.

IV. Circuit Design Considerations

A. SBG Design and Stage Selection

The goal during implant design is to maximize the efficiency of the rectifier for a range of input power levels at higher output voltages. A relatively high output voltage is needed for neural stimulation with electrodes. Our analysis focused on two aspects of multi-stage SBG rectifier design, the transistor dimensions for one SBG stage and the number of SBG stages needed for a given input voltage level or power level. An SBG rectifier, like other rectifier topologies, also exhibits a maximum power-point voltage (V_max,n) for the maximum output power at a given input power. Consequently, one can increase the transistor dimensions to increase rectifier conductivity and obtain more power by increasing the output current. However, this will reduce the amplitude level (V_A) seen at the input of the rectifier. Therefore, for an n-stage rectifier, an optimal device size will exist for maximum output power. However, as we change the number of stages, both the output power and optimum device dimensions will also change. This requires a nested sweeping of transistor size and number stages to obtain the maximum power for a given input. Fig. 9 shows how the efficiency changes with device size and number of stages, where we swept the device width from 1μm to 22μm (with a fixed width of one finger being 1μm) within the n-stage rectifier. As the number of stages increases, the peak efficiency decreases due to increased losses. Considering the passive gain of the matching network, we designed with 900mV voltage swing at the input of the rectifier to optimize its design. A 100KΩ resistor was used as load to represent the microelectrode. Due to the required high voltage gain for neural stimulation, a 10-stages is desirable for the application, shown in Fig. 9(b). We selected 8μm width for SBG stage based on the simulation results (Fig. 9) showing highest efficiency. Fig. 11 shows the simulation results of the design after the optimization process mentioned above. An ideal matching network was used here to show the efficiency of proposed SBG structure with respect to the incident power.

Fig. 9:

Simulation results used to obtain maximum rectifier efficiency by sweeping the device size (width) and number of stages for the proposed SBG design with a 900mV input voltage. The width of a single finger is 1μm.

Fig. 11:

Performance of the proposed 10-stage SBG design with an ideal matching network.

B. On-Chip Matching Network (MN) Design

Prior works, such as in [27], [28] reported on the iterative design flow to find the design parameters such as the transistor dimensions, number of stages and matching network (MN) design for optimal power conversion efficiency (PCE). In our platform, we utilized the setup from [29] for assessments for the RF neural stimulation system with neural electrodes. The analysis included path loss during the transmission as well as estimation of the received power. The final received power is between −1.1 to 1 dBm due to the upper limit of the transmitting coil. We designed the energy harvester to have maximum efficiency at 0 dBm with design optimized for frequency close to 1GHz transmit coil [30].

Fig. 10 displays the complete diagram with the proposed rectifier stages, matching network and the extracted parasitics model. The major parasitics come from input/output (IO) pads on the chip and bonding wires for the direct attachment of the die to the PCB. The extracted pad model for simulation is shown in the figure. The bonding wire inductance was estimated based on 1 nH per millimeter length of the wire, and the resistance was estimated according to: R = ρl/A, where ρ is the resistivity of the conductor (e.g., ρ = 2.24 × 10 ⁻⁸Ω·m for gold wires), l is the length and A is cross-sectional area. The output parasitics are not shown in the figure for simplicity. This model was utilized during the design of the matching network, which is described next.

Fig. 10:

Diagram of 10-stage SBG rectifier, on-chip matching network, electrode load model and paracitics model.

The MN in Fig. 10 is needed to transfer the maximum amount of power from the antenna to the rectifier. High integration with small form factor is the priority of our IMD design for neural stimulation applications. This requires the MN to be on-chip despite the relatively poor quality factors (Q) of on-chip inductors. The value of these passive components have to be chosen carefully to avoid the use of excessive silicon area. Fig. 12 presents the contour plots of the input power with different matching network combinations of capactors and inductors, where the right y-axis shows the silicon area that would be consumed by the inductors. The area that the matching capacitor takes is significantly less than the inductor, which is why it is not included in this plot. We note that as the inductance increases, the more input power drawn from the RF source is approaching the maximum power, i.e., 1mW in this simulation scenario, but the area that the large inductor would require for this maximum power is beyond our constraint of < 0.1 mm₂ design. The red box in the figure identifies the inductor and capacitor combination that we adopted for this design. It implies 2× less area compared to using a 9nH inductor at the cost of only 10% input power drop. Fig. 14 displays the die photo with the proposed design, where L₁ and L₂ are the two identical standard spiral-type inductors. Standard inductors with foundry-supplied device models from the process design kit were utilized. Under the area constraint, they have a combined inductance of 4.8 nH (2.4 nH and Q = 8.03 provided by the design kit for each inductor). Constructed with a MIM capacitor (C₁), an L-matching network is used in this design to optimize the power transfer. The overall Q of the MN is 4.49 from post-layout simulation, and it goes up to 7.25 while considering the bond-wire parasitics. Fig. 13a shows the quality factor and inductance with frequency from post-layout simulation and Fig. 13b demonstrates the EM field strength with the help of ADS EM simulation. Fig. 15 shows the power breakdown of the complete system (illustrated in Fig. 10) based on post-layout simulation with estimated parasitics. The simulated PHE is 31% at 0 dBm incident power and 3% reflection loss, i.e., −15dB S₁₁ at 1GHz input frequency, which match the measurement results shown in Fig. 17. Hence, 27.8% of the incident power dissipates in the on-chip matching network, but allowing to realize a smaller design (< 0.1mm₂) that meets the application-specific needs.

Fig. 12:

Contour plot of the input power with MN design by varying inductor, capacitor, and the area of the inductor.

Fig. 14:

Photo of the die for neural implants, including the SBG rectifier with on-chip matching inductors and bond-pads.

Fig. 13:

(a) Quality factor and inductance vs. frequency of the selected on-chip inductors. (b) EM field strength (A/m) of the selected on-chip inductors at 1GHz. The peak strength is 3kA/m

Fig. 15:

Power breakdown at 0 dBm incident power with 100lΩ load from post-layout simulation with estimated parasitics.

Fig. 17:

Measured S₁₁ and PHE from a frequency sweep at 0-dBm of incident power.

V. Measurement Results

The energy harvester (EH) was designed and fabricated in 65 nm CMOS technology, and its die photo is shown in. Fig. 14. The two inductors consume a total area of 280 × 140μm₂ and the SBG rectifier has an area of 400 × 85μm₂. Four 80μm × 80μm bond-pads were included to create a direct integration point for neural implants. The total area of the die is 600 × 230μm₂, which includes the bond pads.

A. Rectifier Characterizing Measurement

Fig. 16 displays the measurement test-bench, where the chip is wirebonded onto a small printed circuit board (PCB). The equivalent electrode model is built on a breadboard and the output voltage is read from oscilloscope by sweeping the input power of a single-tone continuous RF signal. The S₁₁ measurement has been carried out using vector network analyzer (VNA), Keysight E5080B.

Fig. 16:

Measurement setup using Keysight N5183B RF and MSOX6004A oscilloscope.

We conducted several measurements to characterize the EH circuits, and also employed it in an animal test. The detailed specifications of the proposed circuits are included in the performance comparison in Table II. Apart from standard and well-defined metrics such as S₁₁, sensitivity, one of the most important performance aspects of a a rectifier is its efficiency. Researchers commonly use power conversion efficiency (PCE) to evaluate the performance of an EH [13], and they define it as the output power of the rectifier (P_OUT) over the input power of the rectifier (P_in,rect): PCE = P_OUT/P_in,rect. A common design practice is to analyze the efficiency of the rectifier in isolation for an optimized rectifier design. However, that does not consider the real-life application scenario where the receiving antenna and MN are indispensable to the complete system. A lossy MN and a poor S₁₁ will waste power even though a higher PCE for the rectifier can be achieved. Considering the fact that the power consumption of a MN cannot be easily measured, sometimes the loss in the MN network is evaluated for the PCE calculation and the effect of MN is excluded. Our design for neural implants is focused on the total power conversion efficiency, which includes losses in the MN. To evaluate our design, we measure power harvesting efficiency (PHE) [9], [33], also known as end-to-end efficiency, defined by P_OUT over the received power of the antenna (P_incident), which includes the reflection loss and MN loss.

TABLE II:

Performance comparison of the SBG-based RF energy harvester with other works.

	On-chip Matching Network				Off-chip Matching Network
	This work	JSSC’17 [10]	JSSC’11 [14]	TMTT’18 [31]	TCASI’19 [11]	TCASI’21 [32]	JSSC’19 [12]	JSSC’21 [33]	TCASI’22 [34]
Tech. Node (nm)	65	180	90	180	130	130	180	65	130
Silicon Area (mm2)	0.0732	1.08	1.35	0.707	0.053	0.127	0.4	125μm2⊕	0.029
Number of stages	10	1, 2, 4, 8	17	2	4	1	2, 3, 4, 6, 12	1	10
Comp. Method	SBG	None	VTH Comp.	None	VTH Comp.	VTH Comp.	None	None	VTH Comp.
Frequency	1.07GHz	915MHz	915MHz	980MHz	896MHz	915MHz	915 MHz	2.45GHz	915MHz
Match. Inductor (Q)	4.49/7.25*	≈ 8	N/A	11	> 100	50	N/A	30	3.5
Sensitivity w/1MΩ @ 1V	−13 dBm	−14.8 dBm	−22.4 dBm	−7.5dBm @ 400 μA	−20.5dBm	−10dBm	−17.1dBm @1V	−26.7 dBm @ 400mV	−25.5 dBm @(5MΩ)
Max VOUT w/ 1MΩ load	9.3 V @ 0 dBm	≈ 1.7V @ −1.7dBm	2.1V @ −5dBm	1.6 V @ 400μA	6.3V @ −7dBm	1.5 V (battery)	2.2 V @ −12 dBm	N/A	3V @ −15 dBm
Peak PHE	30% @ 0 dBm	25% @ 0 dBm(1-stage)	11% @ −18.3dBm	32%# @ 2dBm	43% @ −11dBm	63.4% @ 2.12 dBm	34.4% @ 1.3 dBm	32.3% @ −14.1 dBm	42.4% @ −16 dBm
PHE Range (> 20%)	12-dB	10-dB	N/A	N/A	N/A	8.5-dB	13-dB	12-dB	N/A
Output Load @ Peak PHE	Micro-Electrode	PMU	Resistor	400 μA	1MΩ	1.2V, 1.5V battery	PMU	N/A	Resistor (450kΩ)

^⊕Rectifier area only

^#Rectifier efficiency only

^*Including bond-wire parasitics

Fig. 17 shows the measured PHE and S₁₁ versus frequency. We can achieve a peak efficiency of 30 % at 1.07 GHz and 0 dBm incident power with 100 kΩ load resistor. This number stands out among other state-of-the-art EH designs with on-chip matching networks. The measured S₁₁ is −15.4 dB at 1.07 GHz, which is considered a good match since only 2.8% of the input power is reflected. The goal of our design was to achieve a 1.2GHz matching network for RF energy harvesting in neural implant applications. Inaccuracies in the device model and parasitic estimation resulted in realizing matching at 1.07GHz. However, this does not limit the application of the SBG rectifier for the implant application, which is primarily a near-field application where a coil is used to transmit energy. The design of the coil transmitter can be adjusted to center the transmit frequency appropriately. Also, on-chip tuning technique [10], [35] can be used to adjust the input impedance to meet the center frequnecy. Fig.18 presents the optimal PHE of 3 chips obtained by sweeping load the resistance at different incident power level. The variation in peak efficiency among three different chips is ≈3%. Fig. 19 and 20 show the measured PHE and output voltage with sweeps of the incident power and load conditions. We observe that there is an optimal incident power and load condition, and that this EH performs best at the required neural-implant load condition (0 dBm). The results also demonstrate that the rectifier can provide high output voltage. Additionally, to test the reliability of the design, we operated the energy harvester at 1 MΩ load with 0 dBm input power for 20 days. The output voltage of the rectifier remained at 9.3V for the entire time (Fig. 21) and the chip showed no noticeable degradation/changes in its output characteristics. The isolation using deep-Nwell design and biasing from the rectifier topology ensures < 1V bias across each stage of the rectifier.

Fig. 18:

Measured optimal PHE with a sweep of the incident power from three different chips.

Fig. 19:

Measured PHE and output voltage with incident power at 1.07GHz at 100kΩ output load.

Fig. 20:

Measured PHE and output voltage with output load resistance at 0dBm incident power (1.07GHz).

Fig. 21:

Measured output voltage with 1MΩ load.

Table II compares this SBG rectifier design with other reported rectifier circuits. There are two broader sets of comparisons that we use here. First, we compare our rectifier circuit with other rectifier that use on-chip implementation of MN as losses associated with MN in an on-chip network will be significantly higher than the designs that are implemented using off-chip matching network. This is due to the resistive loss in the parasitic resistance of the on-chip inductor for impedance matching. Our design uses a 10-stage implementation of the rectifier and achieves a maximum efficiency of 30%. The peak efficiency for the rectifier implemented with on-chip MN in [10] is 25%. However, this peak is achieved for a single stage rectifier at a lower output voltage. Since, our neural implantable design requires a higher output voltage, we use 10-stage design. Generally, our peak efficiency is higher than that of previous designs with an on-chip matching network. At the same time, our peak efficiency is comparable to some of the other works with off-chip MN in Table II. Specifically, our design caters to a high output voltage, multi-stage design scenario, while other high-efficiency designs involve 1-4 stages [9], [11].

High PHE-range [11], [12], which is defined as the input power range for which the efficiency remains higher than 20%, is shown in Fig. 18. We achieve a High-PHE range of 12-dB from −5dBm to 7dBm even when our peak efficiency is 30%, which compares well with other works in Table II, especially compared to works with on-chip matching networks. The work in [32] reports high efficiency of over 60%, but uses three off-chip high-Q inductors for the matching network and biasing, which would incur large area overhead for implantable applications. Furthermore, differential rectifier topologies can also achieve higher peak efficiencies [36], but suffer from a V_TH dead zone issue and balun is often needed but cannot be implemented on the silicon. Another differential topology [31] uses on-chip matching network but it requires off-chip balun and reports only rectifier’s efficiency of 32%. To keep the area lower for the implant, we use relatively small matching inductors, which causes an additional estimated efficiency degradation. However, keeping the inductor size smaller has helped in realizing the 0.138-mm₂ die area and the harvesting circuit area of 0.0732-mm₂ (excluding bond-pads and unused area), which is more than 14× less area compared to other energy harvesters with on-chip MN.

B. Animal Test Setup

An acute hippocampal slice is an excellent model system for the proof-of-concept of the proposed system. To demonstrate that this system can activate neurons, we used the device to provide stimulus to Schaffer collaterals of rat hippocampal slices while recording from CA1 fields.

All research protocols were approved and monitored by the Massachusetts General Hospital (MGH) Institutional Animal Care and Use Committee (IACUC). The ex-vivo experiments were conducted using brain slices extracted from 2-4 weeks old Sprague Dawley rats (Charles River Labs, MA, USA). The rats were deeply anesthetized with isoflurane and decapitated. After extracting the brain, 300 μm thick slices were prepared in Ca²⁺ free artificial cerebrospinal fluid (aCSF) using a vibratome. The slices were then incubated in aCSF solution at 34 °C. After a one-hour recovery period, the slices were transferred to the recording chamber that was continuously perfused with oxygenated aCSF solution. The PI20030.01A3 Pt/Ir stimulating stereotrode (100 kΩ, Pt/Ir, 225 μm pitch) was connected to the rectifier output while a recording glass micropipette was connected to a headstage (model 1800, A-M Systems) that was connected to a differential amplifier (model 3000, A-M Systems). Finally, the amplified (100 k) and filtered (3 Hz – 300 Hz) signal entered the data acquisition system (DAQ) to display the evoked field excitatory postsynaptic potential (fEPSP) measurements.

To demonstrate that the system can activate neurons, we used it with the SBG rectifier to provide stimulus to Schaffer collaterals of rat hippocampal slices while recording from CA1 fields. Fig. 22 shows the recorded field potentials while a stimulating stereotrode was connected to the rectifier output and a recording glass micropipette was connected to an external data acquisition system (DAQ) to display the field response. The voltage across the stimulating electrode reaches 1.36 V within 200 μs at 2 dBm of input power. While we can achieve stimulation at lower voltage, nonetheless, often much higher voltage is needed [37]-[39]. In addition, high voltage compliance becomes more important for overcoming the effect of tissue encapsulation around the electrode which inevitably occurs in chronic applications.

Fig. 22:

Animal stimulation test. (a) a micrograph of the hippocampus slice with the recording and stimulating electrodes, (c) recorded field response in an ex-vivo brain slice while using the wirelessly powered energy harvesting circuit for neuromodulation, (b) voltage across the stimulating electrode.

VI. CONCLUSIONS

This work described a new SBG rectifier for implantable medical devices (IMDs). The fully integrated, area-efficient SBG rectifier is capable of maintaining high PHE and high output voltage with a specific electrode model for application in neural stimulation. The principle of operation was explained together with key design considerations such as matching network design and IMD-oriented constraints. A new self-biased gate (SBG) design technique was introduced, which achieves high efficiency over a wide power range. Measurement results demonstrated that this energy harvester is on par with other state-of-the-art designs, despite of its on-chip matching network with inductors having relatively low quality factors. The proposed rectifier achieves a maximum PHE of 30% while operating with a 10-stage configuration. The area-efficient on-chip matching network enables over 14× lower total area compared to other on-chip designs, while the energy harvester also realizes a high voltage and efficient RF energy transfer. The design was experimentally tested through animal tissue stimulation.

TABLE I:

Device implementation for SBG stage

Device	Type	Property
M1,M2	LVT_DNW	W/L=8μ/60n
M3,M4	LVT_DNW	W/L=200n/100n
CF1,CF2	MIM	208.6 fF
CD	MIM	1 pF

Biographies

Ziyue Xu received the B.S degrees in electrical and engineering department from Anhui University, Hefei, China in 2016. He is currently a Ph.D. candidate and the member of energy circuits and system group of electrical engineering in Northeaster University, Boston, MA, US. His research interests include power management integrated circuits design, RF design and energy harvester design.

Adam Khalifa received the B.S and MPhil degrees in electronic and computer engineering from Hong Kong University of Science and Technology, Hong Kong, China, in 2011 and 2013, respectively. He received the Ph.D. degrees in electrical and computer Engineering from Johns Hopkins University, Baltimore, MD, in 2019. He currently works at Massachusetts General Hospital and Harvard Medical School on novel neural interface technologies. His research interests include low-power Analog/RF/Mixed-mode ASIC design, neural stimulation and recording, wireless powering, miniaturization, electrode design/microfabrication and implant packaging.

Ankit Mittal received his B.Tech. degree in Electronics and Communication engineering from Day-albagh Educational Institute, India in 2014 where he was also the recipient of Director’s medal. Currently he is a Ph.D. candidate in the Energy Circuits and Systems Group , Electrical Engineering at Northeastern University, USA. Prior to joining Ph.D. program , he was a senior design engineer in NXP Semiconductors, India with a rich experience in SoC design and 5 memory testchip tapeout to his credit. His research interests include power management integrated circuit design, ultra-low power biomedical circuits, ultra-low power RF radio design.

Mehdi Nasrollahpour received the B.S. degree from Shahid Rajaee Teacher Training University, Tehran, Iran, in 2015 and the Master’s degree from San Jose State University, San Jose, CA, USA, in 2017. From 2014 to 2015, he was a Research Assistant with the Microelectronic Circuits Laboratory (MECL) and joined the Radio Frequency Integrated Circuits Laboratory (RFIC) in 2015. His research interests include Analog/Mixed-signal and RF integrated circuits. He got his PhD with the Advanced Materials and Microsystems Laboratory (AMML) Lab, Northeastern University, Boston, MA, USA, focused on Brain Implants for biomedical applications and MEMS based radio frequency integrated circuits. He received the 2017 Donald Beall–Rockwell Award for Engineering Accomplishment, the IEEE 2017 NGCAS Young Professional Award and 2018 Northeastern University College of Engineering Dean’s Fellowship. He is currently with MediaTek as Staff Mixed-signal IC Design Engineer in Woburn, MA

Diptashree Das is currently pursuing the Ph.D. degree at Northeastern University, Boston, MA, USA. Her research interests include analog and mixed-signal integrated circuit (IC) design, RF IC design, IC design for wireless communication and medical applications.

Marvin Onabajo (S’01–M’10–SM’14) is an Associate Professor in the Electrical and Computer Engineering Department at Northeastern University. He received a B.S. degree (summa cum laude) in Electrical Engineering from The University of Texas at Arlington in 2003 as well as the M.S. and Ph.D. degrees in Electrical Engineering from Texas A&M University in 2007 and 2011, respectively.

From 2004 to 2005, he was Electrical Test/Product Engineer at Intel Corp. in Hillsboro, Oregon. He joined the Analog and Mixed-Signal Center at Texas A&M University in 2005, where he was engaged in research projects involving analog built-in testing, data converters, and on-chip temperature sensors for thermal monitoring. In the spring 2011 semester, he worked as a Design Engineering Intern in the Broadband RF/Tuner Development group at Broadcom Corp. in Irvine, California. Marvin Onabajo has been at Northeastern University since the Fall 2011 semester. His research areas are analog/RF integrated circuit design, on-chip built-in testing and calibration, mixed-signal integrated circuits for medical applications, data converters, and on-chip sensors for thermal monitoring. He currently serves as Associate Editor on the editorial boards of the IEEE Transactions on Circuits and Systems I (TCAS-I, 2016-2017, 2018-2019, 2020-2021 and 2022-2023 terms) and of the IEEE Circuits and Systems Magazine (2016-2017, 2018-2019, 2020-2021 and 2022-2023 terms). During the 2014-2015 term, he was on the editorial board of the IEEE Transactions on Circuits and Systems II (TCAS-II). He received a CAREER Award from the National Science Foundation, a Young Investigator Program Award from the Army Research Office (ARO), and the Martin Essigman Outstanding Teaching Award from the College of Engineering at Northeastern University.

Nian Sun is a professor of Electrical and Computer Engineering, and of Bioengineering, Director of the W.M. Keck Laboratory for Integrated Ferroics, Northeastern University, and founder and Chief Technology Advisor of Winchester Technologies, LLC. He received his Ph.D. degree from Stanford University. Prior to joining Northeastern University, he was a Scientist at IBM and Hitachi Global Storage Technologies. Dr. Sun was the recipient of the Humboldt Research Award, NSF CAREER Award, ONR Young Investigator Award, the Sren Buus Outstanding Research Award, Outstanding Translational Research Award, etc. His research interests include novel magnetic, ferroelectric and multiferroic materials, devices and microsystems, novel gas sensors and systems, etc. He has over 300 publications and over 30 patents and patent applications. One of his papers was selected as the “ten most outstanding full papers in the past decade (2001 2010) in Advanced Functional Materials”. Dr. Sun has given over 180 plenary/keynote/invited presentations and seminars. He is an editor of Sensors, and IEEE Transactions on Magnetics, and an elected fellow of the IEEE, Institute of Physics, and of the Institution of Engineering and Technology.

Sydney Cash received the M.D. and Ph.D. degrees from Columbia University, New York, NY, USA. He gained further clinical training at Massachusetts General Hospital, Boston, MA, USA. Currently, he is an Associate Professor in the Epilepsy Division of the Neurology Department at Massachusetts General Hospital and Harvard University, Cambridge, MA, USA. He is a member of the BrainGate clinical trial team, and codirector of the Department of Neurology NeuroTechnology Trials Unit. The research in his lab is, broadly speaking, dedicated to trying to understand normal and abnormal brain activity, particularly oscillations, using multi-modal and multi-scalar approaches particular those which allow for recordings to be made at the microscale (e.g., single unit recordings) as well as at the more macro scale. His work includes a focus on the development of novel neurotechnological approaches to help diagnose and treat common and devastating neurological diseases including epilepsy.

Aatmesh Shrivastava (S’12–M’15–SM’19) received his Ph.D. degree from University of Virginia in 2014. Prior to his Ph.D. studies, he worked as a senior design engineer at Texas Instruments, Bangalore from 2006 to 2010. From 2014 to 2016, he worked at the IoT start-up Everactive as senior design director, where he headed the research and development of the energy harvesting and power management solutions. In August 2016, he joined Northeastern University, where he is now working as an Assistant Professor in the Electrical Engineering Department. His research interests include self-powered and ultra-low power circuits and systems, energy-harvesting and analog computing, hardware for AI, internet-of-things, and ultra-low power bio-medical and neural circuits. Dr. Shrivastava is a recipient of 2022 CAREER Award from National Science Foundation (NSF). He currently serves as an Associate Editor for IEEE Open Journal on Circuits and System (OJCAS).