High-performance and low-power source-gated transistors enabled by a solution-processed metal oxide homojunction

Significance

Source-gated transistors (SGTs) exhibit high intrinsic gain, immunity to bias instability, low-power consumption, and tolerance to short-channel effects, and thus are attractive candidates for wearable devices. However, few studies have addressed the potential of metal oxide semiconductor (MO)-based SGTs. Here we demonstrate solution-processed MO SGTs based on a semiconductor homojunction, comprised of solution-processed In₂O₃ and In₂O₃:PEI polymer blend layers of controlled doping, exhibiting low saturation voltage, low-power consumption, and high intrinsic gain. Furthermore, electrooculographic signal monitoring is demonstrated using an SGT inverter, which provides a voltage gain of over 300 and is readily suitable for applications in wearable medical sensing.

Abstract

Cost-effective fabrication of mechanically flexible low-power electronics is important for emerging applications including wearable electronics, artificial intelligence, and the Internet of Things. Here, solution-processed source-gated transistors (SGTs) with an unprecedented intrinsic gain of ~2,000, low saturation voltage of +0.8 ± 0.1 V, and a ~25.6 μW power consumption are realized using an indium oxide In₂O₃/In₂O₃:polyethylenimine (PEI) blend homojunction with Au contacts on Si/SiO₂. Kelvin probe force microscopy confirms source-controlled operation of the SGT and reveals that PEI doping leads to more effective depletion of the reverse-biased Schottky contact source region. Furthermore, using a fluoride-doped AlO_x gate dielectric, rigid (on a Si substrate) and flexible (on a polyimide substrate) SGTs were fabricated. These devices exhibit a low driving voltage of +2 V and power consumption of ~11.5 μW, yielding inverters with an outstanding voltage gain of >5,000. Furthermore, electrooculographic (EOG) signal monitoring can now be demonstrated using an SGT inverter, where a ~1.0 mV EOG signal is amplified to over 300 mV, indicating significant potential for applications in wearable medical sensing and human–computer interfacing.

Low-power consumption and mechanical flexibility are indispensable requirements for emerging transistor-based wearable/portable electronics technologies (1–6). A common approach to minimize power consumption of transistors having differing architectures and functions is to employ dielectrics with high gate capacitance, such as electrolytes or high-k dielectrics, which effectively lower the driving voltage of these devices (7–12). Recently, organic and metal oxide-based source-gated transistors (SGTs; Fig. 1) with Schottky contacts at the source of a thin-film transistor (TFT) geometry have delivered significantly lower drain current (I_D) and saturation voltage (V_{D_SAT}), thereby reducing power consumption to orders of magnitude lower than that of conventional (Ohmic contact) TFTs (cTFTs; Fig. 1A) (13, 14). Since the I_D is mainly governed by the source contact, SGTs do not require extreme scaling of the channel dimensions. Furthermore, SGTs have high intrinsic gain, large output resistance, immunity to bias instability, and tolerance to short-channel effects (15, 16). Studies have demonstrated excellent SGT performance from devices using a variety of semiconducting materials, including amorphous/poly silicon, nanowires, organic semiconductors, and metal oxides (MOs) (14, 17–20).

Fig. 1.

Structures and response characteristics of the indicated conventional TFT (cTFT) and source-gated TFT (SGT) devices. Schematic representations of (A) cTFT, (B) SGT-1, (C) SGT-2, and (D) SGT-3 used in this study, and the corresponding representative (E) output and (F) transfer characteristics. (G) I_{D_SAT,}V_{D_SAT} and P_SAT at V_GS = 30 V in the indicated cTFT and SGTs. Channel lengths are 5 µm for all devices.

Although current generation oxide semiconductor transistors are less mature than silicon TFTs, they show great promise for large-area electronics due to their high electron mobility (>10 cm²/Vs), superior optical transparency, low trap density, and large area uniformity (21–28). Several studies have reported MO-based SGTs with low V_{D_SAT}s and high gains (29, 30). For example, by carefully adjusting the O₂ partial pressure during IGZO (indium-gallium-zinc oxide) film sputtering, an optimal Schottky barrier between the source electrode and IGZO is formed, yielding SGTs with an ultra-high intrinsic gain (15, 19; Fig. 1B). Introducing a tunneling layer between the source contact and the oxide semiconductor can also modulate the Schottky barrier (31). Thus by using a 3-nm Al₂O₃ layer between IGZO and Ni source/drain contacts, Silva et al. demonstrated SGTs with a low V_{D_SAT} of ~+3 V, and low gate voltage (V_GS) dependence of V_{D_SAT} (ΔV_{D_SAT}/ΔV_GS ~ 0.12 V/V) (32). However, these pioneering approaches require accurate control of the O₂ partial pressure during MO sputtering or the tunneling layer thickness. Moreover, most current MO-based SGTs have only been fabricated by vapor-phase growth techniques, such as atomic layer deposition, chemical vapor deposition, or sputtering deposition, which limits broad applicability and requires considerable capital investment (33). In contrast, solution processing of MOs is an alternative approach for producing large-area and high-performance electronics owing to its simplicity, scalability, and minimal capital investment (34–38). Recently, solution-processed indium oxide (In₂O₃) SGTs were reported by Li et al., exhibiting a respectable V_{D_SAT} of 12 V at a V_GS of 20 V less than that in the corresponding ohmic TFT (28 V at V_GS = 20 V) (39).

In recent studies, we developed a procedure for doping MOs with organic polymers which can effectively modulate the work function of the corresponding doped MO films by up to 1 eV, which could prove useful in tuning the metal contact/semiconductor injection properties of MO TFTs (40, 41). Specifically, using amino-containing polymers such as polyethyleneimine (PEI), we demonstrated In₂O₃ TFTs with electron mobilities ~8 cm²/V s and I_on/I_off > 10⁷ versus <4 cm²/V s and <10⁴, respectively, for pristine In₂O₃ cTFTs, reflecting the capacity of electron-rich PEI to donate electrons and neutralize defects (42). Furthermore, devices comprising a homojunction of In₂O₃ (work function = 4.00 eV) and a :PEI blend (work function = 3.89 eV for 0.5 wt.% PEI) afforded a two-dimensional electron gas with enhanced electron mobility as well as promising temperature and bias stress stability (43).

In this contribution, we now demonstrate MO SGTs using a semiconductor homojunction and Au contacts (Fig. 1D). These devices, comprising solution-processed In₂O₃ and In₂O₃:PEI blend layers as the homojunction, exhibit a V_{D_SAT} as low as +0.8 ± 0.1 V and an intrinsic gain (A_v) of ~2,000. Moreover, these SGTs have a power consumption (V_{D_SAT} × I_{D_SAT}) of only ~25.6 μW, obtained at V_GS = +30 V, which is about 500× lower than that of the corresponding cTFTs. It will be seen that surface potential measurements by Kelvin probe force microscopy (KPFM) under different biases reveal that placing the In₂O₃:PEI blend layer under the Au source contact improves gate control over the effective source resistance. Furthermore, lower driving voltages (<+2 V) and flexible variants of these SGTs are achieved using a high-capacitance fluoride-doped AlO_x (F:AlO_x) dielectric material, which affords low-power consumption (~11.5 μW) and an inverter with an outstanding voltage gain of over 5,000. Most importantly, real-time monitoring of human electrooculogram (EOG) signals is demonstrated with this SGT in an inverter, exhibiting a voltage gain of over 300 and ~250 for vertical and horizontal eye movement, respectively. This work demonstrates a conceptually simple and efficient route for realizing low-power solution-processed MO SGTs.

Results and Discussion

TFT and SGT Fabrication and Performance Characteristics.

Unlike cTFTs, the source contact in SGTs is a reverse-biased Schottky diode. At relatively low V_GS and V_DS, the channel under the source contact is depleted, pinching off the semiconductor and producing large current saturation (SI Appendix, Fig. S1). A typical strategy to realize a SGT is to use a source metal contact with a large difference in work function from the semiconductor channel, e.g., a high work function metal for an n-type semiconductor. The resulting Schottky barrier enhances the electric field under the source and thereby reduces V_{D_SAT} (14). Here, to demonstrate SGT operation, cTFTs based on a bilayer of ~8-nm-thick undoped In₂O₃, fabricated by 2× (spin-coating + thermal annealing) steps, were fabricated with evaporated Al (ohmic contact) or Au (Schottky contact) as source/drain electrodes, indicated as SGT-1 device in Fig. 1B. Here, Si/SiO₂ (100 nm) wafers are used as the gate electrode/gate dielectric. The thermally evaporated Al or Au contacts (40 nm) were patterned as the source/drain electrodes (channel width = 150 µm, channel length = 5 ~ 20 µm; see Experimental Section and SI Appendix, Fig. S2 for details). Output characteristics (Fig. 1E) of the 5-μm-long cTFTs indicate a high saturation voltage (V_{D_SAT} ~ +30 V) while much lower V_{D_SAT}s (+3.8 ± 0.3 V) are obtained for SGT-1 at all gate voltages (V_GS, from 0 V to +30 V). Note that cTFTs with a 5 μm channel length exhibit poor switching properties, including hump-like features in the transfer characteristics (SI Appendix, Fig. S3). The observed hump-shaped artifact of the short-channel TFTs originates from geometrical channel length inhomogeneity associated with the fabrication process and can be explained as two channels of different lengths operating in parallel (44, 45). Considering that the SGTs are fabricated using the same procedures as the cTFTs, the hump behavior in the cTFTs and lack thereof in the SGTs (SI Appendix, Fig. S4) suggest that the current control in SGTs is more resistant to channel length inhomogeneities, relaxing the need for strict current control. Interestingly, as shown in SI Appendix, Fig. S4, SGT-1 devices with different channel lengths (5, 10, and 20 µm) exhibit similar drain currents (I_Ds) (~200 μA at V_GS = +30 V) whereas those of cTFTs at the same V_GS vary widely by ~3× (SI Appendix, Fig. S3). The strong I_D saturation in SGT-1 can be also seen from the transfer characteristics at different V_DS (Fig. 1F). Upon increasing the V_DS from 1 V to 10 V, the I_on of SGT-1 exhibits a 154% increase, which is ~13× less than that in the cTFTs (1981%) (SI Appendix, Fig. S5). The channel length-independence and strong saturation of I_D suggest that the current in SGT-1 is controlled primarily by the source depletion region, which is consistent with SGT behavior (46, 47). However, the relatively large V_{D_SAT} (~+4 V) in SGT-1 indicates that the source-gating effect is not ideal.

To achieve better saturation characteristics at a lower V_{D_SAT}, SGTs based on In₂O₃:1% PEI blend bilayers and Au source/drain electrodes (structure SGT-2, Fig. 1C) were next fabricated and characterized. Note, SGT-2 exhibits V_{D_SAT} of +1.8 ± 0.2 V at a V_GS = +30 V, which is ~2× lower than that of SGT-1 (Fig. 1E). Interestingly, note that I_on in SGT-2 exhibits minor variations (~63%) when V_DS varies from +1 to +10 V (Fig. 1F and SI Appendix, Figs. S6 and S7). Next, another type of SGT (SGT-3, Fig. 1D) was fabricated with the channel composed of an In₂O₃:1% PEI top layer and a neat In₂O₃ bottom layer, thus forming a homojunction architecture. SGT-3 shows a significantly lower V_{D_SAT} of +0.8 ± 0.1 V, which is ~5× lower than that of SGT-1 (Fig. 1G and Table 1). Furthermore, I_on of SGT-3 remains 38.5 ± 2.7 μA (I_on variation ~ 20%) in the V_DS range of +1 ~ +10 V (SI Appendix, Fig. S7) and SGT-3 devices with longer channel lengths (10 and 20 μm) also exhibit similar saturation currents (30.8 ± 0.7 μA) and V_{D_SAT} (+1.0 ± 0.3 V) to those of the 5 μm channel SGT-3 (SI Appendix, Fig. S8). Although the large contact resistance in SGT-3 results in lower on-current, the on/off current ratio remains ~10⁶, which is comparable to that of the best sputtered IGZO SGTs (15, 48). Note, control device SGT-4 (SI Appendix, Fig. S9) with a reversed homojunction (i.e., an :1% PEI bottom layer and undoped In₂O₃ top layer) shows a V_{D_SAT} (+4.1 ± 0.2 V) similar to that of SGT-1 and a significant V_DS-dependence of I_on in saturation. From these results, it can be seen that PEI incorporation in the top In₂O₃ layer optimizes SGT response. Finally, we note that the I_D of SGT-1 and control SGT-4 at biases beyond that of saturation (>~+4 V) slightly decreases (negative differential resistance) likely due to charge trap creation in the top neat In₂O₃ layer under drain bias stress (49). These trap states likely originate from extensive oxygen vacancies present in neat In₂O₃ acting as electron trap sites (50), since I_Ds of both SGT-2 and SGT-3 are far more stable after saturation as the result of the dopant effectively pre-filling these trap states (42).

Table 1.

Performance metrics of the indicated cTFT and SGT devices

Device*	Semiconductor/Electrode	Ion/Ioff (105)	VT (V)	Von (V)	VD-SAT (V)	ID-SAT (μA)
cTFT	In2O3/In2O3/Al	94.5 ± 20.2	−2.6 ± 2.4	−7.5 ± 1.2	+30.5 ± 2.7	417.6 ± 43.2
SGT-1	In2O3/In2O3/Au	153.8 ± 18.0	+6.1 ± 2.1	−15.6 ± 2.1	+3.8 ± 0.3	199.5 ± 14.4
SGT-2	In2O3:1% PEI /In2O3:1% PEI/Au	8.1 ± 0.5	+12.4 ± 1.0	−14.6 ± 1.7	+1.8 ± 0.2	24.9 ± 2.5
SGT-3	In2O3/In2O3:1% PEI/Au	8.0 ± 0.6	+1.7 ± 1.4	−11.6 ± 1.1	+0.8 ± 0.1	31.8 ± 2.2

^*I_on/I_off,V_T,V_on were extracted from the transfer characteristic curve under V_DS = +10 V. V_D-SAT and I_D-SAT were extracted from the output characteristic curve under V_GS = +30 V. Each datum reported for an average of ≥10 devices.

Power consumption at V_{D_SAT} (P_SAT) in the present devices was estimated based on V_{D_SAT} and the corresponding I_DS (Fig. 1G) using P_SAT = I_{D_SAT} × V_{D_SAT} (14). P_SAT dramatically falls from ~12,750 μW for cTFT to ~760 μW for SGT-1 to ~45 μW for SGT-2, and to ~25.6 μW for SGT-3, which is comparable to state-of-the-art sputtered metal oxide (IGZO) SGTs (P_SAT ~ 10 μW) (15). Note that the change in V_{D_SAT} with V_GS of the cTFT (ΔV_{D_SAT}/ΔV_GS ~ 1) exhibits a typical TFT pinch-off dependence (V_{D_SAT} = V_GS − V_T). In contrast, V_{D_SAT} in the present SGTs exhibits an exceptionally low dependence on V_GS of only ~0.02 for the optimal device (SGT-3). Consequently, the voltage drops across the device when implemented in series for a circuit (ΔV_{D_SAT}) will not vary significantly on increasing I_{D_SAT} of the SGT, representing an important feature for energy-efficient analog circuits (14).

KPFM and Resistance Measurements.

Next, KPFM measurements were carried out to correlate enhancements in SGT performance characteristics with the effects of PEI doping on the electrostatic potential in the channel. In cTFTs, pinch-off occurs at the drain electrode (51), whereas in SGTs it occurs at the source electrode due to the large electric field and resulting depletion created by the Schottky barrier. Accordingly, KPFM measurements were employed to confirm that the source electrode limits the current in saturation and to determine whether the PEI doping in In₂O₃:PEI film enhances the potential drop at the source electrode. Surface potential profiles of SGTs were measured across the channel under V_DS = +1 V and V_GS = ±20 V biases and then subtracted from with those measured under V_DS = 0 V at each V_GS to extract potential drop data of SGT-1 and SGT-3 (blue and red curves in Fig. 2A, respectively). When the channel is depleted (V_GS = −20 V, open symbols), significant potential drops are measured at both source and drain contacts for both devices. In contrast, when the channel is gated into accumulation (V_GS = +20 V, solid symbols), the potential drops primarily at the source electrode, and the effect is more pronounced in the SGT-3 device. Note, these devices exhibit similar potential profiles at higher V_DS of +3 V, where the source is fully pinched-off (SI Appendix, Fig. S10). The KPFM analysis therefore confirms that the gate voltage is effectively modulating injection at the source contact and that saturation arises from pinch-off at the source as expected. Considering that the device structure is symmetric and that applying a negative V_DS induces a potential drop at the drain (Fig. 2 A, Inset), we conclude that the asymmetry arises from the Schottky nature of the metal–semiconductor contacts (52).

Fig. 2.

KPFM and resistance characteristics of the indicated SGT devices. (A) Surface potential profile of SGT-1 (blue) and SGT-3 (red) devices at V_DS = +1 V and V_GS = −20 V (open symbols) and +20 V (solid symbols). The surface potential drops at the drain-semiconductor or source–semiconductor interfaces are shown as ΔV_D and ΔV_S, respectively. Inset: surface potential profiles at V_DS = −1 V, V_GS = −20 V (open symbols) and +20 V (solid symbols). (B) Effective source and drain resistances of SGT-1 and SGT-3 calculated from the surface potential drop in (A) and output current. (C) Ratio of surface potential drop at source versus drain, extracted from (A). Increasing V_GS increases the fraction of the potential drop at the source electrode.

To correlate the observed source potential drop (Fig. 2A) with greater SGT performance (Fig. 1 E and G), the resistances of the source and drain regions were calculated from the potential drops at the contacts and output currents under different bias conditions (Fig. 2B). Note that the resistance plotted arises from both the Schottky barrier at the metal–semiconductor interface and the pinch-off region under and adjacent to the electrode. At V_GS = −20 V, the resistances of source (solid lines) and drain (dashed lines) regions are comparable in both devices, with those of SGT-3 being an order of magnitude higher. As the channel is biased further into accumulation by increasing V_GS, the drain resistance decreases more rapidly than the source resistance (Fig. 2C), shifting control of the current to the source electrode as expected for an SGT. Thus, PEI doping of the top semiconductor layer increases the fraction of the potential that drops at the source electrode for a given gate voltage and thereby lowers the V_{D_SAT}. These observations are consistent with the expectation that PEI doping increases the effective Schottky barrier of the source electrode, where “effective” refers to the barrier height that would be measured under the combined influence of thermionic emission, field emission, and image-force barrier height lowering (53). As a result, the effective gate bias at the source end of the channel will be reduced by the potential drop from the source electrode across the channel (i.e., $V_G-\mathrm{\Delta }{V}_S$), reducing the V_D required to pinch-off the channel (54).

Effect of PEI Content on SGT-3 Devices.

To further investigate the effects of how PEI doping affects SGT characteristics, additional devices were also fabricated based on the SGT-3 structure but with varying amounts (x% weight) of PEI in the In₂O₃:x% PEI layer (x = 0.5, 2, 3 and 5 %) (see details in SI Appendix, Table S1 and Figs. S11–S13). Thus, the 0.5% PEI-doped SGT-3 exhibits a V_{D_SAT} of 2.5 V, which is larger than that in the 1% PEI-doped SGT-3 (0.8 V), but lower than that in SGT-1 (3.8 V). This result further verifies that a higher PEI content increases the effective Schottky barrier under the source electrode and leads to pinch-off and saturation at lower drain voltages (SI Appendix, Fig. S11). In contrast, although lower V_{D_SAT}s (0.7, 0.5, and 0.3 V) with even higher PEI doping levels (2%, 3% and 5%, respectively) are achieved, enhanced negative resistance in the output curves is also observed, which is attributed to dynamic charge trapping effects since excessive PEI increases the trap density by greater carbon contamination and morphological irregularities (42). Since obvious negative resistance behaviors are visible in both SGT-1 and SGT-3 with >2% PEI doping levels, the hysteresis in SGT-1 and 3% PEI-doped SGT-3 was also investigated (SI Appendix, Fig. S14), revealing considerable hysteresis which increases with V_DS, showing that the higher bias amplifies charge trap effects. Therefore, the optimal PEI content in the context of this study (1 wt.%) exploits a delicate balance between the beneficial increase in electron doping adjacent to the contacts and the influence of increasing trap density in the doped region of the channel due to PEI doping and possible decomposition (55). As a consequence, SGT-3 (with a In₂O₃/In₂O₃:1% PEI blend homojunction) exhibits enhanced bias stress stability versus SGT-1 (with neat In₂O₃) under bias of V_GS = 30 V, with V_th shifts of 2 V and 10 V, respectively (SI Appendix, Fig. S15).

Since transistor performance is enhanced upon PEI doping of the top layer and the operating mechanism confirmed by KPFM, we further characterized the performance of the optimally doped SGT-3 devices in terms of key transistor figures of merit. Intrinsic gain (A_v = g × γ, where g is transconductance = ${\displaystyle \partial I_{\mathrm{DS}}/\partial V_{\mathrm{GS}}}$ and γ is output resistance = ${\displaystyle \partial V_{\mathrm{DS}}/\partial I_{\mathrm{GS}}}$) describes the maximum voltage gain of a transistor (15), which represents the transistor’s ability to amplify signals. A large A_v is desirable for applications requiring high output impedance and good current stability. The nearly constant output curve after V_DS of 3 V in SGT-3 with 1% PEI doping translates to an ultrahigh γ (~3.4 × 10⁹ Ω) under V_GS = +5 V, making this device optimal for logic applications. Consequently, an A_v of ~2,000 is obtained (SI Appendix, Fig. S16) which is much greater/comparable to those of IGZO cTFTs (40 ~ 120) and IGZO SGTs (400 ~ 10,000) (15, 19, 56, 57). Note that after the device reaches saturation, I_D increases slightly with increasing V_DS due to non-ideal Schottky contact which enhances the leakage current (15). In this case, the γ calculated based on I_D in the V_GS range of 0.8 ~ 3 V is underestimated (SI Appendix, Fig. S16C). Moreover, compared to SGT-1 and SGT-4, the output curves of SGT-3 under a low V_GS (0, 5, 10 V), which exhibit negligible negative differential resistance, are used to extract γ.

Low Driving Voltage and EOG Demonstration.

A low driving voltage is also a crucial requirement to achieve ultra-low-power electronics, along with low V_{D_SAT} and I_{D_SAT}. However, most previously reported metal oxide-based SGTs have primarily focused on achieving low V_{D_SAT} and have not investigated reduction of the driving voltage. Here, we employ a fluoride-doped (3.7 at.%) solution-processed AlO_x dielectric (F:AlO_x) to achieve a low-voltage SGT-3 (Fig. 3A) (58, 59). Note this F:AlO_x dielectric film has a thickness of ~ 20 nm and a specific capacitance of 166 nF/cm²—much higher than that of 100 nm SiO₂, 35.5 nF/cm², and exhibits ultra-stable capacitance-frequency behavior and bias stability due to reduced proton mobility upon fluoride doping (58). Thus, the F:AlO_x-based SGT-3 operates at a driving voltage as low as +2 V while retaining the superior transfer and output characteristics achieved previously with SiO₂ (SI Appendix, Fig. S17 A and B). Thus, V_{D_SAT} ~ +1.0 V and the saturation current behavior (~11 μA under V_GS = V_DS = 2 V, SI Appendix, Fig. S17) of the F:AlO_x device for 5 to 20 μm channel lengths is similar to that of SiO₂ devices. However, this device does not exhibit the typical s-shaped output characteristics of traditional In₂O₃/In₂O₃:PEI blend homojunction Schottky TFTs where the source and gate electrodes do not overlap (18, 19). Next, the low-voltage SGT-3 was used in an inverter configuration to exploit the extremely high gain. As shown in Fig. 3B, owing to the low saturation voltage and flat saturation characteristics, the SGT inverter exhibits typical reverse responses. The voltage gain (∂V_out/∂V_in) (Fig. 3C) increases from 631 to 5,082, as the drain compliance (V_D-C) steadily increases from +1.1 V to +1.5 V. Setting a different value of the current source does not obviously affect the gain of the inverter (SI Appendix, Fig. S18). These gains are ~10× higher than those obtained for silicon- and organic semiconductor-based SGTs, and are comparable to those of sputtered oxide-based SGTs (15, 17, 18).

Fig. 3.

Low driving voltage and EOG demonstration. (A) Structure of the low-voltage F:AlO_x SGT-3 device. (B) Voltage transfer characteristics and (C) voltage gain of the SGT inverter under different V_DS values. Inset: schematic of the inverter with a current source as a load. Circuit diagram of the SGT for EOG signal monitoring during (D) up-down and (E) left-right eye movements. EOG signals obtained from the control group and the after amplification during (D) up-down and (E) left-right eye movements.

The very high voltage gain of the present SGT-3-based inverter is attractive for signal amplification, by functioning as an inverting amplifier. Here we demonstrate the potential for measuring human electrophysiological signals by tracking an electrooculogram (EOG) signal, which is a small potential (V_EOG) between the cornea and retina originating from eye movement (18, 60). The amplified EOG signals have the potential to detect subtle eye movements for a better depiction of the virtual and augmented environment (61). For this, we used two 3M-2,238 electrodes attached over the eyebrow and below the lower eyelid for tracking up/down eye motion (Fig. 3D). Thus, without amplification, the V_EOG varies in the range from 0.5 to 1 mV (control signal), as reported in the literature (62). By connecting the lower eyelid electrode to V_in, along with proper adjustment of V_D-C and V_SS to ensure ∼0 V switching voltage, the amplified V_out exhibits voltage variations over 300 mV upon eye movement. Similar V_out amplification (~250 mV) is recorded by placing the two 3M-2,238 electrodes on the left and right sides of the eyes (Fig. 3E). Note, existing technologies for monitoring EOG signals usually require bulky and costly specialized instrumentation or complex circuitry (63, 64); however, the present SGT circuit can measure and amplify the EOG signals simultaneously, which is advantageous in terms of portability, directness of evaluation, fabrication simplicity, and low cost.

Flexible SGTs.

Finally, as proof of concept, mechanically flexible devices were demonstrated by fabricating F:AlO_x-based SGT-3 on flexible polyimide (PI) substrates (Fig. 4A). Note, in this SGT the Cr/Au (3 nm/20 nm) gate contact, patterned on the polyimide (PI) substrate using photolithography, only overlaps with the source and the semiconducting channel region (Fig. 4A). These flexible devices, are also semitransparent (Fig. 4 B, Inset), exhibit rapid saturation at a low V_{D_SAT} ~ +1 V (Fig. 4B) and similar saturated currents of ~57 μA for different channel lengths (5 to 20 μm, SI Appendix, Fig. S19). In addition, I_{D_SAT} in the transfer curves remains similar (87 ~ 99 μA) when V_DS is increased from +0.8 V to +1.2 V (Fig. 4C). Mechanical stress tests were carried out by bending the devices at a radius (r) of 7 mm (~0.4% strain) over multiple bending cycles (Fig. 4D and SI Appendix, Fig. S20). Thus, after bending for 10 times I_{D_SAT} and V_{D_SAT} retained 76.3% and 94.5% of their initial values, respectively. Degradation likely occurs at the source/drain contact and/or at the contact/oxide interface in these SGTs since the contact area is much larger than the channel area and experiences the greatest elongational strain as the uppermost layer of the stack (65, 66).

Fig. 4.

Mechanical properties of the present low-voltage SGT devices. (A) Flexible SGT-3 fabrication procedure. Representative output (B) and transfer (C) characteristics of flexible SGT-3. (D) Saturation current variations extracted from output curves of the flexible SGT-3 after the indicated bending cycles. Channel length = 5 μm.

Conclusions

Solution-processed metal oxide SGTs exhibiting a low-power consumption of ~25.6 μW and an intrinsic gain ~2,000 were realized with a homojunction of In₂O₃ and In₂O₃:PEI blend as the transistor channel (SGT-3). PEI incorporation in In₂O₃ layer under the source contact increases the potential drop at the source, thereby lowering the drain bias to pinch-off and achieving saturation versus the undoped (SGT-1) or single-layer doped (SGT-2) devices. Furthermore, using F:AlO_x as the gate dielectric in SGT-3 lowers the driving voltage, and thus V_{D_SAT}, to ~ +1.0 V, and further reduces power consumption to ~11.5 μW. Inverters based on these devices exhibit a high gain >5,000. Furthermore, real-time monitoring of human EOG signals using the present inverter shows a voltage gain of over 300. Finally, we demonstrated integration of the F:AlO_x dielectric in a SGT-3 device on a flexible substrate. Thus, this work provides an approach to the design and fabrication of solution-processed low-power metal oxide SGTs for promising implementation in a wide range of (opto)electronic applications.

Materials and Methods

Precursor Preparation.

In(NO₃)₃ (99.999%) and PEI (average M_W ~ 25,000 by LS; average Mn ~ 10,000 by GPC) were purchased from Sigma-Aldrich. For In₂O₃ precursors, appropriate amounts of the metal salt In(NO₃)₃·xH₂O were dissolved in deionized water to achieve a 0.1 M In concentration. PEI was also dissolved in DI water to reach a concentration of 20 mg/mL. After these solutions were each stirred for at least 6 h, the PEI solution was added to the metal oxide precursor solution to achieve the desired polymer weight fraction, indicated here as In₂O₃:x% PEI (x = 1, 2, 3, and 5 wt.%). After addition, the MO: polymer precursor solutions were stirred for at least for 8 h before use. For F:AlO_x precursor preparation, 93.78 mg of Al(NO₃)₃ was dissolved in 5.0 mL of 2-methoxyethanol (2-ME). Next, 25 μL of acetylacetone (HAcAc) and 11.25 μL of 14.5 M NH₃(aq) were added and the solution was stirred overnight (∼10 h) before film fabrication. Then, 1,1,1-trifluoro-2,4-pentanedione in 20 wt.% of the total weight of Al(NO₃)₃ was added to the above precursor solutions 1 h before spin-coating.

Thin-Film Fabrication and Electrical Characterization.

⁴³ All solutions were filtered through a 0.2-μm PTFE syringe filter before device fabrication. Highly doped (n⁺⁺) silicon and 100-nm-thick thermally grown SiO₂ (WRS Materials) were employed as the gate electrode and gate dielectric layer, respectively. The substrates were first cleaned by ultrasonication in acetone and isopropanol and then subjected to an O₂ plasma for 20 min. Next, the first MO layer (neat In₂O₃ or In₂O₃:PEI blend precursor) was spin-coated on substrates at 3,000 rpm for 30 s and subsequently annealed for 20 min at 250 °C (relative humidity ~ 30%). The second layer was then deposited by repeating the first layer spin-coating and annealing process with the desired precursor. Metal oxide semiconductor layer patterning was achieved by spin-coating S1813 photoresist (5,000 rpm for 30 s, 1.2 μm), followed by annealing at 115 °C for 1 min and then exposing in a Heidelberg Maskless Aligner model MLA150). Next, S1813 film was developed by soaking in AZ 400 for 60 s, and the films were then rinsed with water and dried under an N₂ flow. The exposed oxide film was then etched with oxalic acid (10% w/v in water) for 30 s and rinsed with water. The remaining S1813 film was then washed away with acetone, and the samples then rinsed with isopropanol. Next, the samples were further annealed at 250 °C for 5 min to remove any residual solvent. All patterning processes were carried out in a clean room. Finally, the source/drain electrodes were fabricated using a lift-off process. The desired S1813 photoresist pattern was achieved following the same procedure as provided above, followed by thermal evaporation of 40 nm Al or Au. Finally, the source/drain pattern was created by dissolving the S1813 in acetone, and the samples were rinsed with isopropyl alcohol.

For the low-voltage SGT fabrication, the F:AlO_x precursor solutions were spin-coated onto the highly doped (n⁺⁺) silicon substrates at 3,500 rpm for 30 s in a controlled atmosphere box [relative humidity (RH) < 20%] and pre-annealed at 120 °C for 60 s (RH ∼ 35%), followed by annealing on a ∼300 °C hot plate for 1 min (RH ∼ 35%). This procedure was repeated four times to obtain the desired film thickness (~20 nm). Then the devices were completed by fabricating an MO bilayer and source/drain electrodes following the same procedure as that of SGTs fabricated with 100 nm SiO₂.

For the flexible SGT fabrication, polyimide film (PI, 25 μm thick) substrates were cleaned by ultrasonication in acetone and isopropanol and then subjected to an O₂ plasma for 10 min. Bottom gate electrodes patterning was carried out by spin-coating an nlf2035 photoresist (5,000 rpm for 30 s, 1.2 μm), which was annealed at 115 °C and then were patterned using photolithography (Heidelberg Maskless Aligner MLA150) for high-quality films. The films were then annealed again at 115 °C. Next, the nlf2035 film was developed by soaking in AZ 300 for 60 s, and the films were rinsed with water and dried under an N₂ flow, followed by thermal evaporation of Cr/Au (3 nm/20 nm). The remaining nlf2035 film was then washed by the same procedure with S1813. Then the F:AlO_x dielectric, MO bilayers, and source/drain electrodes were fabricated following the same procedure as provided above for the low-voltage SGTs.

Transistor and inverter electrical characterization was performed on devices stored under a flow of nitrogen (RH < 10%) and within 3 d of fabrication using an Agilent B1500A semiconductor parameter analyzer with a probe station. For flexible device fabrication, the flexible substrate (PI) was attached to a glass carrier during fabrication. The flexible SGT was bent with the PI substrate and de-bonding was unnecessary. For inverter measurements, the current source was generated by an Agilent B1500A. For the EOG monitoring, a 31-y-old healthy male participated in the experiments, which were conducted safely without any external stimulus. Before the experiments, the subject was trained on how to move the eyeballs and was also instructed not to speak to avoid any interference. During the test, two adhesive electrodes (3M Red Dot 2,238) were placed on the upper/lower or left/right sides of the eye sockets, respectively. The V_D-C and V_SS were supplied by an Agilent B1500A semiconductor parameter analyzer and properly adjusted to make sure that the switching voltage was ~0 V, which is critical to the EOG monitoring to make sure a tiny voltage can reverse the signal. The lower or left adhesive electrode was directly connected to the V_in. The amplified EOG signal was also recorded by monitoring V_out using Agilent B1500A. The EOG experiment involving human subjects described in this research was assigned as “Not Human Research” by the Institutional Review Board of the Northwestern University. A subject consent was signed before participating in the research, and the authors are very grateful to the participant for involvement in this study.

Surface Potential Characterization.

KPFM measurements of SGT-1 and SGT-3 were carried out with a commercial Bruker Dimension Icon AFM. LabVIEW-controlled Keithley 2400 source-meters were used to apply a drain and gate bias to the devices and to measure the device current during the surface potential measurements. The surface potentials were measured with PeakForce KPFM configuration, where the Pt/Ir-coated conductive tips (NanoAndMore PPP-EFM) were lifted 50 to 70 nm from the sample surface.

Supplementary Material

Appendix 01 (PDF)

Data, Materials, and Software Availability

All study data are included in the article and/or SI Appendix.