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Science Advances logoLink to Science Advances
. 2024 Sep 4;10(36):eadp6388. doi: 10.1126/sciadv.adp6388

High-performance fault-tolerant quantum computing with many-hypercube codes

Hayato Goto 1,2,*
PMCID: PMC11373590  PMID: 39231228

Abstract

Standard approaches to quantum error correction for fault-tolerant quantum computing are based on encoding a single logical qubit into many physical ones, resulting in asymptotically zero encoding rates and therefore huge resource overheads. To overcome this issue, high-rate quantum codes, such as quantum low-density parity-check codes, have been studied over the past decade. In this case, however, it is difficult to perform logical gates in parallel while maintaining low overheads. Here, we propose concatenated high-rate small-size quantum error-detecting codes as a family of high-rate quantum codes. Their simple structure allows for a geometrical interpretation using hypercubes corresponding to logical qubits. We thus call them many-hypercube codes. They can realize both high rates, e.g., 30% (64 logical qubits are encoded into 216 physical ones), and parallelizability of logical gates. Developing dedicated decoder and encoders, we achieve high error thresholds even in a circuit-level noise model. Thus, the many-hypercube codes will pave the way to high-performance fault-tolerant quantum computing.


Proposed quantum error-correcting codes allow for high encoding rates, high performance, and a beautiful geometrical code structure.

INTRODUCTION

Quantum computers have been expected to outperform current classical computers by harnessing quantum superposition states. However, the quantum superpositions are notoriously fragile. The so-called decoherence leads to many errors in quantum computers, spoiling quantum computation. A standard approach to this issue is quantum error correction. Careful use of quantum error-correcting codes can protect quantum computation from errors, which is called fault-tolerant quantum computation (13). A standard quantum error-correcting code for this purpose is the surface code (410), which requires only a two-dimensional qubit array with nearest-neighbor interactions and therefore is suitable for, e.g., superconducting-circuit implementations (1113). However, the surface code uses many physical qubits to protect a single logical qubit. More precisely, the number of physical qubits to encode a single logical qubit is the square of the code distance, where the code distance characterizes the code size and we can, in principle, correct arbitrary physical-qubit errors if their number is less than half the code distance. This means that the encoding rate defined as the ratio of the number of logical qubits to that of physical qubits vanishes rapidly as the code size becomes larger, resulting in large resource overheads (1416).

In contrast, quantum low-density parity-check (qLDPC) codes (17) are known for their ability to achieve constant encoding rates and therefore have been studied over the past decade to mitigate the above overhead issue (18, 19). Various kinds of qLDPC codes have been proposed (2028), high-performance decoders for them have also been developed (2935), and their physical implementations have recently been proposed (3640). However, they have relatively complex structures, making it difficult to implement logical gate operations in a fault-tolerant manner. A few methods for this purpose have been proposed (18, 3943), but parallel execution of logical gates maintaining the advantage of the qLDPC codes, i.e., low overheads, is still challenging.

Recently, a completely different approach to the constant encoding rate has been proposed (44), which is based on a more conventional approach called code concatenation. Concatenation means recursive encoding with multiple codes. By increasing the encoding rates for higher concatenation levels, this proposal achieved a finite rate for the infinite code size. This also allows for parallel execution of logical gates with constant overheads, unlike qLDPC codes. In other words, this proposal offers time-efficient, constant-space-overhead fault-tolerant quantum computation. However, this approach based on quantum Hamming codes has two issues. First, the encoding rate is not very high, converging to 1/36. Second, the decoding of the concatenated codes is based on hard-decision decoding, which is known to be suboptimal and has relatively low performance.

In this work, we propose another family of high-rate concatenated quantum codes. The characteristic feature of our proposal is the use of quantum error-detecting codes (2), which have distance 2 and therefore can detect an error but cannot correct it. By concatenating the error-detecting codes, we can increase the code distance and thus obtain error-correcting codes. The advantage of the quantum error-detecting codes is their simple structure. Harnessing this advantage, Knill proposed concatenated quantum error-detecting codes called the C4/C6 scheme and achieved the realization of the error threshold exceeding 1% in a circuit-level noise model (45). [Recently, the concatenation of the C4/C6 scheme and the concatenated quantum Hamming codes mentioned above has been proposed to improve the performance of the latter (46), but this still has the above-mentioned two issues, that is, the rate becomes rather lower and the decoding is still based on hard-decision decoding.] However, the C4/C6 scheme is based on a single-logical-qubit encoding, like the surface code, and therefore its encoding rate approaches zero rapidly as the code size increases. Unlike the C4/C6 scheme, the proposed concatenated codes have high encoding rates. In this work, we focus on the ⟦6,4,2⟧ code, which encodes four qubits into six qubits and has distance 2. (The reason for choosing this code is its relatively high rate and small size. The use of other codes, such as ⟦4,2,2⟧ and ⟦8,6,2⟧, is also interesting but left for future work.) By concatenating it (L − 1) times, we obtain the ⟦N(L), K(L), D(L)⟧ = ⟦6L,4L,2L⟧ code, which we refer to as the ⟦6L,4L,2L⟧ level-L many-hypercube code or simply the level-L many-hypercube code for the reason explained later. Although it is not a constant-rate code, that is, its rate, K(L)/N(L) = (4/6)L, approaches zero as L becomes larger, the rate is remarkably high for small L, e.g., 30% (20%) at level 3 (4) with distance 8 (16), which is higher than not only the surface code but also well-studied qLDPC codes (3640). Thus, the many-hypercube codes will be promising as a near-term target. Note that the number of logical qubits is not limited to K(L) = 4L. Using M code blocks encoded with the level-L many-hypercube code as fault-tolerant quantum registers (44), we can use MK(L) logical qubits for fault-tolerant quantum computing.

We developed a high-performance decoder dedicated to the many-hypercube codes based on level-by-level minimum distance decoding. (Our proposed decoding method will also be useful for other concatenated codes, such as the above concatenated quantum Hamming codes.) Using this decoder, we achieved a threshold of 5.6% for bit-flip errors, which is comparable to the surface code (10.9%) (47) and a 4%-rate qLDPC (hypergraph product) code (7.5%) (33). We also propose fault-tolerant zero-state encoders for the many-hypercube codes. Using them, we achieved a threshold of 0.9% for a logical controlled-NOT (CNOT) gate in a circuit-level noise model. Last, we explain how to perform logical gates for the many-hypercube codes in parallel.

RESULTS

Many-hypercube codes

We start with the definition of the ⟦6,4,2⟧ code. The ⟦6,4,2⟧ code is one of the simplest stabilizer codes (3) and has only two stabilizer generators (check operators): SZ = Z1Z2Z3Z4Z5Z6 and SX = X1X2X3X4X5X6, which can detect an X (bit-flip) error and a Z (phase-flip) error, respectively, in its six-qubit code block (see Materials and Methods for the definitions of elementary gates). Its four logical qubits are defined by the following logical Z and X operators

ZL1=Z1Z2,XL1=X2X3 (1)
ZL2=Z2Z3,XL2=X1X2 (2)
ZL3=Z4Z5,XL3=X5X6 (3)
ZL4=Z5Z6,XL4=X4X5 (4)

Other definitions are possible (2), but we use this because of the geometrical interpretation of the code structure using hypercubes explained below. By the definition, the logical all-zero state of the ⟦6,4,2⟧ code is the six-qubit Greenberger-Horne-Zeilinger (GHZ) state

0000L=000000+1111112 (5)

Therefore, the zero-state encoder of the ⟦6,4,2⟧ code is given by, e.g., the quantum circuit shown in Fig. 1A. This can be generalized to an arbitrary-state encoder by adding two CNOT gates, as shown in Fig. 1B. The logical SWAP gates between the logical qubits 1 and 2, 3 and 4, and (1,2) and (3,4) can be performed by physical SWAP gates between the physical qubits 1 and 3, 4 and 6, and (1,2,3) and (4,5,6), respectively, as shown in Fig. 1C. We can also easily find that transversal logical CNOT and Hadamard gates can be performed by transversal physical CNOT and Hadamard (and SWAP) gates, respectively, as shown in Fig. 1 (D and E).

Fig. 1. Encoders and logical gates of the ⟦6, 4, 2⟧ code.

Fig. 1.

(A) Zero-state encoder. (B) Arbitrary-state encoder. In (B), additional two CNOT gates are highlighted in red. (C) Logical SWAP gates. (D) Transversal logical CNOT gates. (E) Transversal logical Hadamard gates. In (C) to (E), the left and right sides correspond to logical and physical ones, respectively.

Using the ⟦6,4,2⟧ code recursively, e.g., the level-3 many-hypercube code is defined as follows. Each of the physical and encoded qubits is labeled by three integers (corresponding to the three levels) and denoted by Q with subscripts of the integers. The corresponding operators are also labeled similarly. The four level-1 qubits Qi,j,k1i=1,,4 are encoded into the corresponding six physical qubits {Qi,j,ki = 1, …,6} with the ⟦6,4,2⟧ code (j,k = 1, …,6), where the two stabilizers and encoded Z and X operators are defined as follows

SZj,k1=i=16Zi,j,k (6)
SXj,k1=i=16Xi,j,k (7)
Z1,j,k1=Z1,j,kZ2,j,k,X1,j,k1=X2,j,kX3,j,k (8)
Z2,j,k1=Z2,j,kZ3,j,k,X2,j,k1=X1,j,kX2,j,k (9)
Z3,j,k1=Z4,j,kZ5,j,k,X3,j,k1=X5,j,kX6,j,k (10)
Z4,j,k1=Z5,j,kZ6,j,k,X4,j,k1=X4,j,kX5,j,k (11)

Similarly, the four level-2 qubits Qi,j,k2j=1,,4 are encoded into the corresponding six level-1 qubits Qi,j,k1j=1,,6 (i′ = 1, …,4, k = 1, …,6) and the four level-3 qubits Qi,j,k3k=1,,4 are encoded into the corresponding six level-2 qubits Qi,j,k2k=1,,6 (i′,j′ = 1, …,4). In this case, we use the 64 level-3 encoded qubits as logical qubits in a fault-tolerant quantum register for quantum computing. In general, the level-L many-hypercube code is defined similarly.

The above code structure can be visualized as shown in Fig. 2 by placing the physical qubit Qi,j,k at the point with the coordinates (x, y, z) = (i, j, k) in a three-dimensional space, where the logical Z and X operators correspond to cubes. For example

Z1,1,13=Z1,1,12Z1,1,22=Z1,1,11Z1,2,11Z1,1,21Z1,2,21=Z1,1,1Z2,1,1Z1,2,1Z2,2,1Z1,1,2Z2,1,2Z1,2,2Z2,2,2 (12)
X1,1,13=X1,1,22X1,1,32=X1,2,21X1,3,21X1,2,31X1,3,31=X2,2,2X3,2,2X2,3,2X3,3,2X2,2,3X3,2,3X2,3,3X3,3,3 (13)

are highlighted in light blue and pink, respectively, in Fig. 2. Also, the level-l stabilizers correspond to l-dimensional objects on the cubes, e.g., as follows

SZ1,41=i=16Zi,1,4 (14)
SX1,51=i=16Xi,1,5 (15)
SZ1,62=j=16Z1,j,61=j=16Z1,j,6Z2,j,6 (16)
SX1,62=j=16X1,j,61=j=16X2,j,6X3,j,6 (17)
SZ3,13=k=16Z3,1,k2=k=16Z3,1,k1Z3,2,k1=k=16Z4,1,kZ5,1,kZ4,2,kZ5,2,k (18)
SX3,23=k=16X3,2,k2=k=16X3,1,k1X3,2,k1=k=16X5,1,kX6,1,kX5,2,kX6,2,k (19)

which are also highlighted in light blue (SZ) and pink (SX) in Fig. 2.

Fig. 2. Visualization of the structure of the level-3 many-hypercube code.

Fig. 2.

The vertices correspond to physical qubits. Examples of logical Z and X operators and stabilizers in Eqs. 12 to 19 are highlighted in light blue (Z) and pink (X).

In general, in a similar visualization, the logical Z and X operators of the level-L many-hypercube code correspond to L-dimensional hypercubes in an L-dimensional space and also its level-l stabilizers correspond to l-dimensional objects on the hypercubes, where the number of the hypercubes is equal to that of the logical qubits. This is the reason for the name of the proposed code. [The “many” is used to distinguish it from a conventional hypercube code (48), which is the ⟦2D, D,2⟧ code defined on a single D-dimensional hypercube.]

The number of the vertices of each L-dimensional hypercube, 2L, is equal to the code distance. That is, the size of the many-hypercube codes is increased by increasing not the edge length but the dimension while keeping the edge length. In contrast, the logical operators and stabilizers of topological codes, such as the surface code (410) and the color code (4952), correspond to the edges and faces, respectively, and their code sizes are increased by increasing the edge length. Unlike the topological codes, the many-hypercube codes require interactions beyond nearest-neighbor ones. This is experimentally challenging, but recent experimental advances in ion-trap (5359) and neutral-atom (6063) systems are encouraging. Hypercube connectivity has already been realized experimentally (63).

Decoders

In this work, we investigated three decoding methods for the many-hypercube codes. The first one is Knill’s method proposed for the C4/C6 scheme (45), which we refer to as hard-decision decoding. The second one is soft-decision decoding based on a posteriori probability calculation (64, 65). The original soft-decision decoding is based on block-MAP (maximum a posteriori probability) decoding, which cannot be applied directly to high-rate codes such as the many-hypercube codes because then we must calculate a posteriori probabilities for an exponentially large number of codewords. We thus modified it to symbol-MAP decoding applicable to high-rate codes. The third one is our proposed method based on level-by-level minimum distance decoding, where we keep only minimum-distance codewords from measurement outcomes as candidates at each level from level 1 to the logical level. See Materials and Methods and the Supplementary Materials for the details of the three methods.

In the following, we assume that error correction is done by error-correcting teleportation (ECT) (45, 65, 66). This is quantum teleportation with logical qubits, where the classical feed-forward information is determined by decoding physical-qubit measurement outcomes, as shown in Fig. 3. Thus, the decoding is the task to estimate the measurement outcomes of logical qubits from those of physical ones in the logical Bell measurements. Note that, in ECT, we obtain all the syndrome information at once; no need to repeatedly measure them one by one, unlike the Shor method (1, 18) used for the surface code and qLDPC codes. Assuming that the two ancilla registers used for the quantum teleportation are reliable sufficiently, the errors in ECT come mainly from the decoding error. Also note that all the errors to be decoded are included in the physical-qubit measurement errors in the Bell measurement, and therefore in the case of ECT, decoders designed for independent physical-qubit errors are directly applicable to circuit-level noise models. In this work, we also assume that all the measurements are done in the Z basis {|0⟩, |1⟩}, resulting in bit-value outcomes.

Fig. 3. Error-correcting teleportation.

Fig. 3.

The input logical-qubit state encoded with the level-L many-hypercube code, |ψ⟩L, on the left side is teleported with two logical all-zero states to the right side. The gray bold arrows show the flow of the classical information. The “D” boxes are the decoders, which decode the physical-qubit measurement outcomes and provide logical-qubit ones. If a logical-qubit outcome is 1, then the corresponding logical Z or X operator is performed on the corresponding logical qubit. The transversal logical CNOT and Hadamard gates are performed by transversal physical CNOT and Hadamard gates, as shown in Fig. 1 (D and E), respectively.

We numerically evaluated the performance of the three decoding methods using a bit-flip error model (see Materials and Methods for details). In this work, stabilizer quantum-circuit simulations in our numerical study were done using a Python package called Stim (67). The decoding error probabilities estimated by the simulations are shown in Fig. 4. First, the exponents of the power-function fits for the hard-decision decoding are smaller than half the code distance, as in the case of the C4/C6 scheme (65), which shows its suboptimality. On the other hand, the exponents for the other two are near to or even exceed half the distance, showing their high performance. Second, the error thresholds are estimated at 1.1, 1.5, and 5.6%, respectively, and only our minimum distance decoding is comparable to the surface code (10.9%) (47) and a well-studied qLDPC (4%-rate hypergraph product) code (7.5%) (33). Thus, our proposed decoding method achieves the highest performance among the three methods.

Fig. 4. Performance of three decoders of the many-hypercube codes for bit-flip errors.

Fig. 4.

(A) Hard-decision decoder. (B) Symbol-MAP decoder. (C) Level-by-level minimum distance decoder. The exponents are estimated by fitting a power function to the linear parts of the log-log plots. The thresholds indicated by arrows are defined by the intersection points of the level-3 and level-4 curves. See Materials and Methods for the details of the three decoding methods and the simulation.

Fault-tolerant zero-state encoders

Hereafter, we consider a circuit-level noise model with error rate pcirc. In this work, we assume the following noise model. Each of the physical-qubit zero-state preparation and Z-basis measurement is accompanied by a bit flip with probability pcirc, and each two-qubit (CNOT) gate is followed by 1 of 15 two-qubit Pauli errors with equal probability pcirc/15 (8). On the other hand, we assume no single-qubit-gate and memory errors for simplicity. This model is relevant for ion-trap (5359) and neutral-atom (6063) systems. (Even for these systems, it is eventually desirable to consider the effect of the neglected errors, but it requires thorough optimization of time overheads and therefore is left for future work.)

In such a circuit-level noise model, we cannot use the non-fault-tolerant encoders in Fig. 1 (A and B) because of undetectable correlated errors due to CNOT gates in a code block. We thus modify the zero-state encoder at each level as follows. In the following, we use various kinds of error detection and repeat encoding until no error is detected.

For the encoding of the level-1 all-zero state, which is the six-qubit GHZ state as shown in Eq. 5, we can use the well-known fault-tolerant GHZ-state preparation method with an ancilla qubit shown in Fig. 5A. We accept the encoding if the measurement outcome of the ancilla qubit is 0, otherwise reject and restart it from the beginning. Thus, logical X errors can be eliminated. (Logical Z errors do not occur on the logical all-zero state.) To evaluate the space and time overheads for the zero-state encoders, here we introduce the total number of physical qubits including ancilla ones, N(L), and the circuit depth including state preparation and measurement, T(L), respectively, required for the level-L zero-state encoder. From Fig. 5A, we obtain

N1=7,T1=8 (20)

Fig. 5. Fault-tolerant zero-state encoders of the many-hypercube codes.

Fig. 5.

(A) Level-1 zero-state encoder. The inputs are seven physical qubits in zero states. The CNOT and Hadamard gates are physical ones. (B) Level-2 zero-state encoder. The measurement outcomes of the level-1 encoded ancilla qubits are obtained by decoding the physical-qubit outcomes with the hard-decision decoding for error detection (see Materials and Methods). The encoding is repeated until no error is detected and all the level-1 outcomes are 0. (C and D) Level-1 Z-error and X-error detection gadgets (EDZL1 and EDXL1), respectively, used for the level-2 zero-state encoder in (B). Errors are detected unless both the measurement outcomes of the two ancilla qubits are 0. (E and F) Level-2 Z-error and X-error detection gadgets (EDZL2 and EDXL2), respectively, used for the level-3 zero-state encoder. Errors are detected unless none of the outcomes of the minimum distance decoding for error detection with LD = 1 is F (see Materials and Methods). (G) Level-4 zero-state encoder. EDTL3 denotes a level-3 EDT gadget, where the minimum distance decoding for error detection with LD = 2 is used (see Materials and Methods). The same decoding is used for decoding the measurement outcomes of the two ancilla registers. The encoding is repeated until no error is detected and all the parities of the outcomes of the level-3 encoded-qubit pairs in the two ancilla registers are even, where if both the outcomes of a pair are 1, we perform encoded X gates on the first half of the six level-3 encoded qubits.

We cannot apply this method directly to level 2 because of uncorrectable intrablock errors. Also, the low-depth circuit for the GHZ-state preparation in Fig. 5A results in many error-detection gadgets to eliminate the intrablock Z errors. To achieve fault tolerance with minimum effort at level 2, we propose the level-2 zero-state encoder shown in Fig. 5B, where the control qubits of the CNOT gates concentrate on a single qubit to eliminate the intrablock Z errors by a single error-detection gadget. To eliminate intrablock and logical X errors, we also need only a single error-detection gadget and ancilla-qubit measurement. To minimize space overheads, the level-1 error-detection gadgets are implemented by the flag-based method with two physical ancilla qubits and depth 12 in Fig. 5 (C and D) (68). The transversal encoded CNOT and Hadamard gates can be performed fault-tolerantly by transversal physical gates with depths 1 and 2, respectively, as shown in Fig. 1 (D and E). Optimizing the overlaps of physical operations to minimize the time overhead, we obtain

N2=N1×7+2×2=53,T2=T1+2+6+122=26 (21)

Note that the space overhead, i.e., the total number of physical qubits, can be reduced by reusing the ancilla qubits, but then the time overhead will increase. Also note that we can use the Steane method with an encoded ancilla qubit (69) for the error-detection gadgets, which, in the level-2 case, are shown in Fig. 5 (E and F), but this results in larger space overheads and no performance improvement (see the Supplementary Materials). This is because, at level 1, we only need to measure just a single weight-6 stabilizer, which can be achieved most easily by the flag-based method.

The level-3 zero-state encoder is the same as the level-2 one in Fig. 5B if the levels are raised by one, but level-2 error-detection gadgets are implemented by the above-mentioned Steane method (69) shown in Fig. 5 (E and F). This is because, at level 2, we need to measure six weight-6 level-1 stabilizers and four weight-12 level-2 stabilizers, which can be achieved by the Steane method more easily than the Shor method with physical ancilla qubits. From Fig. 5 (B, E, and F), we obtain

N3=N2×7+N2×2=477,T3=T2+2+6+4=38 (22)

where, and in the following, decoding is not counted for time-overhead evaluation.

Although the encoder in Fig. 5B can also be applied to the level-4 case, then the acceptance probabilities at error-detection gadgets become too low if we use the most stringent condition for error detection. To mitigate this issue, we can relax the error-detection condition (see Materials and Methods), but then the logical gate performance becomes low. (See the Supplementary Materials for the results using the encoder in Fig. 5B at level 4.) To improve the performance, we propose the level-4 zero-state encoder shown in Fig. 5G, which uses two level-3 four-qubit GHZ states with error-detecting teleportation (EDT) gadgets eliminating intrablock Z and X errors simultaneously. The reason why this encoder can achieve higher performance than that in Fig. 5B is that the intrablock errors in two four-qubit GHZ states are independent and therefore detectable with high probability by the ancilla measurements. From Figs. 3 and 5G, we obtain

N4=N3×8+N3×2×2=5724,T4=T3+2+3+4=47 (23)

where, and in the following, Pauli operations are not counted for time-overhead evaluation.

As numerically shown below, the encoders in Fig. 5 well satisfy fault tolerance. The time overheads evaluated above are almost proportional to the level. (The effect of postselection at error-detection gadgets is discussed later.) On the other hand, the logical-gate error rates decrease doubly exponentially with respect to the level, as numerically shown later. These facts suggest that the encoding only needs doubly logarithmic time overheads with respect to computational size and hence is time efficient (44). Although the space overheads increase more rapidly, the net encoding rates defined by K(L)/N(L) including ancilla qubits are still relatively high, higher than 4% even at level 4. (The encoding rate for the same-distance surface code is 1/162 ≃ 0.4% even without ancilla qubits.) Further optimization of the space and time overheads may be possible but is left for future work.

The comparison with the C4/C6 scheme (45, 65) is as follows. The parameters of the C4/C6 scheme are given by N(L) = 4 × 3L−1, K(L) = 1 (or 2), D(L) = 2L, and N(L) = 4 × 12L−1 (65). By a similar technique to the one for the GHZ states in Fig. 5G, the number of physical qubits may be reduced to N(L) = 5L. Then, the net encoding rate at level 4 is K(4)/N(4) = 0.16% (or 0.32%), which is much lower than that of the level-4 many-hypercube code, as expected. On the other hand, the logical CNOT performance of the C4/C6 scheme (65) is much higher than that of the many-hypercube codes presented below. This may be due to the high rates of the many-hypercube codes and the optimal (block-MAP) decoder for the C4/C6 scheme.

Logical gate operations

Arbitrary encoded Pauli gates can easily be performed fault-tolerantly by physical Pauli gates [or the so-called Pauli frame (45, 66)] according to the definitions of the encoded Pauli operators, e.g., in Eqs. 12 and 13.

Logical SWAP gates can also be performed easily by physical SWAP gates or renumbering of physical qubits as follows. The level-1 encoded SWAP gates are performed as shown in Fig. 1C.At higher levels, e.g., at level 3, simultaneous physical SWAP gates {Q1,j,k ↔ Q3,j,kj,k = 1, …,6} result in simultaneouslogical SWAP gates Q1,j,k3Q2,j,k3j,k=1,,4 Similarly, Qi,3,k3Qi,4,k3i,k=1,,4 and Qi,j,13,Qi,j,23Qi,j,33,Qi,j,43i,j=1,,4 are performed by corresponding simultaneous physical SWAP gates, {Qi,4,k ↔ Qi,6,ki,k = 1, …,6} and {(Qi,j,1, Qi,j,2, Qi,j,3) ↔ (Qi,j,4, Qi,j,5, Qi,j,6) ∣ i, j = 1, …,6}, respectively. In general, we can perform simultaneous logical SWAP gates between the logical qubits corresponding to the hypercubes on two parallel hyperplanes by simultaneous physical SWAP gates.

For the other gates necessary for universal computation (see Materials and Methods), we first consider the case where the same gate is performed on all the encoded/physical qubits in a code block, which we refer to as full transversal gates. If the same gate is performed on only some specified qubits in a code block, then we call it partial transversal gates, which is harder to implement.

From Fig. 1 (D and E), full transversal logical CNOT and Hadamard gates can be performed fault-tolerantly by full transversal physical CNOT and Hadamard gates (and physical SWAP gates) followed by ECT gadgets. Their time overheads are dominated by the ECT gadgets, which are estimated at T(L) + 7 in the level-L case from Fig. 3 and therefore time efficient. We numerically evaluated the performance of the full transversal logical CNOT gates using the above-mentioned circuit-level noise model (see Materials and Methods for details). The logical CNOT error probabilities estimated by the simulation are shown in Fig. 6A. The error threshold is estimated at 0.9%, which is comparable to the surface code (1.1%) (70) and a recently developed qLDPC quantum memory (0.7%) (40). Also, the exponents of the power-function fits are close to half the code distance, showing that the logical CNOT gates (and the zero-state encoders in Fig. 5) well satisfy fault tolerance. (The level-4 value at pcirc = 10−3 seems an outlier, resulting in a smaller exponent, e.g., 7, in the range of pcirc ≤ 10−3 than that estimated by fitting, 7.8, shown in Fig. 6A. The exponent smaller than half the code distance may be due to the relaxation of the error-detection condition mentioned above.)

Fig. 6. Performance of full transversal logical CNOT gates for the many-hypercube codes in the circuit-level error model.

Fig. 6.

(A) Each circle shows the error probability per logical CNOT gate for error rate pcirc. The dotted lines are power-function fits to the five data points from the lowest, from which the exponents are estimated. (B) Total number of physical qubits required for the preparation of a logical all-zero state. See Materials and Methods for the details of the simulation and the main text for the definition of the error model.

In the above simulation of logical CNOT gates, we also estimated the expectation value of N(L) taking the effect of postselection and restart into account. The results are shown in Fig. 6B. It turns out that we need pcirc ≤ 10−3 to keep the space-overhead increase rate due to postselection less than 2 even at level 4. This will be achievable for ion-trap and neutral-atom systems (38).

Next, we consider full transversal logical phase and non-Clifford gates, S and RY(π/4) (see Materials and Methods for their definitions). It is known that these two gates can be performed using ancilla qubits in |Y=0+i1/2 and H=cosπ80+sinπ80 , respectively, together with CNOT and Hadamard gates (see Fig. 7, A and B), where |Y⟩ and |H⟩ are the eigenstates of Y and H, respectively, with eigenvalue 1 (15, 71). Therefore, the full transversal logical S and RY(π/4) require to fault-tolerantly prepare the level-L logical YLKL and HLKL , which can be achieved by non-fault-tolerant encoding with the arbitrary-state encoder in Fig. 1B followed by state distillation and level-raising teleportation, as originally proposed for the C4/C6 scheme (71). (The full transversal logical non-Clifford gates also need partial transversal logical Hadamard gates depending on the measurement outcomes, which are explained later.) We propose the 2-to-1 distillation method for YLKL based on HS|Y⟩ = |1⟩ shown in Fig. 7C. Note that our method needs only two noisy YLKL , unlike the well-known 7-to-1 distillation method with the Steane code (15). This difference comes from the fact that the many-hypercube codes are based on distance-2 codes and therefore do not need distance-3 codes, such as the Steane code, for distillation. For HLKL , we can use, e.g., the standard 14-to-2 distillation method based on the distance-2 H6 code (71, 72). The level-raising teleportation shown in Fig. 7D can convert four distilled YL1KL1 and HL1KL1 to YLKL and HLKL , respectively, in a fault-tolerant manner (71).

Fig. 7. Logical phase and non-Clifford gates.

Fig. 7.

(A and B) Full transversal logical phase and non-Clifford gates, S and RY(π/4), respectively. In (B), the measurement outcomes are decoded, and the logical Z and H are performed if the corresponding decoding outcome is 1. (C) Proposed 2-to-1 distillation for YLKL . The distillation is accepted if all the decoding outcomes are 1. (D) Level-raising teleportation. The box “Encode−1” is the gadget performing the inversion of the arbitrary-state encoder in Fig. 1B, outputting four level-(L−1) states, where the other two level-(L−1) blocks are measured and decoded by an error-detection decoder, and the Bell-state preparation is repeated until no error is detected and all the decoding outcomes are 0. In the Bell measurements, the measurement outcomes are also decoded by an error-detection decoder (71).

In the following, we consider partial transversal logical gates. using an ancilla register where some logical qubits are in +=H0=0+1/2 and the others in |0⟩, which we refer to as partial |+⟩ states, together with full transversal logical CNOT and Hadamard gates and an ECT gadget, as shown in Fig. 8A. (The ECT gadget is necessary to prevent intrablock errors from spreading through the logical CNOT and Hadamard gates.) Logical partial |+⟩ states can be prepared fault-tolerantly in a similar manner to YLKL and HLKL explained above. At level 1, we can fault-tolerantly prepare encoded partial |+⟩ states more efficiently than state distillation, as follows. Any level-1 encoded partial |+⟩ state can be prepared by one of the three methods in Fig. 8 (B to D). The first and second encoders in Fig. 8 (B and C) are based on the fact that some level-1 partial |+⟩ states can be expressed with only the Bell state, 00+11/2 , and the four-qubit GHZ state by definition. The third encoder in Fig. 8D is obtained from the arbitrary encoder in Fig. 1B followed by verification with minimum effort through the measurements of an encoded Z operator and an encoded X operator, in a similar manner to the most efficient fault-tolerant Steane-code encoder with a single ancilla qubit (73). Applying the level-raising teleportation to the resultant level-1 partial |+⟩ states, we obtain level-2 partial |+⟩ states. At higher levels, we use the 4-to-1 distillation method shown in Fig. 8E.

Fig. 8. Partial transversal logical Hadamard gates.

Fig. 8.

(A) Partial transversal logical Hadamard gates with a logical partial |+⟩ state and full transversal logical CNOT and Hadamard gates. The logical Z (X) is performed if the decoding outcome is 0 (1). (B to D) Fault-tolerant preparation methods for level-1 logical partial |+⟩ states. The other ones can also be prepared similarly to one of the three through SWAP gates and full transversal Hadamard gates. (E) 4-to-1 distillation for a logical partial |+⟩ state. This is repeated until no error is detected and all the decoding outcomes are consistent with the input state.

The total number of physical qubits and circuit depth for the preparation of a level-L logical partial |+⟩ state, which are denoted by N+L and T+L , respectively, are estimated from Figs. 7D and 8 (D and E) in the worst-case scenario where all the level-1 blocks are encoded by the encoder in Fig. 8D as follows

N+1=8,T+1=9 (24)
N+2=N+1×4+N2×2=138,T+2=T+1+6+4=20 (25)
N+3=N+2×4×4+N3×2=3162,T+3=T+2+6+4=30 (26)
N+4=N+3×4×4+N4×2=62040,T+4=T+3+6+4=40 (27)

Although this preparation is time efficient, the space overheads are considerably larger than those for the encoded all-zero states. More efficient encoding of partial |+⟩ states may be possible but left for future work.

From Fig. 7 (A and B), we can perform partial transversal logical S and RY(π/4) by replacing the full transversal logical Hadamard gates with partial ones explained above because then the two logical CNOT gates on the qubits without logical Hadamard gates are cancelled out.

Partial transversal logical CNOT gates between two registers (interblock logical CNOT gates) can be performed using two ancilla registers in the same partial |+⟩ state and full transversal logical CNOT and Hadamard gates, as shown in Fig. 9A. In this case, each logical CNOT gate is performed on the corresponding two logical qubits with the same label in the two registers. Using logical SWAP gates explained above, we can perform at least a logical CNOT gate on an arbitrary logical-qubit pair between the two registers. Last, logical CNOT gates in a register (intrablock logical CNOT gates) can be performed with an ancilla register in the logical all-zero state, logical SWAP gates, and interblock full and partial transversal logical CNOT gates, as shown in Fig. 9B.

Fig. 9. Logical CNOT gates.

Fig. 9.

(A) Interblock partial transversal logical CNOT gates with two ancilla registers in the same partial |+⟩ states. The Z and X are performed if the corresponding decoding outcome is 1. Then, the logical CNOT gates denoted by UCNOT are performed on the logical qubits corresponding to |+⟩ of the partial |+⟩ state in the control and target states, |ψc⟩ and |ψt⟩, respectively. (B) Intrablock logical CNOT gates using an ancilla register in the logical all-zero state. The first and third CNOT gates highlighted in red are partial transversal logical CNOT gates on the control qubits of the logical CNOT gates to be performed on |ψ⟩L. (The second one is full transversal logical CNOT gates.) The SWAP gate moves the logical qubits corresponding to the control qubits to the ones corresponding to the target qubits of the logical CNOT gates to be performed. They are returned to the original positions by the SWAP−1 gate. Thus, the desired intrablock logical CNOT gates denoted by UCNOT are performed on |ψ⟩L.

Thus, we can implement a universal gate set for the many-hypercube codes fault-tolerantly and perform most of them in parallel. For qLDPC codes, we can, in principle, achieve parallel execution of logical gates in a similar manner, but then logical ancilla states required for it are difficult to prepare, which may need another high-threshold code such as concatenated Steane codes (18). To overcome the ancilla-preparation issue, a current standard approach to logical gates for qLDPC codes uses the teleportation between a logical qubit in a qLDPC quantum memory and another logical qubit encoded with, e.g., the surface code (39, 40), where logical gates are performed on the surface-code logical qubits. Then, however, parallel execution of N logical gates requires at least N surface-code logical qubits, leading to large overheads for large N. Thus, parallel execution of logical gates for qLDPC codes is still challenging. On the other hand, for high-rate concatenated codes, such as the many-hypercube codes and the concatenated quantum Hamming codes (44), the required ancilla states themselves are encoded with the same high-rate concatenated codes and therefore relatively easy to prepare in a step-by-step manner. This is the advantage of high-rate concatenated codes.

DISCUSSION

We have proposed concatenated high-rate quantum error-detecting codes as a family of high-rate quantum codes for fault-tolerant quantum computing. Because the simple code structure allows for a geometrical interpretation using hypercubes corresponding to logical qubits, we call them many-hypercube codes. The encoding rates are remarkably high, 30 and 20% (64 and 256 logical qubits are encoded into 216 and 1296 physical qubits, respectively) for the code distances of 8 and 16, respectively. We have developed a high-performance decoder and fault-tolerant zero-state encoders dedicated to the codes. Using them, we have achieved high error thresholds: 5.6% for bit-flip errors and 0.9% for a logical CNOT gate in a circuit-level noise model. Further improvements of the decoder and encoders for the many-hypercube codes are challenging but desirable. We have also explained how to implement logical gates necessary for universal quantum computation. More efficient logical-gate implementations for the many-hypercube codes may be possible but are left for future work. Minimizing the number of logical gates and computational depth for given quantum circuits is also an important compilation problem for the many-hypercube codes.

MATERIALS AND METHODS

Elementary gates

In the Z basis {|0⟩, |1⟩}, the matrix representations of elementary gates for universal quantum computation are as follows (3)

Identity gate: I=1001

Pauli gates: X=0110,Z=1001,Y=iXZ=0ii0

Hadamard gate: H=121111

Phase gate: S=100i

Non-Clifford gate: RYπ/4=cos(π/8)sin(π/8)sin(π/8)cos(π/8)

CNOT gate: UCNOT=1001000000000110

Hard-decision decoding of the many-hypercube codes

The hard-decision decoding of, e.g., the level-3 many-hypercube code is done as follows (65). The measurement outcomes of physical qubits in each level-1 block and the corresponding level-1 outcomes are denoted by {xi,j,ki = 1, …,6} and xi,j,k1i=1,,4 , respectively (j,k = 1, …,6). All the four xi,j,k1 are set to F (flag indicating an error) if the parity of the six bits, {xi,j,ki = 1, …,6}, is odd, according to the Z stabilizer. Otherwise, they are set according to the definition of the logical Z operators in Eqs. 1 to 4 as follows: x1,j,k1=x1,j,k+x2,j,k, x2,j,k1=x2,j,k+x3,j,k , x3,j,k1=x4,j,k+x5,j,k , and x4,j,k1=x5,j,k+x6,j,k (mod 2). Next, using the level-1 outcomes in each level-2 block, xi,j,k1j=1,,6 , we obtain the corresponding level-2 outcomes, xi,j,k2j=1,,4, as follows. If there is a single F in the six xi,j,k1, e.g., xi,1,k1, then we can correct this as xi,1,k1=xi,2,k1+xi,3,k1+xi,4,k1+xi,5,k1+xi,6,k1 (mod 2) according to the Z stabilizer. (Note that error-detecting codes can correct a located error.) Then, the four xi,j,k2 are set according to the definition of the logical Z operator, as above. If there is no F and the parity of the six bits is even, then we set the four xi,j,k2 similarly. Otherwise, we set all the four xi,j,k2 to F. Applying this decoding recursively, we lastly obtain the logical-level outcomes. If it is F, then we randomly choose 0 or 1. For error detection used in the proposed encoders, the decoder returns F (indicating detected errors) unless no F is obtained throughout the decoding.

Symbol-MAP decoding of the many-hypercube code

In the symbol-MAP decoding, we calculate marginal probabilities for each logical qubit, which can be done efficiently. For example, the symbol-MAP decoding of the level-3 many-hypercube code is vthe physical-qubit measurement outcomes {xi,j,ki = 1, …,6}, the a posteriori probability for a physical-qubit value x is expressed as

pi,j,kx=peIxxi,j,k1peIx=xi,j,k (28)

where I(A) is the indicator function that returns 1 if A is true and otherwise 0. Then, the marginal a posteriori probability for a level-1 qubit, e.g., Q1,j,k1, is given by

p1,j,k1x=x2=0,1x3=0,1x4=0,1Rj,k1x,x2,x3,x4x1=0,1x2=0,1x3=0,1x4=0,1Rj,k1x1,x2,x3,x4 (29)
Rj,k1x1,x2,x3,x4=x1=0,1x2=0,1x3=0,1x4=0,1x5=0,1x6=0,1i=16pi,j,kxi×Ii=16xi=0 Ix1=x1+x2Ix2=x2+x3Ix3=x4+x5Ix4=x5+x6 (30)

where the summation in the indicator functions is modulo 2. Repeating such calculations recursively, we lastly obtain the marginal a posteriori probabilities for the logical-qubit values xi,j,k3 . If pi,j,k30>0.5 , then we set xi,j,k3 to 0 and otherwise to 1.

Level-by-level minimum distance decoding of the many-hypercube code

The minimum distance decoding is known as one of the highest-performance decoding methods, where we search for a codeword closest to the measurement outcomes in the sense of the Hamming distance. However, there are an exponentially large number of codewords in general; hence, it is usually intractable to find such a minimum-distance codeword. To solve this issue, we keep only minimum-distance codewords and discard larger-distance ones at each level from level 1 to the logical level. Because each level-1 codeword (a bit string corresponding to a level-1 computational-basis state, e.g., 000000 or 111111 for |0000⟩L; see Eq. 5) consists of only six bits, we can easily select minimum-distance codewords and corresponding encoded bit strings (e.g., 0000 for |0000⟩L) in each level-1 block. While there is a single minimum-distance codeword (encoded bit string) when the parity of the six bits is even, there are six minimum-distance codewords (encoded bit strings) when the parity is odd. To construct level-2 codewords using the level-1 minimum-distance encoded bit strings, we first choose five level-1 blocks from the six ones of each level-2 block and then pick one of the minimum-distance encoded bit strings from each of the five level-1 blocks. The encoded bit string of the other level-1 block is automatically determined by the parity-check condition corresponding to the Z stabilizer. In general, the determined encoded bit string is not included in the minimum-distance ones of this block. Therefore, we evaluate the distance of this encoded bit string. Then, we obtain the distance of the level-2 block by summing the distances of the six level-1 blocks. We select the minimum-distance codewords (encoded bit strings) of the level-2 block among all the choices of the five level-1 blocks and their encoded bit strings and keep only them as minimum-distance candidates at level 2. This is our strategy to use the minimum-distance candidates while satisfying the parity-check condition. Doing this selection recursively, we lastly obtain the minimum-distance candidates at the logical level. If we have multiple candidates at the logical level, then we randomly choose one of them. See the Supplementary Materials for more details of this decoding method. For error detection used in the proposed encoders, the decoder returns F unless all the numbers of the candidates at the levels from LD to L are one, where L is the logical level and LD (≤L) is chosen appropriately. The most stringent condition for error detection is given by LD = 1. To increase the acceptance probabilities at error-detection gadgets in the level-4 zero-state encoder, we relax the condition by setting LD as LD = 2.

Simulation of the bit-flip error model

To evaluate the performance of the decoders, we did the following numerical Monte Carlo simulation. We first prepare error-free logical zero states of the many-hypercube code using the encoder in Fig. 1A. Then, independent physical-qubit bit-flip errors are induced with probability pflip per physical qubit. Last, we ideally measure the physical qubits in the Z basis. This quantum circuit includes measurements only at the end. Therefore, we can use the fast sampler of Stim (67) to obtain the physical-qubit measurement outcomes. Then, we decode the outcomes using our homemade Python codes implementing the above-mentioned decoding methods. If all the logical-qubit outcomes are 0, then the decoding succeeds and otherwise fails. We evaluated the decoding error probabilities by sufficiently many trials of this simulation; the numbers of which are provided in table S1.

Simulation of logical CNOT gates

To evaluate the performance of full transversal logical CNOT gates in the circuit-level noise model, we did the numerical Monte Carlo simulation shown in Fig. 10. In this simulation, we first prepare two error-free logical Bell-state blocks using the zero-state encoder in Fig. 1A and error-free physical CNOT and Hadamard gates. Then, we perform faulty full transversal logical CNOT gates implemented by faulty full transversal physical CNOT gates on the first code blocks of the two Bell-state blocks. This is followed by ECT gadgets in which physical operations are faulty according to the noise model. The faulty logical CNOT gates with faulty ECT gadgets are repeated 10 times. After that, the Bell states are disentangled and converted to the logical zero states by error-free physical CNOT and Hadamard gates. Last, the logical zero states are ideally measured in the Z basis and the measurement outcomes are decoded by the proposed minimum-distance decoder. Unlike the above simulation of bit-flip errors, this simulation requires mid-circuit measurements and feed-forward operations based on the measurement outcomes. Therefore, we use the slow Tableau Simulator of Stim (67) for stabilizer quantum-circuit simulation parts. From many trials of this simulation, the numbers of which are provided in table S2, we estimate the error probability and its standard error of 10 sets of full transversal logical CNOT gates, which are denoted by p10 and Δ10, respectively. Then, we evaluate those for one set, which are denoted by p1 and Δ1, as p1=11p10110 and Δ1=Δ10101p101101 . Because each set includes K(L) logical CNOT gates at level L, we lastly evaluate the error probability and its standard error per logical CNOT gate denoted by pCNOT and ΔCNOT as pCNOT=11p11KL and ΔCNOT=Δ1KL1p11KL1.

Fig. 10. Simulation of logical CNOT gates.

Fig. 10.

We first prepare two sets of error-free logical Bell states encoded with the level-L many-hypercube code in four registers. Then, we perform 10 times faulty full transversal logical CNOT gates (implemented by faulty full transversal physical CNOT gates) followed by faulty ECT gadgets on the first and third registers in the circuit-level noise model. Last, we disentangle the logical states by error-free operations and ideally measure all the physical qubits in the Z basis. The measurement outcomes are decoded by the minimum distance decoder. If all the logical outputs are 0, then the 10 sets of full transversal logical CNOT gates succeed and otherwise fail.

Acknowledgments

Parts of numerical simulations were done on the HOKUSAI supercomputer at RIKEN (project IDs Q23614 and RB230022).

Funding: H.G. acknowledges that he received no funding in support of this research.

Author contributions: H.G. conceived the idea, constructed the many-hypercube codes, found its geometrical interpretation, developed the decoders and encoders, established the methods for logical gates with the many-hypercube codes, did all the simulations, and wrote the manuscript.

Competing interests: H.G. is an inventor on a Japanese patent application related to this work filed by RIKEN (no. P2024-031469, filed 1 March 2024). The author declares that he has no other competing interests.

Data and materials availability: All data needed to evaluate the conclusions in the paper are present in the paper and/or the Supplementary Materials.

Supplementary Materials

This PDF file includes:

Supplementary Text

Figs. S1 to S6

Tables S1 to S3

sciadv.adp6388_sm.pdf (471.5KB, pdf)

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Supplementary Materials

Supplementary Text

Figs. S1 to S6

Tables S1 to S3

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