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. Author manuscript; available in PMC: 2026 Jun 21.
Published in final edited form as: J Neural Eng. 2025 Nov 18;22(6):10.1088/1741-2552/ae1876. doi: 10.1088/1741-2552/ae1876

Iris 128x: open-source 128 channel headstages for neural stimulation and recording

Emma K Jacobs 1,3, Manuel Monge 2,3, Ander Switalla 1, Rebecca A Frederick 1, Felix Deku 1,*
PMCID: PMC13283003  NIHMSID: NIHMS2186643  PMID: 41151158

Abstract

Objective.

Investigation into complex neural circuits necessitates interfaces capable of high channel count recording and stimulation. However, existing commercial neural headstages often have limited scalability, restrictive proprietary designs, and constrained bidirectional capabilities, which worsens accessibility challenges and compels researchers to reinvent tools rather than build on a shared foundation.

Approach.

Here, we present two open-source, 128 channel headstages—Iris 128B and Iris 128S—designed for integration with microelectrode arrays. The Iris 128B enables fully bidirectional interfacing, with stimulation or recording across all 128 electrode channels, while the Iris 128S provides recording on 128 channels and stimulation on 16 simultaneous channels, which can be assigned to any 16 of the 32 available stimulation channels. Both designs use Intan Technologies’ RHS and RHD series integrated circuits for amplification, filtering, digitization and stimulation, and are available on GitHub.

Main results.

The headstages were validated through benchtop impedance, noise, and frequency response measurements, as well as acute in vivo recordings in an anesthetized rat. Results demonstrate low noise levels and reliable signal acquisition across all channels.

Significance.

By releasing fully documented printed circuit board designs for headstages, this work aims to take a step towards broader adoption of bidirectional recording and stimulation systems while increasing channel counts. Future iterations will focus on miniaturization and wireless integration to improve usability in chronic and freely moving small animal experiments.

Keywords: bidirectional neural headstage, thin-film microelectrode array, neural interface, open-source, neural recording and microstimulation

1. Introduction

Technologies for neural stimulation and recording have become foundational for both basic neuroscience and clinical therapy. A major milestone in the field has been the idea of closed-loop neuromodulation, in which real-time feedback is used to influence brain activity. As early as 1969, Eberhard Fetz demonstrated the importance of this idea, when he showed that rhesus macaques could learn to voluntarily modulate the firing rates of individual neurons when given visual feedback linked to their neural activity (Fetz 1969). This principle was later extended to neuromuscular control (Yoshida and Horch 1996) and has since blossomed into a variety of clinical applications requiring both neural recording and stimulation (Juzhe et al 2021). These clinical applications include Parkinson’s disease (Rosin et al 2011), chronic pain (Knotkova et al 2021), stroke rehabilitation (Ibáñez et al 2017, Reis and Machado 2025), and neuropsychiatric disorders (Widge 2024). As the ambition of these therapies grows, targeting finer resolution across larger brain areas, so does the demand for neural acquisition systems that can support high channel count recording, while also enabling bidirectional communication (Luan et al 2020, Liu et al 2024, Widge 2024). A first key step towards therapies with complex, closed-loop control is increasing the channel counts available for stimulation and recording in basic neuroscience headstages.

Commercial neural signal acquisition systems typically consist of three core components: (1) a headstage for signal amplification, digitization, and sometimes driving electrical stimulation; (2) a controller, often a field programmable gate array, for data processing that allows for multiplexing of incoming and outgoing signals, and (3) a host computer for system configuration and data analysis (Murphy et al 2019). The headstage, specifically, is a hardware component commonly used to interface between the implanted neural electrodes and the controller. Because of its proximity to the brain and the fact that neural signals are extremely low in amplitude, often in the microvolt range, headstages are needed for amplifying and digitizing these signals, and for modulating neural activity through stimulation drivers. Often, all of these components are contained inside integrated circuits (ICs).

The development of ICs has transformed neuroscience over the last five decades. Early efforts in the 1960s and 70s began exploring the integration of electronics with neural interfaces, and a key milestone came in 1971 with the seminal work of Wise and Angell, who developed one of the first ICs designed for use with microelectrode arrays (MEAs) (Wise and Angell 1971). Over the ensuing decades, advances in microfabrication have enabled increasingly compact and power-efficient designs. These developments ultimately led Harrison and Charles to design a low-power, low-noise amplifier architecture that formed the foundation for Intan Technologies’ RHD and RHS series of chips in the early 2000s (Harrison and Charles 2003). The widespread availability of commercial amplifier and stimulator ICs has played a pivotal role in enabling open-source hardware development and custom laboratory systems without requiring researchers to have specialized IC design expertise.

Intan’s chips, in particular, are commonly used in academic labs to construct flexible, scalable neural recording and bidirectional interface platforms (Shupe et al 2021, Mourão et al 2022, Yasar et al 2024, Newman et al 2025). However, even when stimulation and recording ICs are available, researchers must still address packaging of those ICs, scale them up to their needs, address interconnection challenges, power delivery, and interfacing with additional hardware (Tsai et al 2015, Raducanu et al 2017, Musk 2019, Sahasrabuddhe et al 2021, Zhao et al 2023). Extensive customization is often required to fully address this abundance of challenges, making scalable and standardized solutions rare.

While the commercial landscape offers many sophisticated headstage solutions, researchers can still encounter challenges in finding options that are openly customizable, and readily integrable with high-density MEAs. This integration challenge is particularly salient because while MEA technology has advanced to support thousands of sites, commercial headstages with high channel counts and stimulation capabilities have not kept pace (Luan et al 2020, Juzhe et al 2021, Vatsyayan et al 2023, Zhou et al 2024). To our knowledge, while widely used commercial headstages provide excellent performance, they are optimized for more modest bidirectional channel counts and are typically limited to fewer than 64 electrode channels.

These factors, alongside considerations of cost and the desire for designs that can be freely adapted or built upon, underscore an ongoing opportunity within the neuroscience community for more accessible, open-source, and highly capable interface solutions. This trend is demonstrated by the emergence of projects such as Open Ephys (Siegle et al 2014), the Open Neuro Interface eXtension (ONIX) (Newman et al 2025), and SpikeGadgets, as well as other tools developed by individual labs (Trumpis et al 2017, Mourão et al 2022, Erofeev et al 2023). The current gap between what is technically possible and what is practically available forces researchers to make tradeoffs between recording density, stimulation capability, and experimental flexibility.

In this work, we take a step towards enabling more effective probing of neural dynamics by developing two 128 channel headstages, shown in figure 1, designed for thin-film MEAs capable of both recording and stimulation. The newly developed headstages in this work leverage Intan Technologies’ RHS and RHD series ICs, which integrate amplification, filtering, digitization, and stimulation (RHS 2116—Part #D5716, Intan Technologies; RHD 2164—Part #D8215, Intan Technologies). All printed circuit board (PCB) designs were created in KiCad and are publicly available on GitHub (https://github.com/openic-org/iris-128) to promote open-source collaboration (2025):

  1. Iris 128B—A fully bidirectional headstage integrating eight of Intan Technologies’ RHS2116 stimulator/amplifier ICs, with stimulation and recording on all 128 channels (figures 1(A) and 2(A)).

  2. Iris 128S—A selective stimulation headstage incorporating two RHD2164 amplifier ICs with one RHS2116 chip, allowing recording on all channels and 32 stimulation outputs, with 16 available for near-simultaneous use, via multiplexing. Fewer chips allows for a slightly smaller footprint (figures 1(B) and 2(B)).

Figure 1.

Figure 1.

The newly developed 128 channel Iris headstages and the thin-film array used to validate their function. (A) Iris 128B: fully bidirectional headstage with eight Intan RHS2116 chips for near-simultaneous 128-channel recording and stimulation. (B) Iris 128S: selective bidirectional headstage using two RHD2164 chips for recording and one RHS2116 chip with multiplexers for 16-channel switchable stimulation. (C) Depiction of an acute rodent surgical setup showing the Iris 128B headstage and a thin-film microelectrode array. The alternative Iris 128S headstage (see A and B for renders of both models) would be placed in a comparable location. (D) 128 channel thin-film microelectrode array design. (E) Scanning electron microscope (SEM) image of one electrode site (2000 μm2). SEM images acquired using an Everhart–Thornley detector (ETD) in secondary electron (SE) mode, 20.00 kV accelerating voltage, 6.4 nA current.

Figure 2.

Figure 2.

Architectures of the Iris 128B and Iris 128S open-source headstages and their adapter boards. (A) Iris 128B headstage: a fully bidirectional 128 channel system enabling near-simultaneous recording and stimulation, using eight Intan RHS2116 integrated circuits (ICs). Each IC has 16 electrode inputs and stimulation outputs, multiplexers, analog to digital converters (ADC), and a serial peripheral interface (SPI). It features a SAMTEC SEAM8 160-pin connector for microelectrode array interfacing (compatible with BlackRock systems Cereplex E headstage) and an 80-pin connection to an adapter board. The adapter routes the SPI signals to four RHS Intan controller ports, manages external power for stimulation, and includes troubleshooting pin-outs. (B) Iris 128S headstage: this system provides 128-channel recording with 32-channels selectable for stimulation (up to 16 simultaneously), using Intan RHD2164 and RHS2116 ICs with switches (analog MUX) for multiplexing electrode signals and protecting inputs. The ICs contain similar internal architecture to Iris 128B, but the RHD chips omit the stimulation outputs. A 36-pin connector links to an adapter board containing a microcontroller (MCU) for switch control and a power management unit (PMU) for generating necessary operating voltages from the main controller’s power. Abbreviations in figure: ADC—analog to digital converter, SPI—serial peripheral interface, MCU—microcontroller, MUX—multiplexer, POS—position, stim—stimulation.

Both designs are open-source, with all design files, schematics, layouts, bills of materials, characterization data, and user documentation available on GitHub (2025) and in an Open Science Framework repository (2025). For the sole purpose of benchtop validation of the headstages, we fabricated a 128 channel polyimide thin-film electrode using methodologies routinely used in the Deku lab. The .dxf and .gds design files for the planar MEA are also included in the repository. While we do not demonstrate any closed-loop control or near-simultaneous recording and stimulation in this work, the availability of a bidirectional, higher channel count headstages makes this more feasible for the neuroscience community. By offering an openly available, adaptable headstage, we aim to reduce obstacles in neuroscience research and increase adoption of higher density bidirectional systems.

2. Methods

2.1. Hardware and headstage PCB design

The implementation of the newly-developed Iris headstages is depicted in figure 1(C), which illustrates the location of the thin-film electrodes, headstage, cabling, and adapter boards. Both headstages communicate with the controller via serial peripheral interface (SPI). SPI typically has four communication lines: chip select (CS), serial clock (SCLK), serial data input, and serial data output. RHS2116 chips require a minimum of ±3.3 V up to ±7 V for stimulation, 3.3 V for digital logic and analog power, and consume ~50 mW when recording on all 16 channels (Intan Tech., RHS2000 Datasheet). RHD2164 chips require a single supply voltage of 3.3 V for digital logic and analog power, do not support stimulation, and consume ~75 mW during recording on all 64 channels (Intan Tech., RHD2000 Datasheet). To decrease sensitivity to noise, we implemented low-voltage differential signaling (LVDS) for the SPI on both headstages. Unlike single-ended signaling, LVDS transmits data at low-voltage levels via paired differential signals, reducing the effects of electromagnetic interference (EMI). To additionally reduce EMI, we used coaxial, shielded cables between the headstages and controllers.

The PCBs of both systems share the same layer stack and specifications (see table 1). To optimize size and cost while maintaining performance, we employed an 8-layer design with a minimum trace width of 3 mil and minimum trace spacing of 3 mil, micro-vias with hole sizes and diameters of 6 mil and 12 mil, and low-cost substrates. PCB routing focused on shielding traces connecting the electrode array to the recording/stimulation ICs. We used the following routing strategy:

  • Layer 1 (top) and Layer 8 (bottom) were used for minimal local routing and ground planes.

  • Layer 2 handled power supplies and some local routing, with an additional ground plane for sensitive routing.

  • Layer 3 served as a ground plane to shield signal traces from power supplies and other switching signals.

  • Layers 4, 5, and 6 were dedicated to analog routing between the electrode pins and recording/stimulation ICs.

  • Layer 7 contained the ground plane and SPI routing from the ICs to the output connector, with SPI traces shielded in Layers 6, 7, and, where possible, Layer 8.

  • The reference electrode trace was routed in Layer 6 and shielded by ground planes in Layers 5, 6, and 7.

Table 1.

Headstage PCB specifications.

PCB specification Iris 128x
Min. Trace width/space 3 mil/3 mil
#Layers 8
Microvia (hole/diameter) 6 mil/12 mil
Thru-Hole Via (hole/diameter) 8 mil/14 mil
Thickness 1 mm
Surface finish ENIG
Copper weight 1 oz

2.1.1. Iris 128B

The Iris 128B design as shown in figure 2(A) integrates eight RHS2116 ICs, enabling recording and stimulation across 128 channels. To interface with the thin-film array, we used a connector (Samtec SEAF8-20-1-S-08-2-RA) compatible with the BlackRock Microsystems CerePlex E Headstage to allow for flexibility in recording system use (Intan Technologies, Los Angeles, CA, USA; Samtec Inc, New Albany, NY, USA). Typically, each port on the Intan RHS controller interfaces with 32 electrodes through SPI. Communication with the RHS controller is routed through an 80-pin Molex connector, which accommodates SPI through LVDS and power lines while minimizing crosstalk. To accommodate multiple chips while minimizing routing complexity, we shared SCLK and CS lines across all ICs. To allow for communication with the Intan RHS controller, the Molex 80-pin cable is routed to an adapter board (figure 2(A)). The board includes pinouts for ground, reference, and SPI lines for troubleshooting. Power is supplied to the ICs by an external HP E3631A DC power supply (HP Inc., Palo Alto, CA, USA) to avoid overloading the controller’s power rails, and to accommodate power requirements to allow stimulating with all 128 electrode sites.

2.1.2. Iris 128S

The Iris 128S (design shown in figure 2(B)) includes two RHD2164 amplifier chips, one RHS2116 recording/stimulation chip, and eight octal switches. The same connector as the Iris 128B was used to interface Iris 128S with the thin-film array. Iris 128S supports recording from all 128 channels. For stimulation, the headstage features 32 designated electrodes, and the user can select any 16 of these 32 electrodes to be active for near-simultaneous stimulation. This design maintains compatibility with RHD and RHS controllers, allowing integration with existing Intan-based acquisition systems.

The switches allow for flexible routing of the 32 electrode pins: while all 32 can be connected to an RHD2164 recording chip, up to 16 pins can be individually rerouted to an RHS2116 chip for stimulation. The remaining pins stay connected to the RHD2164 chip for recording. Since the RHS2116 has a voltage compliance of ±7 V and the input voltage range of the RHD2164 is +3.3 V, we used additional switches to protect the RHD2164 inputs from voltages outside its input range, resulting in the 2-switch per pin circuit shown in figure 2(B). Furthermore, the input/output capacitance of the switches add parasitic capacitances to the signal path which could affect the performance of the neural amplifiers. Given these constraints, we selected the ADGS5414 because of its low parasitic switch capacitances (tens of pF) while withstanding voltages of at least ±9 V.

The Iris 128S in this configuration communicates with both the RHD and RHS controllers. Communication is routed through a 36-pin Omnetics connector, which accommodates SPI through LVDS and power lines for the recording and stimulation ICs, and programming and power lines for the switches. The 36-pin cable is then routed to an adapter board (figure 2(B)). The board includes a microcontroller unit (MCU) to program the state of the switches and a power management unit (PMU) to generate the required voltages for the MCU (+3 V) and the switches (+3 V, ±9 V) from the power signal (+3.3 V) of the RHD Controller. Thus, once the MCU is programmed, this adapter board only needs to be connected to the Intan controllers.

2.2. Thin-film MEA design and fabrication as a test platform for headstages

Two types of MEAs were used to evaluate headstage performance. Planar MEAs, with 2000 μm2 platinum (Pt) electrode sites supported in vitro testing. Penetrating MEAs, with 200 μm2 iridium oxide–coated (EIROF) sites supported in vivo testing to place electrodes closer to neurons and enhance the likelihood of single-unit recordings (McNaughton et al 1983, Khodagholy et al 2015).

2.2.1. Planar MEAs

A 128-channel polyimide-based MEA was designed for the functional assessment of the 128-channel headstages. The electrode sites were arranged in a grid pattern and each site had an approximate geometric surface area (GSA) of 2000 μm2, as shown in figure 1(d). The GSA was selected to be representative of commonly used sizes in thin-film MEAs. Arrays currently in clinical trials (Precision Neuroscience, Hettick et al 2024), employ 50 μm diameter platinum electrodes, and this dimension has also been widely adopted for material characterization studies (Fan et al 2021, SzKlarz et al 2024).

Fabrication begins with a 5 μm thick polyimide layer (PI2611, HD Microsystems) spin-coated onto the substrate and cured at 350 °C in a nitrogen ambient oven. To facilitate metallization patterning, lift-off photolithography was employed, with a bilayer resist stack consisting of LOR5C resist (Kayaku Advanced Materials, Inc.) and AZ1512 photoresist (MicroChemicals GmbH) to facilitate undercut formation. A descum step was performed in oxygen plasma using reactive ion etching (RIE, Trion) system to remove residual resist. Metallization consisted of a three-layer coating of Ti/Pt/Ti (30 nm/200 nm/30 nm) by electron beam deposition (ATC-E HV Series Electron Beam Evaporation). This process follows a similar three-layer metallization stack previously described by Deku et al (2018). After metal deposition, lift-off was achieved by immersion in Remover PG (Kayaku Advanced Materials, Inc). A second polyimide layer (PI2611, HD Microsystems) was spin-coated and cured at 350 °C in a nitrogen ambient oven. A 100 nm aluminum layer was used as a hardmask to expose the bond pads and electrode sites. The surrounding polyimide was then etched away via RIE using oxygen plasma (Corial ICP-RIE 210IL, Plasma-Therm, St. Petersburg, Florida USA). The top titanium layer was etched in an SF6 plasma without breaking vacuum. After etching, the aluminum hardmask was removed using aluminum etchant. Figures 1(D), (E) show the details of the array geometry, with the finished thin-film array after bonding to the connector shown in section 3.2.

2.2.2. Penetrating MEAs

For in vivo investigation, separate 128 channel penetrating electrodes were fabricated following the methods described above, with the exception of the electrode site layout and electrode material. The penetrating device consists of four, 3 mm long shanks (the part of the device that penetrates brain tissue), with 32 electrode sites and 40 μm center-to-center spacing aligned linearly along the length of each shank (figure 3(C)). The GSA of each electrode site is approximately 200 μm2. To reduce the electrode impedance for neural recording, iridium oxide films were electrodeposited on each platinum electrode site following methods reported previously (Rüdiger Meyer and Cogan et al 2001).

Figure 3.

Figure 3.

Schematic of the various measurements performed, showing the setup for each type of measurement. (A, B) Setup for impedance and noise measurements. A thin-film array in a three-electrode configuration, with either a potentiostat or the Intan controller was used to demonstrate the performance of impedance measurements across a range of frequency values. Only the setup in B is used for the noise measurements. (C) In vivo measurements were performed with a three-electrode configuration, with platinum bone screws in contact with the CSF as the reference and ground. The working electrodes were iridium oxide coated sites on a penetrating array. (D) Frequency response measurements were recorded without a thin-film device. A waveform generator was connected to the bond pads on the headstage, and the reference and ground pads were shorted. (E, F) Voltage transients were recorded across the stimulating electrode using the DC amplifier on the Intan chips, in a two-electrode configuration. The same setup was used with the Plexon stimulator.

2.2.3. Connectorization of MEAs

After electrode fabrication, both types of arrays were released from the Si carrier wafer by gently immersing the wafer in deionized water, after which the arrays were carefully lifted off with tweezers. Next, a 160-channel Samtec SEARAY connector (SEAF8–20-1-S-08–2-RA; Samtec, New Albany, IN, USA) was attached to each MEA using low-temperature indium solder paste and reflow (Indium Alloy 290, Indium Corporation), then encapsulated in medical-grade epoxy (Loctite EA M-121HP). Alignment of the connector and the bondpads on the MEA was achieved using a custom alignment fixture to place the bond pads in a known location relative to the connector.

Micro-computed tomography (micro-CT) imaging was performed using a Zeiss Xradia 620 Versa system (Carl Zeiss AG, Oberkochen, Germany) to validate the alignment of the SEAF connector with the thin-film (figure 4). Scans were conducted using a source energy of 160 kV, power setting of 25 W, and an HE6 filter. Two volumes of interest (VOIs) were imaged: a larger VOI (figure 4(B), panels 1–4) using the 0.4× objective at a voxel resolution of 18.5 μm with a 3 s exposure time (scan duration approximately 2.5 h), and a smaller VOI (figure 4(C)) using the 4× objective at a higher voxel resolution of 2.9732 μm with a 12 s exposure time (scan duration approximately 6.5 h). Sequential slices from the micro-CT scan (top to bottom) show the interface between the thin-film and connector, with indium solder balls visible at the connector interface (figure 4(B), panels 1–4). A magnified view of a subset of pads highlights the successful mechanical connection between the two components (figure 4(C)). Electrode site imaging (figure 1(E)) was performed using a Helios liquid metal ion source focused ion beam scanning electron microscope operating at an accelerating voltage of 4 kV under high-vacuum conditions (Thermo Fisher Scientific, Waltham, MA, USA). Samples were prepared by mounting onto aluminum stubs using carbon tape and coated with a few nanometers of carbon to minimize charging. Secondary electron (SE) images were acquired to visualize electrode site surface morphology (figure 1(e)).

Figure 4.

Figure 4.

Connectorization of a 128-channel thin-film MEA and micro-CT validation of indium solder bonding to a 160-pin Samtec connector. (A) Fully connectorized 128-channel thin-film microelectrode array (MEA), showing the 160 pin SAMTEC (SEAF8–20-1-S-08–2-RA) connector attached to the polyimide-based array via a low-temp indium solder reflow process and encapsulated in epoxy. (B) Diagram of the 160-pin Samtec connector placement onto the thin-film MEA, with illustrative microcomputed tomography (micro-CT) cross-sections of the interface. These sections detail the progression from the MEA’s Pt bond pads (1), through the indium solder balls and connector pins (2, 3), to the connector pins alone (4), confirming successful bonding. (C) A 3D micro-CT reconstruction visualizing a magnified portion of the bond pads and their connection. All micro-CT imaging (Zeiss Xradia 620 Versa) utilized a 160 kV source, 25 W power, and an HE6 filter, with voxel resolutions of 18.5 μm (B, overview) and 2.97 μm (C, detailed view).

2.3. Benchtop electrical testing

Prior to in vivo experimentation, benchtop characterization of each headstage was performed to validate electrical performance. This was done by measuring amplifier frequency response, acquiescent noise levels, comparing impedance measurements between Intan hardware and the Gamry potentiostat, and measuring voltage transient (VT) response. The phosphate-buffered saline (PBS) solution used for benchtop measurements was prepared by dissolving 22 mM sodium dihydrogen phosphate monohydrate (NaH2PO4·H2O), 81.05 mM disodium hydrogen phosphate heptahydrate (Na2HPO4·7H2O), and 125.94 mM sodium chloride (NaCl) in deionized water (Cogan 2008).

2.3.1. Measurements without MEA: frequency response

To evaluate the AC high-gain amplifier response of the headstages (section 3.3.1), we performed a frequency response analysis using a 2-electrode configuration. These measurements were conducted before connecting any thin-film array to the headstage, as shown in figure 3(d), in a dry environment (i.e. without immersing in PBS). We tested one channel on Iris 128B, one recording-only channel on Iris 128S, and one stim-capable channel (with additional routing through the 8-channel MUX) on Iris 128S. For both the Iris 128S measurements, the RHD controller was used to record the response. For signal input, a platinum wire was soldered to a single channel on the headstage’s 160 pin SEAF connector. A waveform generator (SDG 1032X; Siglent Technologies, Shenzhen, China) was used to deliver a 2 mV peak-to-peak (mVpp) sine wave at discrete frequencies ranging from 0.5 Hz to 10 kHz, with six points per decade. This signal was applied between the platinum wire and the shorted ground and reference channels on the headstage, which were also connected to a platinum wire. The corresponding signal recorded at the headstage was acquired using Intan RHS and RHD controllers with a sampling rate of 30 kSa s−1, a wide band filter (no software filtering added), and digital signal processing (DSP) disabled.

For each tested frequency, we recorded data to a separate file. The output amplitude at each input signal frequency was then calculated by averaging the peak-to-peak values across 10 signal periods. Finally, this amplitude was normalized to the maximum amplitude observed across all tested frequencies.

2.3.2. Measurements with MEA: impedance

To characterize the recording system in combination with microelectrodes, a 3-electrode configuration was used for impedance measurements. The reference electrode in the Intan RHD and RHS chips is isolated through a high impedance buffer. Headstages were connected to the planar thin-film fabricated arrays (described in 2.2.1), and two platinum wires with a GSA of ~0.518 cm2 (roughly 25 000 times larger than the working electrode) were separately connected to the ground channel pin and reference channel pin on the headstage (figures 3(A) and (B)). Measurements were obtained by submerging the microelectrodes in PBS within a Faraday cage.

We tested electrode impedance with 5 different hardware configurations. (1) Gamry potentiostat, 124 connected MEA channels, with a Ag|AgCl reference electrode and platinum wire counter. (2) Intan RHS controller with Iris 128B headstage, 124 channels, with a platinum counter and reference electrode. (3) Intan RHD controller with Iris 128S headstage, 124 channels (routed through the RHD chips), with the same reference and ground configuration as 2. (4) Intan RHS controller with Iris 128S headstage, 16 channels (routed through RHS chips), with the same reference and ground configuration as 2. (5) Intan RHS controller with commercial Intan headstage (item #M4016, Intan technologies, Los Angeles, CA, USA), 8 channels, with the same reference and ground configuration as 2.

Channels with impedance values exceeding 600 kΩ at 1 kHz when measured with the Gamry potentiostat were defined as ‘unconnected’ and excluded from data analysis, based on previously reported work that used similarly sized and fabricated electrodes (Fan et al 2021). The 600 kΩ threshold is just above the higher end of the variability reported in this prior work. Four electrode sites were determined to be disconnected per the impedance threshold and excluded from further analysis.

Impedance magnitude from 50 Hz to 5 kHz was measured using an Intan controller (RHD or RHS) for all connected electrode sites (n = 124) on both Iris 128S and Iris 128B headstages and (n = 8) on the commercial 16 channel Intan RHS headstage, and compared to the impedance spectra (10 Hz to 10 kHz) measured using a Gamry Reference 600 potentiostat (Gamry instruments, Warminster, PA, USA; section 3.3.3).

2.3.3. Measurements with MEA: noise

For acquiescent noise measurements (table 2), continuous voltage data was recorded from each channel (n = 124) for 20 s for each headstage (128B and 128S). Noise measurements used the same 3-electrode setup as impedance measurements (planar MEA, platinum wire counter, platinum wire reference). Data preprocessing of noise measurements, consisting of voltage versus time recordings from electrode sites, involved removing unconnected channels (|Z| > 600 kΩ at 1 kHz; n = 4). The system was allowed to reach steady state before performing measurements. No filters were applied; therefore, the bandwidth of the measurement is 0.5 to the Nyquist frequency, 15 kHz.

Table 2.

Comparison of Iris 128x headstages to commercially available designs.

Metric Iris 128B Iris 128S Intan 32ch Kontex 64ch TDT 64ch switching
[this work] [M4032] [X3SR64] [ZC64SW16]
Noise (uVrms) 3.09b 3.33b 2.4a 2.4a —
Weight (g) 9.61 4.47 1.42 — 2
Volume (mm3) 1188 720 576 891 3503
Electrode # 128 128 32 64 64
Stim/record 128/128 32/128 32/32 64/64 16/64
a

Intan IC AC high-gain amplifier input referred noise.

b

Measurement included AC high-gain amplifier input referred noise.

2.3.4. Measurements with MEA: VTs

VTs were recorded in response to constant-current, biphasic, cathodic-first waveforms to confirm the stimulation functionality of each headstage. The intention of these recordings was to demonstrate the ability of the headstages to generate and apply a stimulus that is comparable to commercially available systems. VT measurements were collected in a two-electrode configuration in PBS, with a ~0.048 cm2 (roughly 2500 times larger than the working electrode) platinum wire used as the reference/counter electrode. VT measurements were collected on connected stimulation-capable channels using the DC amplifier on the Intan RHS controller with DSP disabled (section 3.3.4). Voltage responses were recorded during trains of stimulation pulses; however, only the response to the first pulse was analyzed and presented. For the Iris 128B, Iris 128S, and the commercial headstage, sampled data points represent the mean across n = 8 electrodes for each headstage, and variability is shown as the standard error of the mean (section 3.3.4). The sampling rate used for these measurements was 30 kSa s−1, and the charge recovery switch enabled. This grounds the electrode at the completion of each pulse.

The applied stimulation consisted of a 2 nC/ph biphasic, square, cathodic-first pulse (4 μA current, 500 μs pulse width, 500 μs interphase delay, 100 pulses per second). This waveform was chosen based on reported charge injection limits for platinum electrodes, as well as the sampling rate limitations of the recording system. The applied charge density, 0.1 mC cm−2, corresponded to ~70% of the maximum (0.15–2.5 mC cm−2) charge injection capacity reported for platinum electrodes (Ivanovskaya et al 2018, Pfau et al 2019). Pulse widths and interphase delays were set to ensure >5× oversampling at the 33 μs system sampling interval. Because this rate is relatively coarse for resolving the rapid polarization dynamics during stimulation, a subset of measurements was repeated using the PlexStim Electrical Stimulator system (Plexon Inc., Dallas, TX, USA), which offers a higher sampling resolution of ~3.2 μs (312.5 kS s−1). VTs were recorded in the discharge mode.

Additional recordings (section 3.3.4) provided finer temporal detail of the transient response, enabling more accurate characterization of capacitive polarization and peak electrode potentials, and thereby increasing confidence in the overall measurements. Following each stimulation pulse, the PlexStim systems activate a discharge phase designed to dissipate residual charge at the electrode–electrolyte interface. For this study, the same configuration as the headstages was used, with a two-electrode configuration. The platinum reference/counter electrode had a GSA of ~0.518 cm2 (roughly 25 000 times the size of the working electrode). To compare the stimulation through the Iris headstage and the PlexStim, two current amplitudes: 2 μA and 6 μA (500 μs pulse width, 500 μs interphase delay, 100 pulses per second) were selected to illustrate how electrode voltage responses scale with increasing current, with one value well within and the other approaching/exceeding the ‘safe’ charge-injection range. In addition, a single electrode trace was recorded on the Iris 128B and compared with the Plexon stimulator. A single representative channel was selected for this comparison to preserve individual waveform features, rather than present an averaged response.

2.4. In vivo measurements

All procedures were approved by the Institutional Animal Care and Use Committee at the University of Oregon (IPROTO202200000267).

To assess headstage performance in a biological setting, acute neural recording was conducted in n = 1 anesthetized adult female Long–Evans rat. Anesthesia was maintained with isoflurane (1%–3% inhalation), and local anesthetic (0.5% bupivacaine, 0.16 cc) was injected subcutaneously at the incision site. The head was secured in a stereotaxic frame using ear bars, and two craniotomies were performed to create 2 × 3 mm openings: (Site 1) 1.1–3.1 mm medial–lateral (M–L) and −1.0 to −4.0 mm anterior–posterior (A–P), (Site 2) −1.0 to −3.5 mm M–L and −1.0 to −4.0 mm A–P, where all coordinates are with respect to bregma, exposing the motor and sensory cortex (M1, M2, S1HL) for electrode placement (Paxinos and Watson 2007). Two stainless steel bone screws in contact with cerebrospinal fluid (CSF) served as connection points for separate platinum wire ground and reference electrodes connected to the headstage. Local field potentials (LFPs) and neural spiking were recorded using the Iris 128B (section 3.3.5), followed by recordings with Iris 128S. Following data collection, the rat was euthanized with an overdose of Euthasol (sodium pentobarbital, 200 mg kg−1).

A high-pass filter (0.5 Hz) was applied to remove DC offset, and a 60 Hz notch filter (59.5–60.5 Hz) was used to reduce power line interference. Power spectral density (PSD) was computed using MATLAB’s pwelch function. The PSD was calculated for each signal in the range of 0.5–100 Hz and expressed in decibels (dB). As shown in the results section 3.3.5, the PSD curves for Iris 128B (dark green) and Iris 128S (light green) were plotted alongside the baseline spectrum (dashed black), derived from noise measurements in PBS. Single unit spiking activity was analyzed using Plexon’s Offline Sorter software (Plexon, Dallas, TX, USA). A high pass 250 Hz Butterworth filter was applied, and single units were identified manually based on 2D principal component analysis and voltage thresholding (−70 μV). Representative single unit activity recorded from Iris 128B can be seen in section 3.3.5, along with the corresponding filtered continuous recording. Signal to noise ratio (SNR) was calculated as

SNR=SignalRMSNoise

where Signal and RMSNoise are the mean peak-to-peak amplitude and the root-mean-squared (RMS) noise, respectively (Pancrazio and Cogan 2019). Peak-to-peak amplitude was individually measured for all detected single unit waveforms while RMS noise was measured from 8 s filtered time-series data containing no detected units.

3. Results

3.1. Headstage design

The Iris 128B and Iris 128S headstages were fabricated according to the designs specified in section 2.1. The Iris 128B integrates only RHS2116 chips and supports both recording and stimulation on all 128 channels (figure 2(A)). It has a recorded noise level of 3.09 μVrms, weighs 9.61 g, and has a volume of 1188 mm3 (table 2). The Iris 128S incorporates a combination of RHS2116 and RHD2164 chips, enabling recording on 128 channels and selective stimulation on 32 channels, with up to 16 channels available for stimulation at once (figure 2(B)). This model exhibits a noise level of 3.33 μVrms, a lighter weight of 4.47 g, and a smaller volume of 720 mm3 (table 2).

3.2. MEA fabrication and connectorization

Polyimide based 128-channel MEAs were successfully fabricated and connectorized for use with the Iris 128x headstages. The arrays featured 2000 μm2 platinum electrode sites arranged in a grid layout as seen in figure 1(d). Each array was then connectorized (figure 4). Alignment between the SEARAY connector and the array bond pads was verified via micro-CT imaging using a Zeiss Xradia 620 Versa system. Imaging confirmed proper alignment at both low and high magnifications, with voxel resolutions of 18.5 μm and 2.97 μm, respectively (figures 4(b) and (C)). Scanning electron microscopy of the electrode sites was performed to validate surface morphology of the Pt electrode sites (figure 1(e)). As discussed in methods section 2.2, an array with 4 penetrating shanks was also fabricated and connectorized similarly for in vivo use. Based on the expected 1 kHz impedance values, 96% of electrodes used in the benchtop electrical testing were connected. For the in vivo penetrating array, 90% of electrodes were considered connected.

3.3. Headstage benchtop electrical performance

3.3.1. Frequency response (without MEA)

Frequency response describes how consistently a system amplifies signals across different frequencies. Measuring it informs us whether the relevant signals are recorded. The 3 dB cutoff marks the frequencies where the amplifier’s gain drops, indicating the effective bandwidth limits of the system. The frequency response of the AC high-gain amplifiers on Iris 128B and Iris 128S headstages (figure 5, panels A–C) is similar to the expected characteristics from the Intan RHD and RHS2000 amplifier characteristics, showing relatively flat gain across most of the passband with attenuation near the low (<10 Hz) and high (~10 kHz) frequency extremes (Intan Technologies 2017). Minor deviations in the frequency response between headstages (e.g. Iris 128S with and without switching components) are within the expected variations of the ICs in the signal path (RHD2164, RHS2116, and ADGS5414). For Iris 128B, the 3 dB cutoffs are below 1 Hz (−2.74 dB) and above 5000 Hz (−0.42 dB). For Iris 128S, without a switch, the cutoff is below 0.5 Hz (−0.27 dB) and above 5000 Hz (−0.92 dB). With the switch it is below 0.8 Hz (−1.51 dB) and above 5000 Hz (−0.76 dB).

Figure 5.

Figure 5.

Frequency response of Iris 128 headstages demonstrating effects of analog multiplexer switching. (A)–(C) Frequency response collected using AC high-gain amplifier on RHS chips from 0.5 Hz to 10 kHz for one channel on each headstage. Signal was generated using a SDG 1032X waveform generator. (A) Amplitude response recorded by Iris 128B. (B) Amplitude response recorded by a channel that is not routed through the analog multiplexer switch on Iris 128S (recording only). (C) Amplitude response by a channel that is routed through the analog multiplexer switch on Iris 128S (capable of stimulation).

3.3.2. Baseline noise (with MEA)

To determine the level of quiescent noise being picked up or generated by the headstages, we conducted benchtop recordings in PBS using the planar MEA. RMS noise across all channels (n = 124, 4 removed due to impedance above 600 kΩ) remained well below expected physiological amplitudes and noise floor <10–20 μV (Marblestone* et al 2013). For Iris 128B Vrms was 3.09 μV, and for Iris 128S it was 3.33 μV (table 2).

3.3.3. Electrode impedance (with MEA)

The impedance of electrodes is critical for recording quality (Lewis et al 2024). Intan RHS and RHD chips generate a small AC current to measure electrode impedance by observing the amplified voltage response and calculating the ratio of peak voltage to peak current.

To validate this functionality and ensure that Iris headstages do not add appreciable resistance or capacitance to the measured values, electrode impedance was first measured across a frequency spectrum with the MEA connected to a Gamry Reference 600 potentiostat (figures 6) and a similar spectrum was obtained using an Intan RHS or RHD controller with the Iris 128B and Iris 128S headstages connected to the MEA. Average impedance for the 2000 μm2 platinum electrodes at 1 kHz was 296 kΩ (SEM = 7.24 kΩ) (n = 124) using the potentiostat, 286 kΩ (SEM = 6.87 kΩ) using Iris 128B, and 261 kΩ (SEM = 6.82 kΩ) using Iris 128S through the RHD chips (n = 124), 310 kΩ (SEM = 2.4 kΩ) using Iris 128S through the RHS chips (n = 16), and 246 kΩ (SEM = 24 kΩ) using the commercial headstage (n = 8).

Figure 6.

Figure 6.

Validation of headstage impedance measurement unit against the Gamry potentiostat for the 2000 μm2 Pt electrodes. Markers represent the average value with shading representing the standard mean error across the available sample size for each type of measurement system. Iris128B RHS, Iris128S RHD, and Gamry Potentiostat (Reference 600): n = 124 electrodes. Iris128S RHS: n = 16 electrodes. Commercial Intan RHS headstage: n = 8 electrodes.

3.3.4. VT measurements (with MEA)

VTs were recorded for n = 8 channels on the Iris 128B, the Iris 128S, and commercial 16 channel Intan RHS headstage, using the DC amplifier in the RHS2116 to confirm stimulation capability. The purpose of these VTs was to show that the headstages are capable of generating a stimulus on each of the available channels (figure 7). The full range of stimulation capabilities for the Intan RHS chips is provided in table 3. The data reported in figure 7 represent the average values ± the standard mean error for each electrode site. The average ± standard mean error for Vdrive (n = 8 electrodes) was −0.75 ± 0.05 V, −0.76 ± 0.09 V, and −0.76 ± 0.04 V, for Iris128S, the commercial headstage, and Iris128B, respectively. We have reported this as a metric to demonstrate stimulation. Charge density per phase can be estimated to be 0.1 mC cm−2. We would like to note that electrode properties (i.e. roughness, geometry) were not characterized, as this graph focuses on verifying the stimulation circuitry is comparable to that of existing headstages. VTs recorded with Iris 128B (figure 8(A)) and PlexStim (figure 8(B)) were closely aligned at both currents, confirming accurate stimulation delivery by Iris 128B despite its lower temporal resolution.

Figure 7.

Figure 7.

Voltage transient response recorded with DC amplifiers during current-controlled biphasic stimulation at 2 nC ph−1 (4 μA current, 500 μs pulse width, cathodic first) at a frequency of 100 pulses per second. Platinum electrodes with geometric surface area of 2000 μm2 were used for this experiment. The estimated current waveform applied is shown, with the respective voltages recorded across electrodes from each headstage. The transient shown here represents the response to the first stimulation pulse. The number of electrodes tested in each headstage configuration is eight and shaded portion is the standard mean error.

Table 3.

RHS chip stimulation limits.

Supply voltagea Supply current Current step size Sampling ratesb
±3.3–10.7 V 2.55–255 uA 10 nA—10 uA 1–30 kS s−1
a

Total for positive and negative cannot exceed 14 V.

b

Using Intan controllers.

Figure 8.

Figure 8.

Voltage transients representing a single stimulation pulse and electrode recorded with DC amplifiers (A) or with the PlexStim system (B) during current-controlled biphasic stimulation at 1 nC ph−1 (2 μA current, 500 μs pulse width, cathodic first) and at 3 nC ph−1 (6 μA current, 500 μs pulse width, cathodic first), at a frequency of 100 pulses per second and geometric surface area of 2000 μm2. (A) The voltage transients recorded on Iris 128B (sampling rate of 30 kSa s−1). (B) The voltage transients recorded using a Plexon stimulator and oscilloscope (sampling rate of 312.5 kSa s−1)

3.3.5. In vivo neural recording

To evaluate the performance of both headstages in a biological setting, acute recordings were conducted in an anesthetized adult female Long–Evans rat. LFPs were recorded from the motor and somato-sensory cortex, using the Iris 128B and subsequently the Iris 128S. Representative PSD plots derived from each headstage are shown in figure 9(A). Both Iris 128B (dark green) and Iris 128S (light green) captured characteristic LFP signatures across the 0.5–100 Hz range. The baseline PSD from in vitro noise measurements in PBS is shown for comparison (dashed black). Raw time-domain LFP signals from both headstages are shown in figure 9(B).

Figure 9.

Figure 9.

Local field potentials (LFP) and single unit spiking data recorded using custom headstages. (A) Power spectral density of LFPs recorded from a single cortical electrode during surgery using both Iris 128B (dark green) and Iris 128S (light green). Baseline noise from phosphate buffered saline is shown for comparison (dashed black). (B) Raw timeseries traces from both headstages recorded from the same electrode site. (C) Representative single unit spike waveforms from a five-minute recording, a high pass Butterworth 250 Hz filter is applied before manual spike sorting. (D) Corresponding 60 s snapshot of high pass filtered (250 Hz), timeseries.

To assess single unit performance, spike detection and manual sorting were performed on Iris 128B recordings. A representative sorted unit is shown in figure 9(C), where spike waveforms (thin lines) and the averaged waveform (bold dark green) are overlaid. Noise traces are plotted in gray. A one-minute segment of the filtered (high pass, butterworth 250 Hz) timeseries data is shown in figure 9(d). The recorded amplitudes peak-to-peak ranged from 208 to 546 μV, with an average spike amplitude of 379 ± 94.3 μV. The SNR was 20.15 ± 0.68.

4. Discussion

There is growing momentum within the neuroscience community to create more accessible, adaptable, and collaborative tools for neural interfacing. Open-source platforms like Open Ephys and OpenBCI are helping democratize access by lowering both technical and financial barriers. These initiatives promote not only the sharing of hardware designs and software code, but also a culture of mentorship and community problem-solving. Additionally, academic institutions and funding agencies are increasingly recognizing the value of open-source tools. For example, the Allen Institute, along with the NIH’s BRAIN Initiative and SPARC program, actively emphasize open-source data and tool sharing as central pillars of their mission to promote transparency, reproducibility, and widespread accessibility in neuroscience research. Despite these promising developments, we believe significant opportunities remain to broaden access to neurotechnology. This is particularly crucial in areas where its availability is often constrained by factors such as high costs, proprietary restrictions, and limited distribution channels (Tennant et al 2016, Aderinto et al 2023). This work aims to contribute to advancing this goal.

Neuroscience research has been significantly advanced since the late 20th century by robust, plug-and-play commercial systems for neural recording and stimulation. Companies such as Blackrock Microsystems, Intan Technologies, IRIS Biomedical, and Tucker-Davis Technologies (TDT) have driven the adoption of electrophysiological methods by providing these platforms, often bundled with quality software, streamlined hardware, and reliable support. Their continued innovations—improving packaging, reducing size, and minimizing noise—allow labs to study neural dynamics with ever-greater precision.

While these platforms offer valuable options for bidirectional interfacing, they are generally limited in their ability to record and stimulate beyond 64 channels near-simultaneously. Various academic research groups have explored custom designs, often leveraging commercial chipsets, or custom ICs to expand channel capacity, reduce size, etc. (Morizio et al 2005, Trumpis et al 2017, Zhou et al 2017, 2024, Mourão et al 2022, Zhao et al 2023). But, these designs often require extensive customization, involve tradeoffs in stimulation capabilities, or require specialized knowledge to implement, limiting the practicality of their implementation.

The significance of our work lies in its ability to scale up channel density while maintaining the same capabilities as prior headstages (table 2) and take a step in the movement towards open-source work. We are making available all design and fabrication files (including schematic, layout, Gerber, and bill of materials) as well as characterization data and user documentation. Both design files and software tools used are open source.

In the present work, we designed, fabricated and tested two headstages: Iris 128B and Iris 128S. The Iris 128B headstage use eight Intan RHS2116 ICs to allow near-simultaneous stimulation and recording on all channels. We also developed a more compact version, Iris 128S, which uses only two RHD2164 and one RHS2116 ICs at the cost of reduced stimulation flexibility. Iris 128S includes switches between the electrodes and the recording/stimulation ICs to enable stimulation on 16 sites at one time, selected from 32 available stimulation channels. These variations provide researchers with options in balancing channel count, size, and cost. Given the board dimensions of Iris 128B and Iris 128S (27 × 44 mm and for 24 × 30 mm respectively) and weight (9.61 g and 4.47 g respectively), these headstages in their current form factor may be more suitable for acute rodent, bird, and non-human primate (NHP) studies. Future iterations will focus on miniaturization to better support wireless systems and freely moving behavior experiments.

Despite the slight size differences, both systems exhibited similar electrical characteristics when connected to a microfabricated test platform. Figure 5 compares the frequency response of the Iris 128B and Iris 128S headstages, showing similar characteristics to the Intan RHS and RHD2000 amplifiers, which is expected since both designs are using these amplifiers (Intan Technologies 2017). All headstages exhibited a broadly flat midband gain profile and appropriate attenuation at the frequency extremes. For the Iris 128B, the 3 dB cutoff points were observed below 1 Hz and above 5 kHz. The Iris 128S showed a slightly lower low frequency attenuation without switching components below 0.5 Hz and more pronounced attenuation with the switch included, below 0.8 Hz. High-frequency roll-off remained above >5 kHz for all headstages. Minor deviations in the frequency response between headstages (e.g. Iris 128S with and without switching components) are within the expected variations of the ICs in the signal path (RHD2164, RHS2116, and ADGS5414). Overall, both headstages preserve characteristics similar to the intended filter characteristics and are suitable for high-fidelity neural signal acquisition.

In this work, we fabricated 128-channel polyimide-based MEAs with platinum electrode sites. These arrays were then connected to headstages using a Samtec SEARAY connector (figure 4) via a solder reflow process, which is routinely employed in the Deku lab for high-density interconnects. Polyimide and platinum were selected because they are prevalent in neural interface designs, offering ease of fabrication, bioinert properties, and a history of long-standing use (Cogan 2008, Tringides and Mooney 2022). To ensure that each channel was properly bonded and to rule out contributions from contact resistance in subsequent electrochemical and noise measurements, we performed micro-CT imaging to verify mechanical and electrical contact across all connector pins.

Figure 6 shows the impedance spectra of the bonded polymer microelectrodes across a frequency range of 50 Hz–5 kHz, measured using both a Gamry potentiostat and various headstages. The impedance profiles of the custom headstages (Iris128B, Iris128S RHD, and Iris128S RHS) follow the same trends observed with the commercial 16-channel Intan RHS headstage and the potentiostat, demonstrating consistency across measurement platforms. At 1 kHz, the impedance values (141–548 kΩ) fall within the expected range reported for similar platinum electrodes of this size (Fan et al 2021). As anticipated, these microelectrodes operate in the linear portion of the EIS curve between approximately 10 Hz and 10 kHz, confirming that the recorded impedance behavior supports proper headstage functionality. The agreement across all devices indicates that the custom headstages can reliably capture electrode impedance comparable to standard commercial systems.

The stimulation capability of the headstages was demonstrated in PBS and is shown in figure 7. In this test, we applied biphasic, cathodic-first, constant-current pulse at 2 nC ph−1 (4 μA current, 500 μs pulse width) and 100 pulses per second, corresponding to a charge density of 0.1 mC cm−2, delivered to 8 electrodes using the Iris 128B, Iris 128S, and a commercially available 16 channel Intan RHS headstage. As shown in figure 7, the voltage transient response to the stimulation pulse was similar between both Iris headstages and the commercial RHS 16 channel Intan headstage. Average Vdrive demonstrated performance comparable to the commercial RHS 16-channel Intan headstage. The average ± standard mean error for Vdrive (n = 8 electrodes) was −0.75 ± 0.05 V, −0.76 ± 0.09 V, and −0.76 ± 0.04 V, for Iris128S, the commercial headstage, and Iris128B, respectively. These measurements were intended to validate the accuracy and stability of current delivery across systems, rather than to characterize the electrochemical behavior of platinum electrodes. The strong agreement with a commercial reference confirms that the Iris headstages deliver current pulses with comparable fidelity, providing confidence for stimulation studies. However, because the headstages sample at 33 μs intervals, they lack the temporal resolution needed to fully resolve the fast electrochemical processes that define electrode behavior. Features such as ohmic resistance drops for example likely occur within the first few microseconds of a pulse—long before the system is able to record. For this reason, we interpret the VT primarily as validation of current delivery rather than as a detailed characterization of electrode–electrolyte interface properties. To validate the accuracy of stimulation delivered by the Iris 128B headstage, we compared the electrode voltage responses measured simultaneously with the PlexStim system (figure 8(B)) and the Iris 128B (figure 8(A)). Unlike the Intan— or Iris-based headstages, which sample at 33 μs intervals, the PlexStim records at a much higher temporal resolution of 3.2 μs. This finer sampling rate enabled us to capture fast features of the voltage transient—particularly the rapid capacitive polarization and peak potentials—that are not fully resolved by the lower-resolution systems. For both injected currents (2 μA and 6 μA), the voltage waveforms showed a monotonic increase in the Vdrive, demonstrating consistent electrode–tissue interface responses across platforms. Although the PlexStim and Iris 128B differ in sampling rate and acquisition resolution, the resulting Vdrive traces are closely aligned in both shape and amplitude. The strong agreement between the two measurements confirmed that the Iris 128B delivers stimulation with accuracy comparable to PlexStim while highlighting the importance of high temporal resolution for faithfully capturing transient dynamics.

While we demonstrated this capability in vitro, the system was not explicitly evaluated for reporting electrochemical properties of the microelectrodes. However, using the Intan system to report VTs holds potential for providing general insights into electrode stability and charge transfer dynamics in vivo in future studies, an area often overlooked by traditional electrochemical characterization (Cogan 2008).

Our in vivo validation assumes that the recorded data from our animal model provides a representative example of typical neural signals. While both planar and shank-based arrays were fabricated, the penetrating shank design was selected for in vivo testing to demonstrate the system’s ability to record single-unit spiking activity. The planar arrays are well suited for surface recordings, such as ECoG, but penetrating electrodes provide improved unit isolation and access to deeper brain regions, making them more appropriate for capturing single-unit activity (McNaughton et al 1983, Khodagoly et al 2015). Representative spikes on the Iris 128B yielded an SNR of 20.15 ± 0.68, which is comparable to values obtained using commercial platforms (Pancrazio and Cogan 2019, Tambaro et al 2021, Voitiuk et al 2021). The measured input-referred noise of the Iris headstages is close to the acquiescent noise of the Intan ICs (table 2), as expected given that these chips form the core of the system.

Additionally, given the headstages’ larger size compared to traditional rodent-scale headstages, we assume its primary applications will be in acute rodent studies or adapted for implantation in larger species, such as NHPs. Further miniaturization, towards or beyond the typical maximum of 10% of an adult rat’s body weight, is essential to achieve a low-profile form factor suitable for chronic implantation, and to enable use in other small animal models such as mice and birds (Szuts et al 2011, Crispin-Bailey et al 2019). Additionally, integrating wireless data transmission will be critical for eliminating tethering constraints and improving animal mobility.

The limitations of current commercial technology, and the present work, further emphasize the need for continued development of accessible and adaptable alternatives. While Intan chips are widely used and user-friendly, with integrated stimulation drivers, they rely on a wired interface that results in bulky cabling when scaled. This further constrains experimental setups and limits system reusability. Reliance on proprietary systems like those from Blackrock or TDT creates an artificial barrier when scaling to a large number of channels, especially when GHz-range processors with Gb/s communication interfaces are readily available in consumer electronics at a fraction of the cost and could feasibly handle similar processing tasks.

5. Conclusions

The evolution of open-source platforms has demonstrated the benefits of standardized interfaces and collaborative tool development. Our headstages build on these principles by offering a solution that integrates with existing acquisition systems. While many publications claim to offer open-source hardware or software, these resources are often shared without the context, documentation, or support necessary for other researchers to adopt and use them. We acknowledge this challenge and aim to go beyond simply posting design files online. To facilitate real adoption, we are providing detailed user guides, design rationales, and annotated documentation to help users understand and adapt the system to their own needs. While we cannot guarantee community uptake or integration into existing platforms, we see this release as an important first step towards more accessible, scalable headstages. Currently, to our knowledge, there are no openly available 128-channel headstages with bidirectional capability; this design fills that gap and provides a valuable, open-source tool for high-density neural recording and stimulation.

Acknowledgments

Authors would like to acknowledge the Knight Campus X-ray Imaging Facility and its Director, Angela Lin, for providing scan and image processing expertise and guidance. Scans performed with the Zeiss Xradia 620 Versa were made possible with equipment acquisition funding support from the M J Murdock Charitable Trust (Grant # SR-201812008).

Funding

This work was supported by the National Science Foundation NRT program under Grant No. DGE-2022168 and the National Institute of Neurological Disorders and Stroke under Award No. R01NS136987. Funding also came from OpenIC.

Footnotes

Conflict of interest

The authors declare that the research was performed independently, without any commercial or financial relationships that could pose a conflict of interest.

Data availability statement

The data that support the findings of this study are openly available on Open Science Framework at https://doi.org/10.17605/OSF.IO/XS2PU (2025) and on GitHub at https://github.com/openic-org/iris-128 (2025).

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Associated Data

This section collects any data citations, data availability statements, or supplementary materials included in this article.

Data Availability Statement

The data that support the findings of this study are openly available on Open Science Framework at https://doi.org/10.17605/OSF.IO/XS2PU (2025) and on GitHub at https://github.com/openic-org/iris-128 (2025).

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