Homeostatic dendritic neuron based on co-integrated volatile and non-volatile memristors for neuromorphic processing

Abstract

Neuromorphic systems offer energy-efficient solutions for temporal signal processing by emulating the dynamics and heterogeneity of biological neural circuits. However, conventional approaches face challenges in adaptive regulation and in capturing multi-timescale temporal features. Here, we present a bio-inspired neuromorphic hardware system that integrates homeostatic neurons with programmable dendritic structures. Utilizing the threshold-switching characteristics of VO₂, we construct a homeostatic neuron enabling autonomous stabilization of neuronal activity. The dendritic module, co-designed using CMOS-RRAM and VO₂ devices at the board level, enables programmable spike delays for multi-timescale temporal feature extraction. When embedded into a spiking neural network, the system achieves classification accuracies of 92.14% ± 0.99% for industrial defect detection and 86.53% ± 0.18% for speech recognition, while operating at 19.29 pJ per spike, surpassing conventional processors. The results demonstrate a scalable and biologically inspired hardware framework for efficient temporal signal processing, suggesting potential in next-generation neuromorphic accelerators.

Current neuromorphic systems are constrained in handling temporally complex computation. Zhang et al. present a fully memristor-based neuron-dendritic system that endows multi-timescale signal processing capability, delivering accurate and energy-efficient computational performance.

Introduction

The application of deep neural networks (DNNs) to time-series data processing has garnered significant attention in fields such as disease diagnosis¹, speech recognition^2–4, and fault detection^5,6. However, the conventional DNN neuron is usually modeled as a weighted sum of inputs followed by a nonlinear activation function⁷. The simplified representation fails to capture the intricate dynamic behavior of neurons and lacks the ability to retain temporal information, ultimately constraining the network’s effectiveness in processing time-series data^8–10. Furthermore, from a hardware perspective, computing-in-memory architectures designed to accelerate DNNs incur area and energy overheads, which is primarily attributed to the analog-to-digital conversion modules and the digital circuits required for nonlinear function computations^11–16.

Owing to the rich heterogeneity observed in the brain^17–19, including diverse temporal dynamics across neuronal, dendritic, and synaptic components^20–24, the brain exhibits a remarkable ability to process complex temporal signals²⁵. Motivated by these mechanisms, spiking neural networks (SNNs) utilize spike-based temporal coding to effectively handle time-dependent signals^26–29. Depending on the application scenario, computational efficiency, and hardware constraints, various spiking neuron models have been employed in SNNs, including Hodgkin–Huxley model, leaky integrate-and-fire (LIF) model, adaptive leaky integrate-and-fire (ALIF) model, and Izhikevich model^30–35. Most existing neuron models produce fixed spiking frequencies, and even the relatively more advanced ALIF neurons mainly exhibit a simple decay trend following spikes, reflecting limited adaptability^36–39. However, these neuron models largely overlook homeostatic regulation mechanisms, which are crucial for counteracting long-term fluctuations in average activity and ensuring a stable and information-rich neural operating regime^40,41.

In parallel, dendritic effects are crucial for neuronal information processing, and increasing research efforts have explored the incorporation of dendritic structures into the design of SNNs. For instance, traditional matrix multiplication has been replaced by local dendritic integration⁴², dendritic ensembles have been utilized for information encoding⁴³, and direction selectivity has been achieved through dendrite-based neuronal structures⁴⁴. Architecturally, hardware dendrites involve a trade-off between one-synapse-per-dendrite structures^45,46, which offer granular temporal control at the expense of hardware redundancy, and multi-synapse shared-dendrite configurations^47,48, which maximize area efficiency by multiplexing inputs onto shared temporal dynamics. While these dendritic structures can be regarded as extensions of the point neuron, they often overlook the intricate nonlinear interactions that occur post-dendritic integration. Moreover, these efforts have primarily focused on dendritic integration, overlooking the critical interplay between dendritic architecture and spiking dynamics, which is fundamental to neuronal computation and temporal information integration^49,50.

Owing to abundant ion dynamics and electrical behaviors akin to those found in biological neurons and dendrites, emerging memory technologies, e.g., resistive random-access memories (RRAMs) and phase-change materials like vanadium dioxide (VO₂), are promising candidates for realizing compact neuromorphic architectures efficiently. These technologies offer advantages, including a small three-dimensional footprint and near-zero static power consumption, enabling efficient hardware implementations. While memristors have been extensively used to implement and store weight parameters^11,51–55, emulate long short-term dynamics^56–58, and realize LIF and ALIF neurons⁵⁹, few studies have demonstrated hardware implementations of homeostatic neurons or more complex dendritic processing that have been shown to enhance the computational capabilities of neuromorphic systems. More importantly, a fully integrated memristor-based neuromorphic signal processing system that combines an efficient spike encoding scheme with a biologically plausible architecture incorporating homeostatic neurons and dendritic structures has yet to be reported.

In this work, we present a comprehensive neuromorphic processing system that addresses above-mentioned limitations by incorporating both neural homeostatic regulation and distributed dendritic computation. Our approach leverages the threshold-switching characteristics of VO₂ devices to implement homeostatic neurons capable of restoring their stable state after transient activity changes, and employs CMOS circuits, RRAM, and VO₂ devices to realize dendritic structures with programmable delays. By adopting a resource-efficient shared-dendrite architecture, our approach scales the number of dendritic units down to the number of neurons, reducing hardware overhead compared to traditional RRAM-based implementations that require per-synapse dendritic structures. Furthermore, instead of relying on sophisticated peripheral circuitry for spike generation, we leverage the intrinsic threshold-switching characteristics of VO₂ devices to directly implement neuronal firing mechanisms. We demonstrate the effectiveness of our approach through two validation studies: integrating homeostatic neurons into SNN for defect detection task achieves 4.83% accuracy improvement over conventional LIF neurons, while incorporating dendritic structures into SNN architecture for speech recognition task yields 1.58% accuracy enhancement compared to baseline. The integrated system demonstrates the capability of neuromorphic hardware to emulate biological efficiency and adaptability in processing complex temporal patterns, supporting edge computing applications for dynamic scenarios.

Results

Memristor-based system for temporal data processing

We present a hierarchical SNN architecture (Fig. 1a) that integrates distributed dendritic computation with homeostatic regulation mechanisms for temporal information processing across multiple timescales, achieved through dendritic delays and varied neuronal firing frequencies to enable simultaneous extraction of fast and slow temporal features. Each neuron integrates a specialized synaptic interface for weighted spike summation, followed by dendritic branches that perform parallel temporal filtering through programmable delay elements. Nonlinear integration at the soma incorporates adaptive thresholding governed by intrinsic homeostatic mechanisms, ensuring stable activity under dynamic input conditions. Network connectivity follows a feedforward topology with full inter-layer connections, enabling comprehensive information transfer between processing stages while maintaining computational tractability. This design enables the extraction of complex temporal features while maintaining computation efficiency through event-driven processing, where neurons remain inactive in idle mode.

Fig. 1. Schematic of the proposed memristor-based neuromorphic computation.

a Spiking Neural Network (SNN) fundamentals. SNN neuron structure illustrating synaptic inputs, dendritic integration, soma processing, and spike output generation. SNN neuron model showing mathematical representation with weighted input summation, dendritic processing, and membrane potential dynamics leading to spike generation. SNN architecture depicting multi-layer network topology with spike-based information processing between input, hidden, and output layers. b By leveraging the threshold switching of volatile VO₂ memristors, a homeostatic neuron circuit is designed to modulate its spiking frequency and restore stability, emulating homeostatic regulation in biological neurons. Meanwhile, a dendritic circuit based on non-volatile RRAM memristors introduces programmable delays to mimic dendritic signal transmission. The complete neuromorphic system integrates both the neuron and dendritic circuits, with each module controlled and coordinated via an FPGA platform.

The system (Fig. 1b) integrates VO₂ based homeostatic neurons with RRAM-based dendritic delay units in a comprehensive neuromorphic platform. By leveraging the threshold-switching characteristics of VO₂ devices, we develop a homeostatic neuron that extends the adaptive threshold behavior of classical ALIF neurons. In addition to dynamic threshold modulation, the proposed neuron exhibits intrinsic stability through homeostatic regulation, enabling it to autonomously recover from both excitatory and inhibitory perturbations. Furthermore, we implement dendritic circuits by integrating packaged VO₂ devices with RRAM arrays and CMOS circuits on a printed circuit board (PCB), incorporating programmable delays across branches to enable temporal processing. The outputs of different dendritic branches are dynamically integrated within a neuron, where their interactions give rise to complex temporal dynamics, enabling the capture of multi-scale temporal features. The system demonstrates a modular and scalable architecture by co-locating memory and computation, thereby alleviating the von Neumann bottleneck that constrains conventional processors. By employing a field-programmable gate array (FPGA) to handle data distribution and routing, the system provides a flexible hardware platform for spiking neural computation while maintaining real-time processing capability. Moreover, the event-driven operation ensures energy-efficient utilization of computational resources, as they are activated only in response to neural activity.

Vanadium dioxide-based leaky integrate and fire neuron

Neurons serve as the fundamental unit of a neuromorphic system, their reliability and stability are essential for developing efficient and robust neuromorphic systems. To effectively emulate biological neuronal spiking behavior, VO₂ based volatile memristors with stable threshold switching characteristics present a promising solution for neuromorphic systems. The schematic diagram and scanning electron microscope image of the VO₂ memristor used in this work are shown in Fig. 2a and Supplementary Fig. 1, indicating a channel length of 400 nm and an electrode width of 2 μm. Detailed information about the fabrication process can be found in the “Methods” Section. We performed 500-cycle voltage sweeps and plotted the current-voltage (I–V) characteristics of the VO₂ memristor (Fig. 2b), which demonstrates stable threshold switching behavior. When a voltage exceeding the threshold voltage (V_th) of around 3.45 V is applied across the device, the VO₂ memristor transitions from the high-resistance state (HRS) to the low-resistance state (LRS). Once the voltage drops below the holding voltage (V_hold) of around 1.70 V, the device switches back from LRS to HRS. Previous studies have shown that this switching behavior is primarily driven by phase transitions induced by Joule heating and the formation of conductive filaments^60–63. Supplementary Fig. 2 further presents the I–V curve under a compliance current of 200 μA, depicting the device’s behavior over 500 cycles of both positive and negative voltage sweeps. The results validate that the device exhibits the same threshold voltage and holding voltage under both positive and negative voltages. Figure 2c presents the cumulative plots of positive and negative threshold or holding voltages, including V_{th_pos}, V_{hold_pos}, V_{th_neg}, and V_{hold_neg} across 500 repeated cycles. The coefficient of variation (C_v), defined as the ratio of the standard deviation (σ) to the mean value (μ), was calculated for each voltage: 1.01% for V_{th_pos}, 1.47% for V_{hold_pos}, 0.97% for V_{th_neg}, 1.39% for V_{hold_neg}, indicating very low cycle-to-cycle variations. The device operates reliably after more than 10⁶ switching cycles, demonstrating stable threshold switching characteristics, as shown in the Supplementary Fig. 3. In addition, we characterized the device-to-device variation of 20 VO₂ memristors and extracted the C_v of both V_th and V_hold to be 4.93% and 5.70%, respectively (Supplementary Fig. 4). These characteristics make it suitable for constructing artificial neurons.

Fig. 2. Basic LIF neuron implemented using VO₂ device.

a Schematic of the VO₂ device with a channel length of 400 nm and an electrode width of 2 μm. The scale bar for the device channel represents 600 nm, and the scale bar for the entire device represents 10 μm. b I–V characteristics over 500 switching cycles, demonstrating stable volatile resistive switching, and the constructed Verilog-A model shows good agreement with the experimental results. c Cumulative distributions of V_{th_pos}, V_{hold_pos}, V_{th_neg}, and V_{hold_neg}, demonstrating low variations. d Circuit of the constructed LIF neuron. e Response of the neuron with 100 pF external capacitance and 80 kΩ load under 6 V pulse input. f As the membrane capacitance increases, the spike output frequency of the LIF neuron decreases. g Schematic of the current-input LIF neuron. h Membrane potential and spike frequency responses under varying supply currents. i As the supply current increases, the interval between spikes decreases, resulting in a higher spike frequency of the neuron.

The basic LIF neuron is implemented through a hybrid analog circuit comprising resistor, capacitor, and VO₂ switching components shown in Fig. 2d. The VO₂ volatile memristor is placed in series with a small resistor R_o (3 kΩ), which converts the pulse current signal into a series of voltage spike output. A capacitor C_m (100 pF) is placed in parallel, converting the voltage across the capacitor to the membrane potential of the neuron. The circuit was fabricated and tested on a PCB, and all electrical waveforms were experimentally recorded using an oscilloscope, with the measurement setup schematically shown in Supplementary Fig. 5. The measurement results, presented in Fig. 2e, show that when a voltage pulse of sufficient amplitude is applied, the capacitor begins to charge. Once the voltage across the VO₂ memristor exceeds V_th, it switches to the LRS, causing a reduction in the voltage across the memristor. The capacitor then rapidly discharges through the memristor and resistor R_o, generating an output spike. The discharge continues until the voltage across the memristor drops below V_hold, at which the memristor switches back to the HRS. Such operation repeats, producing a series of spikes, as shown in Fig. 2e. The neuron’s output frequency is primarily governed by the capacitor’s charge-discharge dynamics, which depend on the capacitance, resistance, and input voltage. As the input voltage drives the entire neuron and the time constant depends on the capacitance and resistance, we conducted further experiments to evaluate the spike frequency under different input voltages, load resistances, and external capacitances. Figure 2f further shows the response of the artificial neuron with different external capacitances while maintaining a constant input voltage of 6 V and a load resistance of 80 kΩ (detailed results can be found in Supplementary Fig. 6). As the external capacitance increases, the integration process slows down, leading to a reduction in the firing frequency. Similarly, a larger R_L or a lower voltage reduces the input current, thus slowing down the charging process, thereby reducing the firing frequency (Supplementary Figs. 7 and 8).

The voltage-driven neuron designed for spike encoding generates spike signals primarily through voltage division between the VO₂ device and a fixed-value resistor, along with the threshold switching behavior of the VO₂ device. While this structure effectively emulates spiking behavior, realizing more advanced functions such as homeostatic regulation would require structural enhancements to the neuron, including the incorporation of feedback mechanisms that dynamically adjust the input. Considering that voltage control in circuits is generally more complex than current control, we physically designed and tested a current-input neuron to facilitate system integration and enable more sophisticated functionalities, as illustrated in Fig. 2g. We applied gradient current inputs and experimentally measured the corresponding changes in membrane potential and spike frequency, as shown in Fig. 2h. Further experiments were conducted to measure the change in the output spike frequency of the neuron under current inputs with varying amplitudes. The results, shown in Fig. 2i, show that increasing the current magnitude leads to a higher output spike frequency, due to faster capacitor charging.

To further analyze the spiking behavior of the neuron and provide reference for the design of structures with extended functionalities, we developed a Verilog-A model for the memristor based on ref. ⁶⁴ The model has no polarity, and in addition to the typical HRS and LRS transitions at the threshold voltage (V_th) and holding voltage (V_hold), it also captures the nonlinear behavior of the device in the HRS when operating below the threshold voltage. The model primarily comprises a voltage-dependent resistor, which adjusts its resistance in the HRS or LRS and switches states when the terminal voltage exceeds the defined thresholds, as illustrated in Supplementary Fig. 9. A small parasitic capacitor (C_p) is added in parallel to prevent transient switching behavior and ensure pulse signal generation. The simulation results of the constructed model show good consistency with the measured data of the device, as shown in Fig. 2b. Further simulations of the LIF neuron’s spiking behavior were conducted using the developed Verilog-A model on the HSPICE platform and the simulation results show good agreement with the experimental results, as illustrated in Fig. 2f, i and Supplementary Fig. 10, validating the effectiveness of the model.

Vanadium dioxide-based homeostatic neuron

Although basic LIF neurons are easy to implement, they tend to generate a fixed spike frequency under constant input and lack biologically inspired mechanisms like homeostatic regulation to modulate their firing behavior. To address these limitations, we propose a homeostatic neuron, as illustrated in Fig. 3a, which incorporates a feedback loop to regulate its firing behavior. This feedback mechanism enables the neuron to partially restore its firing rate after perturbations, thereby improving its ability to encode temporal information. Two MOSFETs were introduced to either supply or leak current, allowing for regulation of the output spike frequency. The output spikes are fed back through a feedback loop to control the gate voltages of the MOSFETs. This dynamic feedback mechanism enables the neuron to sense its own activity level, thereby maintaining a relatively stable firing frequency.

Fig. 3. Design of homeostatic neuron based on VO₂ device.

a Comprehensive characterization of the homeostatic neuron. The frequency-voltage characteristics illustrate how M₁ and M₂ transistors regulate neuronal spiking frequency by either supplying additional current or providing a leakage path for the input current. The corresponding circuit schematic comprises a basic LIF neuron and a feedback module. The voltage response at node₁ in the feedback module is shown as a function of input pulse number, modulated by the gate bias voltage applied to M₆. b Schematic diagram of the frequency regulation mechanism of the homeostatic neuron. c The voltage changes at different nodes of the neuron under a 40 µA input, where the pulse output frequency decreases first and then returns to the initial spike frequency. d Replace the M₁ and M₂ transistors with PMOS, and test the process of the neuron’s spike output frequency increasing and stabilizing under a 15 µA input.

To illustrate how these transistors modulate the spike frequency through current supply and leakage, we simulated the output spike frequency under a fixed 40 µA current while varying the voltage at node₁. The simulated results in Fig. 3a demonstrate that as the voltage at node₁ increases, the output spike frequency shows a non-monotonic variation, first decreasing and then rising. Further details regarding the specific contributions of each NMOS transistor can be found in Supplementary Figs. 11 and 12. We simulated the effect of applying a pulse with a period of 10 µs and a pulse width of 500 ns as the spike output of the neuron to the feedback module. The simulation results shown in Fig. 3a, demonstrate that as the number of applied pulses to the feedback module increases, the voltage at node₁ gradually rises under different gate bias voltages of M₆. The charging rate of node₁ can be controlled by adjusting the gate bias voltage of M₆. These simulations confirm that the feedback module meets the requirements for the frequency self-tuning capability of our neuron. Moreover, we carefully designed the sizes of M₁ and M₂ to regulate the supplemental and leakage currents within optimal ranges, thereby ensuring that the input current remains suitable for sustaining oscillation, as demonstrated in Supplementary Figs. 13 and 14. Consequently, the size of C_m, as well as transistors, must be designed to ensure that the time constant is at least an order of magnitude greater than the output oscillation period (simulation results in the supplementary Figs. 15 and 16 and detailed parameter design in the Supplementary Note 1).

Building upon the basic LIF neuron, where spike generation relies on the threshold switching behavior of the VO₂ device, we introduced a feedback loop to enhance and regulate its firing dynamics. The mechanism behind the transient changes in spike frequency and the subsequent return to a stable state is illustrated in Fig. 3b. Initially, the basic neuron generates spiking outputs in response to the input current, and those spikes gradually charge capacitor C₁ through the feedback loop, leading to a slow increase in the voltage at node₁. When the voltage remains below a certain threshold, transistor M₂ dominates, causing leakage current to reduce the input current and thereby decreasing the spike frequency. Conversely, once the voltage exceeds the threshold, transistor M₁ takes over, increasing the input current and consequently raising the spike frequency, eventually bringing it back to its stable firing rate. Further details of the principle can be found in the Supplementary Note 2. To verify this homeostatic regulation, we conducted transient simulations by applying a pulse with fixed amplitude to the neuron model and monitored the gate voltage, output spikes, and membrane potential. The simulated waveforms, shown in Fig. 3c, clearly illustrate the transient modulation and subsequent recovery of spike frequency, where each generated pulse causes the voltage at node₁ to increase, leading the output spike frequency to initially decrease and then rise. The steady-state regulation process can be controlled by adjusting circuit parameters, such as the C₀, the W/L of M₅ and M₆, and gate voltage bias of M₆ (Supplementary Fig. 17). Therefore, this neuron structure provides flexible control over the steady-state regulation process in various ways. Additionally, by replacing the NMOS transistors M₁ and M₂ with PMOS transistors, the pulse frequency initially increases and then returns to its normal value (Fig. 3d and Supplementary Fig. 18). This demonstrates that the neuron structure can mimic the natural modulation of spike frequency, with either an increase or a decrease followed by a homeostatic return to stability.

Dendritic design with volatile and nonvolatile memristors

In addition to the homeostatic regulation observed in neurons and their internal temporal variability, heterogeneity between dendritic branches within neural circuits has also been identified. The dendritic structure introduces branch-specific delays to achieve nonlinear spatiotemporal integration, enabling local feature detection and the capture of time-dependent patterns across multiple time scales⁴⁹. In this work, we utilize non-volatile RRAM devices to store synaptic weights and realize programmable delays. The non-volatile memristors feature a TiN/HfO₂/TaO_x/TiN structure, as illustrated in Fig. 4a, with HfO₂ serving as the resistive switching layer and TaO_x as the oxygen reservoir layer. Further details about the 1T1R array can be found in the Supplementary Note 3. Figure 4b shows the typical I–V characteristics of the 1T1R non-volatile memristor for 1000 repeated cycles after the forming operation, with the voltage ranging from −1.8 to 1.5 V and the gate voltage set at 3.3 V. In addition, we performed endurance tests by repeatedly applying set and reset operations to the device, and the results are shown in Supplementary Fig. 19. Our device demonstrates analog resistive switching and multilevel behavior by applying a series of set-reset pulses which gradually increase the pulse amplitude (Fig. 4c). Furthermore, to demonstrate that the array is suitable for analog in-memory computing, we measured the conductance after programming the analog values, and the conductance exhibits only minor deviations from the target values (Supplementary Fig. 20). Figure 4d and Supplementary Fig. 19 display the cumulative distribution functions across 8 independent conductance states and the excellent retention characteristics of our non-volatile memristor. These characteristics confirm that the array is suitable for both analog in-memory computing and the implementation of dendritic structures with tunable delays, thereby improving computational performance.

Fig. 4. The dendritic structure and its fundamental units.

a Photograph of the packaged 32 × 18 1T1R memristor array and schematic diagram of its TiN/TaO_x /HfO₂/TiN structure. b Typical I–V characteristics of a memristor from 1T1R cell for 1000 measurements. c The gradual change in memristor conductance during the set and reset processes under a series of pulse inputs. d Cumulative probability distribution of 576 cells with respect to 8 independent conductance states. e The overall schematic diagram of the dendritic structure. f The PCB hardware diagram of the entire dendritic structure. g The detailed circuit of the dendritic structure. h The dendritic structure exhibits different output delays depending on the conductance states of the memristors at a read voltage of 0.2 V. i Structural modification of the dendritic circuit by integrating a voltage-holding unit with the current-to-voltage conversion circuit to support deeper network layers. j Under a narrow pulse, the dendritic structure generates a single spike output with varying delays depending on the conductance.

The overall schematic diagram of the dendritic structure used to achieve the delay function is illustrated in Fig. 4e, which comprises a 1T1R RRAM array, a pulse generation circuit based on VO₂ device, and a transimpedance amplifier (TIA) that converts the output current into the neuron’s input voltage. During readout, the current charges the membrane potential through the TIA, where higher resistance leads to longer delays and lower resistance to shorter ones. The fabricated hardware system, illustrated in Fig. 4f, comprises a VO₂ array for pulse generation, an RRAM array for weight storage, and the necessary peripheral circuitry. The detailed circuit configuration of the dendritic structure is presented in Fig. 4g. Experimental tests under various RRAM conductance states reveal that the dendritic structure produces distinct output responses corresponding to different temporal delays, as shown in Fig. 4h and Supplementary Fig. 21.

Although the dendritic circuit in Fig. 4g can introduce a delay between the input and output, its behavior is limited by the width of the input pulse and often results in multiple output spikes from a single pulse input. These properties make it particularly suitable for implementation near the input layer of SNN, where rich temporal information from sensory signals can be exploited. However, these features may cause redundant spikes and disrupt temporal coding in the hidden layers, where precise temporal coding and controlled spike propagation are essential. Therefore, structural modifications are necessary to tailor the dendritic behavior for deeper network layers. To address this, we designed a modified dendritic circuit incorporating a pulse peak-holding mechanism, which preserves the membrane voltage after the read pulse is removed. This modification stabilizes the neuron’s input and prevents multiple spike firing. The detailed schematic and performance evaluation are provided in Supplementary Fig. 22. We further optimized the circuit design by employing the operational amplifier of the TIA circuit as the first stage of the pulse-hold circuit, instead of directly widening the input pulse, as illustrated in Fig. 4i. Figure 4j and Supplementary Fig. 23 show the experimentally measured output spikes in response to the applied pulse inputs under different RRAM conductance states, exhibiting delays ranging from 45 to 63 μs. When the RRAM device is programmed to a low-conductance state, the pulse input results in a larger delay in the output. Notably, by varying the capacitance parameters, the temporal delay can be flexibly tuned across a broad range from 15 μs up to 5 ms, as shown in Supplementary Fig. 24.

Hardware architecture and system implementation

The hardware platform developed in this work serves as a partial experimental realization of key functional modules of the proposed SNN architecture, rather than a fully monolithically integrated system. The architecture is designed to emulate essential features of dendritic processing and history-dependent spiking dynamics. Conceptually, the system comprises dendritic delay circuits coupled with neuron structures (Fig. 5a). Each dendritic branch within the circuit array incorporates multiple synaptic processing elements connected through programmable delay units, mimicking the temporal dynamics inherent in biological dendritic computation. Synaptic weights are realized using RRAM devices that provide non-volatile and continuously tunable conductance states for flexible weight modulation. By adopting a paired differential RRAM configuration, the system reliably encodes both positive and negative weights, providing hardware-level support for signed computational parameters. The details of the signed-weight mechanism are provided in the Supplementary Fig. 25 and Supplementary Note 4. The dendritic computation is achieved through hybrid analog circuits assembled at the PCB level using packaged VO₂ devices, RRAM arrays, and discrete CMOS amplifier components, enabling programmable temporal dynamics and nonlinear processing. The scalable architecture enables parallel processing through multiple dendritic branches that can be configured to receive multi-channel input spike trains simultaneously. This parallel dendritic tree structure converges onto individual output neurons, allowing each neuron to integrate spatiotemporally distributed input patterns. Multiple such dendritic trees can be arranged in groups to form larger network topologies, establishing connectivity between input and output layers. Within each group, input spike sequences are broadcast across all dendritic trees, while word lines (WL) and access transistors provide independent control over individual RRAM cells, enabling programmable temporal delay configuration.

Fig. 5. Illustration of the time-series signal processing system, accompanied by a fault detection application demonstrating the effectiveness of the proposed homeostatic neuron.

a Schematic diagram of the dendritic structure with multiple programmable delay paths and self-tuning neurons. b Experimental setup showing the complete neuromorphic computing system implementation. c The CWRU experimental setup used for investigating ball-bearing defects. d The overall structure of the inference process of the SNN. e Flow chart of the SNN operation. During the forward pass, the weighted input spikes are added to the weighted hidden spikes from the previous timestep and fed into the hidden layer. The resulting hidden spikes are low-pass filtered and then weighted to generate output vectors. In the final timestep, the output node with the highest value corresponds to the classification result. During backward pass, the cross-entropy loss is combined with the spike regularization term and propagated backward to update the weights. A differentiable surrogate function is employed to calculate the gradients. f A schematic diagram of the basic units included in the hardware platform. g Spike signals generated after encoding the input signal. h The accuracy and loss variations for both the training and test sets during the training process across ten independent runs. i Confusion matrix obtained from testing with the optimal model configuration. j Average test accuracy comparison among SNNs with homeostatic LIF (HSLIF), classical LIF, and adaptive LIF (ALIF) neurons, demonstrating the improved classification performance of HSLIF neurons. The values represent the mean of the best test accuracies during ten independent training runs.

The experimental setup implements a heterogeneous hardware validation framework that bridges software preprocessing with board-level neuromorphic modules (Fig. 5b). Raw input data undergoes preprocessing on a conventional PC before being transmitted to FPGA controller. The FPGA serves as the primary control and interface unit, managing real-time spike data streaming, conductance programming of RRAM devices, and temporal control of the test board. The board-level platform hosts the experimentally implemented dendritic circuits and basic LIF neuron modules, while the homeostatic LIF neurons are simulated. The bidirectional data flow architecture ensures efficient spike-based communication between computational layers. Output spikes generated by the neuromorphic PCB are captured by the FPGA for temporal buffering and formatting before transmission back to the PC for post-processing analysis and visualization. In this framework, the FPGA functions analogously to a control unit (or MCU) in a future fully integrated silicon implementation, while the PCB serves as a testbed for validating programmable dendritic delay and neuron–dendrite interaction. This staged validation architecture provides experimental verification of key functional mechanisms and programmable temporal dynamics.

Homeostatic neuron-based network for fault diagnosis

Building upon the neuromorphic hardware architecture, we develop a SNN system that integrates optimized temporal data encoding with our hardware-calibrated homeostatic neuron models, to evaluate their effectiveness through simulation in real-world-inspired applications. To efficiently convert continuous time-series signals into spike representations while preserving temporal information, we adopt a frequency-domain encoding strategy that combines Discrete Fourier Transform with LIF neurons. Specifically, we employ the Short-Time Fourier Transform (STFT) to decompose input signals into time-frequency representations, thereby mitigating inefficiencies in SNN processing caused by long time steps and overcoming the limitations of assigning each data sequence to a single input neuron. Most importantly, to validate the specific contribution of our VO₂-based homeostatic regulation mechanism to network performance and stability, we conduct comprehensive evaluations on the Case Western Reserve University (CWRU) bearing fault dataset⁶⁵, which provides an ideal testbed for assessing how the homeostatic regulation mechanism of our neuromorphic neurons enhance temporal pattern recognition under varying operational conditions compared to conventional neuron models without homeostatic regulation.

Figure 5c illustrates the CWRU experimental setup used for investigating ball-bearing defects. The vibration waveform data recorded by the sensors were first processed by category to obtain the expected dataset (as described in the “Methods”), and then split into training, validation, and test sets with a ratio of 0.7:0.1:0.2. We constructed a 3-layer SNN for solving the 10-class fault detection task. The SNN network includes 18 nodes in the input layer for receiving the encoded frequency domain features derived from the input data, 32 neurons in the hidden layer for intermediate processing, and 10 nodes in the output layer for representing the final classification results corresponding to the 10 fault categories. The overall structure of the inference process is illustrated in Fig. 5d, the spike signals are transmitted to the SNN decision network, which is equipped with homeostatic neurons and the output of the decision network distinguishes the damage types and sizes corresponding to the various signals.

The ability of homeostatic neurons to return to a stable state after excitatory or inhibitory activity, along with their rich dynamic behaviors, provides the network with enhanced capabilities for processing complex temporal information. During network simulations, neuron dynamics are modeled based on their circuit designs using the following membrane Eqs. (1–3). The input current $I$ is passed through a ReLU function in simulations to reflect the hardware behavior, as the physical neuron circuit receives current through a current mirror that inherently restricts the input to positive values without requiring additional circuitry. R_HRS is the effective resistance of the VO₂ memristor in HRS, R_L is the readout resistance, and I_leak represents the leakage current via transistors M₂ and M₁. When V exceeds V_th, it is reset to V_hold, where V_th and V_hold are the threshold and hold voltages of VO₂ memristor considering the readout resistor. I_leak depends on V_node1, which evolves according to the discretized dynamics Eq. (4). Where $\beta =\exp \left(-△t/{R_{\mathrm{eq}}C}_{\mathrm{m}}\right)$, z is 1 if a spike is fired and 0 otherwise, $I_{\mathrm{a}}$ is the adaptive charging current via M₃, and R_eq is the equivalent resistance of the transistor M₄ at a specific gate voltage.

$$I-I_{\mathrm{leak}}=C_{\mathrm{m}}\frac{dV}{dt}+\frac{V}{R_{\mathrm{HRS}}+R_{\mathrm{L}}}$$ 1

$$V\left(t+\mathrm{\Delta }t\right)=\alpha V\left(t\right)+\left(1-\alpha \right)\left(R_{\mathrm{HRS}}+R_{\mathrm{L}}\right)\left(I-I_{\mathrm{leak}}\right)$$ 2

$$\alpha =\exp \left(\frac{-△t}{R_{HRS}+R_L}{C}_{\mathrm{m}}\right)$$ 3

$$V_{\mathrm{node}1}\left(t+\mathrm{\Delta }t\right)=\beta V_{\mathrm{node}1}\left(t\right)+\left(1-\beta \right)R_{\mathrm{eq}}{I}_{\mathrm{a}}\mathrm{z}$$ 4

The forward pass during the training and testing, as well as the backward pass during only the training phase, is shown in the flow chart in Fig. 5e. During the forward pass, the neuronal state is determined by combining feedback signals from previous timestep outputs processed through recurrent modules and current timestep inputs transformed by weight matrices, for which the matrix–vector multiplication of selected weight vectors and input data is partially mapped onto the RRAM array (Supplementary Fig. 26). The backward propagation optimizes the fully connected weights using a total loss that integrates classification cross-entropy and a spike-based regularization term to encourage sparse neuronal firing. As each spiking neuron is a non-differentiable step activation function, we used a surrogate derivative for gradient calculations. We trained the SNN model for 200 epochs. Supplementary Fig. 27 presents the time-frequency features extracted via STFT from the original signal, along with the spike signals generated by encoding these features through neurons. These spikes are subsequently fed into the homeostatic neurons, whose membrane potential dynamics respond to the input spikes under the control of node₁ voltage and leak current, as illustrated in Fig. 5g. Figure 5f illustrates a simplified hardware architecture, where the positions of neuron node₁, the leakage current, and the membrane potential are indicated. We repeated the training procedure ten times using the same method. The evolution of accuracy and loss across epochs for all runs is shown in Fig. 5h and Supplementary Fig. 28. The maximum test accuracy from each run was recorded, yielding an average of 92.14% with a standard deviation of 0.99%.

To further evaluate the advantages of the homeostatic neuron over classical LIF and adaptive LIF (ALIF) neurons, we constructed SNNs of identical scale using these neuron types and trained them repeatedly on the same task. The LIF-based and ALIF-based networks achieved accuracies of 87.31 ± 0.51% and 90.04 ± 0.52%, respectively. A comparison of all configurations (Fig. 5j) indicates that the network incorporating our homeostatic neurons demonstrates an improvement in classification performance. Beyond the improvements in accuracy, our homeostatic neurons exhibit a significant advantage in continuous, long-term information processing compared to ALIF neurons. To assess this, we concatenated multiple test segments into longer sequences (Supplementary Fig. 30) and evaluated the performance of the trained HSLIF (homeostatic LIF neuron) and ALIF-based networks. As shown in Supplementary Fig. 30, the HSLIF-based network maintained stable performance across continuous samples, whereas the ALIF-based network showed a gradual decline in classification accuracy over time. This difference arises from the neurons’ intrinsic dynamics, as HSLIF neurons quickly recover after a sudden firing-rate drop, whereas ALIF neurons remain in a prolonged low-frequency state until manually reset. In addition, we have compared the performance of our constructed network with other models reported in the literature on the CWRU dataset. As presented in Supplementary Table 1, our proposed approach achieves slightly lower classification accuracy compared to some state-of-the-art networks; however, it demonstrates a remarkable reduction in both parameter count and computational cost. Consequently, under the same testing platform, our network is expected to deliver lower inference power consumption and latency, highlighting its efficiency and suitability for resource-constrained neuromorphic applications.

Network with dendritic structure for keyword spotting

To further demonstrate the role of our constructed dendritic structure within the SNN, we performed a keyword spotting task involving 35 keyword categories and 105,829 audio samples from the Google Speech Commands (GSC) dataset⁶⁶. We preprocessed the raw data as described in the “Methods” section, and the processed data was then fed into our SNN network, as illustrated in Fig. 6a. Building on homeostatic neuron and dendritic delay structure, we further developed an SNN model with richer dynamic behaviors. The network was modeled using experimentally extracted device parameters and corresponding circuit parameters from the implemented hardware system. These parameters were integrated into the network simulations to provide a realistic performance analysis aligned with the behavior of the physical hardware. The basic structure of each layer in the SNN network is shown in Fig. 6a. The three-order derivatives generated by our preprocessing are used as pre-synaptic inputs, distributed across three channels. Each input pulse on each channel within a branch undergoes programmable delays, and the temporal features of the input are identified by detecting coincident spikes between different channels on each branch. Through joint training of synaptic weights, neuronal time constants, and delay parameters, we optimize these programmable elements to achieve precise spike overlap for effective temporal feature detection. Additionally, the outputs from each dendritic branch are then gathered into the homeostatic neurons, where the time constant α controls pulse emission, and the time constant β governs the steady-state regulation process.

Fig. 6. Demonstration of a spiking neural network (SNN) incorporating homeostatic neurons and dendritic structures for speech recognition tasks.

a The waveform of the speech command backward is shown, and the raw audio data are transformed using STFT, followed by Mel filtering and extraction of the first three derivative orders. The processed data is then fed into the SNN decision system. STFT, short time fourier transform. b Distribution of delays across all dendritic branches. c A portion of the confusion matrix for the test results of the trained model. d Averaged accuracy and loss over 80 training epochs for four different models, calculated from ten independent training runs, along with results from testing. LIF leaky integrate and fire neuron, LIF & dendrite LIF neuron with dendritic compartments, HSLIF homeostatic LIF neuron, HSLIF & dendrite homeostatic LIF neuron with dendritic compartments.

An SNN with a network scale of 120 × 200 × 35 was constructed and trained for 80 epochs. The training process was repeated ten times, and the best accuracy from each trial was collected. The average of these best accuracies reached 86.53%, with a standard deviation of 0.18%. The input to each homeostatic neuron is distributed across eight dendritic branches, each introducing distinct delays during inference. These delayed signals are then merged at the neuron for spike generation, and Fig. 6b presents the statistical distribution of these delays. The spike emissions of 200 neurons over 101 time steps for the optimally trained model are depicted in Supplementary Fig. 31, demonstrating a sparsity of 89.78%. As demonstrated in the confusion matrix in Fig. 6c, the trained model exhibits high accuracy, and confusion matrix of all the data is shown in Supplementary Fig. 32. To further evaluate the effectiveness of the dendritic structure and homeostatic neuron, we compared four network configurations: (1) regular LIF neurons only, (2) homeostatic neurons only, (3) dendritic structures with regular LIF neurons, and (4) a combination of homeostatic neurons and dendritic structures. Each model was trained for 80 epochs with ten independent runs. The accuracy and loss curves of all runs are shown in Supplementary Fig. 33, and their epoch-wise averages are presented in Fig. 6d. The results indicate that introducing dendritic delays enhances the network’s spatiotemporal processing capability. To assess the hardware implications of these designs, we further evaluated and compared the silicon area of the four different model configurations for this task, as summarized in Supplementary Table 2. The results indicate that the additional homeostatic and dendritic modules introduce only a minor increase in area, while providing a 3.5% improvement in classification accuracy. To investigate whether the observed performance improvement is due to the learnability of the delays rather than merely the presence of delays, we conducted a control experiment with fixed delays. As shown in Supplementary Fig. 34, this fixed-delay model yielded a modest improvement over the baseline network without delays, yet consistently underperformed compared to the model with trainable delays. These results indicate that learnable dendritic delays contribute more to performance improvement than randomly assigned delays. We further analyzed the impact of dendritic delay range on network performance (Supplementary Fig. 35). The results indicate that an optimal delay range exists that maximizes system performance. In addition, we compared the constructed network with other models reported in the literature on the GSC dataset. As summarized in Supplementary Table 3, our network demonstrates significant advantages in terms of parameter count and computational cost while maintaining competitive classification accuracy. Since the silicon area is primarily dictated by the parameter storage and the energy consumption scales with the number of operations, our approach is expected to achieve improved area and energy efficiency when implemented on a unified hardware platform. These reductions in memory footprint and operational intensity translate directly into a more compact hardware design and minimized power consumption, thereby validating the suitability of our architecture for resource-constrained neuromorphic applications.

Since the RRAM and VO₂ devices used in our system may suffer from inherent variations, we conducted simulation analyses to evaluate the impact of such device variations on network performance. As shown in Supplementary Figs. 36 and 37, the classification accuracy decreased by only 1.42% when the RRAM conductance variation reached 10%, and by only 0.57% when the VO₂ threshold and holding voltages varied by 5%, demonstrating that the proposed network exhibits strong robustness against device variations. In addition, we evaluated the hardware-level performance of the proposed neuromorphic system for the 35-class GSC dataset. The energy consumption and silicon area of our system implementation are quantitatively analyzed at 180 nm node and compared with other representative neuromorphic and digital hardware systems, as summarized in Supplementary Table 4. Despite being implemented at a larger technology node (180 nm), our system demonstrates up to an order of magnitude reduction in area and notable improvements in energy efficiency, highlighting its potential for scalable and energy-efficient neuromorphic hardware integration for temporal signal processing tasks.

Discussion

We conduct a comparative analysis between the constructed neuron circuit and representative CMOS or memristor based implementations. The results indicate that the proposed memristor-based system for time-series signal processing offers improved area and energy efficiency. Specifically, the homeostatic neuron, optimized at both the device and circuit levels, attains a compact area of 76.8 μm² and ultra-low energy consumption of 19.29 pJ per spike (Supplementary Table 5). Beyond its minimal area overhead, the neuron is capable of operating at higher spiking frequencies via capacitor optimization, which offers improved trade-offs across area, speed, and energy consumption. In our design, the dendritic structure adopts a multi-synapse shared-dendrite architecture, which achieves a significant reduction in hardware overhead by multiplexing multiple inputs onto a common dendritic branch. Furthermore, by leveraging the intrinsic threshold-switching characteristics of VO₂ devices, the dendritic structure further minimizes the consumption of hardware resources (Supplementary Table 6). These results underscore the potential of VO₂ based memristive devices as a scalable and high-performance building block for future hardware neural networks. At the system level, we evaluated the hardware performance of the proposed neuromorphic network for the GSC dataset. The implementation achieves a compact area of 0.102 mm² and energy consumption of 12.9 × 10⁻⁶ J per second of speech while maintaining the classification accuracy. Compared with other representative works, our design demonstrates significant improvements in area and energy efficiency (Supplementary Table 4). Together, the single-neuron optimizations and system-level design enable a highly efficient and scalable architecture capable of performing real-time time-series processing tasks with low power consumption and compact silicon footprint.

Compared with existing ALIF models, our proposed homeostatic neuron demonstrates significant advantages, including improved accuracy and enhanced long-term stability. The benefits of the homeostatic neuron-based SNN are validated across two distinct tasks: fault diagnosis in engineered systems and speech recognition in natural environments, highlighting its generalization capability and applicability across diverse time-series processing scenarios. To evaluate the contribution of dendritic processing, we compared SNNs with and without dendritic structures on the GSC dataset. The results show that incorporating trainable delays improves network accuracy. The dendritic circuit introduces temporal shuffling by incorporating programmable delays into each input channel prior to membrane integration, enabling both spatial and temporal reorganization of input signals and enhancing the network’s ability to extract complex dynamic features more effectively. Furthermore, we conducted comprehensive experiments on the GSC dataset to evaluate the individual and combined contributions of homeostatic neurons and dendritic structures. The combined architecture achieved the highest performance, demonstrating a 3.50 percentage point improvement over the baseline and confirming the synergistic effects of these two biologically inspired mechanisms. These results highlight that homeostatic regulation and dendritic computation operate complementarily, with homeostatic neurons providing stability and adaptation while dendritic structures enhance temporal feature extraction, collectively advancing neuromorphic computing toward more energy-efficient and biologically faithful implementations.

Methods

Fabrication of vanadium dioxide devices

10 nm VO₂ thin films were epitaxially grown on c-Al₂O₃ substrates using molecular beam epitaxy. During deposition, the chamber pressure and substrate temperature were maintained at 1–3 mPa and 550 °C, respectively. Metallic vanadium was electron-beam evaporated from a vanadium powder source at a rate of 0.1 Ås-1 while oxygen was introduced at a flux of 2.5 sccm. The evaporation rate of vanadium was monitored by a crystal oscillator. The activated oxygen was provided by a radio-frequency plasma source and its flow rate was controlled by a mass flow controller. Reflective high-energy electron diffraction was used to monitor the deposition process in-situ. A final post-annealing step was carried out under a high vacuum at 300 °C for 2 h after deposition was complete. VO₂ memristors with a channel length of 300 nm and a width of 2 μm were fabricated using electron-beam lithography followed by electron-beam evaporation of 10 nm Ti and 90 nm Au and lift-off.

Preprocessing for the fault diagnosis dataset

The CWRU dataset consists of bearing vibration data collected under various fault modes and operating conditions. The data were recorded at sampling frequencies of 12 or 48 kHz, across different horsepower loads (0, 1, 2, and 3). Accelerometers placed at the 12 o’clock location on the motor housing drive end, fan end, and base captured vibrations for faults of varying diameters (0.007, 0.014, and 0.028 inches) and locations (ball, inner race, outer race). We selected the data recorded under the healthy condition as the baseline, labeled as 0. The remaining 9 categories correspond to different fault locations and sizes, such as data from a ball fault with a 0.07-inch diameter at different horsepower settings, labeled as 1, or a ball fault with a 0.14-inch diameter at different horsepower levels, labeled as 2, and so on. To increase the dataset size, the original long sequence data were converted into multiple 2¹⁴ length segments.

Preprocessing for the speech command dataset

The GSC dataset v0.02 contains 105,829 utterances from different speakers saying 35 different speech commands, and each sample consists of a 1 s audio file of a spoken English word with a sampling rate of 16 kHz. In our experiments, we adopted log Mel filters and extracted their first three derivative orders from the raw audio files by calculating the logarithm of 40 Mel filters coefficients using the Mel scale between 20 Hz and 4 kHz for pre-processing⁶⁷. Each frame of the inputs has 40 × 3 channels. The spectrograms are normalized. During the analysis, each Mel frame was assumed to remain constant over a 10 ms interval, such that one Mel frame represents the input within a single 10 ms simulation timestep. Thus, each audio sample is transformed into a sequence of 101 frames with 120 channels.

Author contributions

L.Z., T.Z., and Y.Y. designed the experiments. P.J.T. fabricated the VO₂ devices. T.Z. fabricated the 1T1R array. L.Z. and X.W. designed the circuits. L.Z. performed electrical measurements and network simulations. L.Z., T.Z., and Y.S. visualized the results. L.Z., P.J.T., and T.Z. prepared the manuscript. Y.Y. directed the research. All authors analyzed the results and implications and commented on the manuscript at all stages.

Peer review

Peer review information

Nature Communications thanks Yong Chen and the other anonymous reviewer(s) for their contribution to the peer review of this work. A peer review file is available.

Funding

This work has been supported by Supported by Guangdong S&T Program (2026B0101070006), Guangdong Provincial Key Laboratory of In-Memory Computing Chips (2024B1212020002), Shenzhen Science and Technology Program (ZDCY20250901103401002, JCYJ20241202125907011), and Beijing Natural Science Foundation (L234026, L257010). This work has been supported by the New Cornerstone Science Foundation and Financial Support for Outstanding Scientific and Technological Innovation Talents Training Fund in Shenzhen.

Data availability

All data supporting this study and its findings are available within the article and its Supplementary Information. Source data are available via Zenodo at 10.5281/zenodo.20072736 (ref. ⁶⁸).

Code availability

The codes used for simulations are available via Zenodo at 10.5281/zenodo.20073414 (ref. ⁶⁹).

Competing interests

The authors declare no competing interests.

Supplementary information

The online version contains supplementary material available at 10.1038/s41467-026-73669-x.