Integration of high-κ oxide on 2D semiconductors with carbon-dot monolayer assembly as van der Waals interfacial layer

Abstract

The atomically smooth surfaces of two-dimensional (2D) nanomaterials minimise scattering-induced carrier-transport degradation. However, this same attribute poses a major challenge for integrating 2D materials with high-quality dielectrics at sub-nanometre equivalent oxide thickness (EOT) through direct growth. Here we show that atomically thin carbon dots with diameters of a few nanometres assemble into a closely packed monolayer on 2D materials without hybridizing with the underneath graphene or molybdenum disulfide (MoS₂) channels. This atomically thin assembly forms a van der Waals interfacial layer that enables deposition of ultrathin high-κ oxides to afford a smooth, thermally stable hybrid dielectric with an EOT down to 0.6 ± 0.1 nm, leakage current density below 10⁻⁴A·cm⁻², and a breakdown field of 28 MV·cm⁻¹. Leveraging this approach, we fabricate top-gated MoS₂ transistors with a subthreshold swing approaching 60 mV·dec⁻¹, hysteresis below 30 mV, near-zero threshold voltage (V_T) for enhancement-mode operation, and excellent bias-stress stability with V_T drift under 25 mV, allowing integration into logic circuits operating at a low drive voltage of 0.5 V.

The integration of high-κ dielectric materials with 2D semiconductors remains an important challenge for the industrialization of 2D electronics. Here, the authors report the application of a carbon-dot monolayer assembly to facilitate the deposition of high-κ HfO₂ on monolayer graphene and MoS₂, enabling the fabrication of high-performance transistors.

Introduction

Two-dimensional (2D) nanomaterials, from graphene to transition-metal chalcogenides, are promising channel materials for constructing next-generation electronics. Their dangling-bond-free, atomically smooth surfaces enable fast carrier transport even at an intrinsic sub-nanometre channel thickness^1–3. In field-effect transistors, these 2D channels must be insulated from the gate electrode by a dielectric layer, whose properties critically determine device performance, power consumption, and reliability⁴. To meet targets set in the International Roadmap for Devices and Systems (IRDS)^5–7, this gate dielectric must achieve an equivalent oxide thickness (EOT) below 1 nm, leakage current density below 10⁻²A·cm⁻², and dielectric strength greater than 10 MV·cm⁻¹. This dielectric layer must also develop a stable, clean interface with 2D channels to preserve fast carrier transport for maximising output current density, ensure high gate efficiency for low-voltage operation with sharp subthreshold swing (SS), allow threshold voltage (V_T) controllability, provide operational stability under bias stress, and enable top-gated device structure for circuit integration. The chemically inert van der Waals surfaces with fully saturated bonds of 2D materials become a disadvantage here, making direct growth of high-quality gate dielectrics particularly challenging due to the lack of nucleation centres^8,9.

Two main strategies have been explored for top-gate integration of dielectrics with 2D materials. The first transfers pre-formed dielectric thin films, such as Al₂O₃, HfO₂, Y₂O₃, SrTiO₃, MgNb₂O₆, Ga₂O₃, and hexagonal-boron nitride (h-BN), from donor wafers onto 2D channels^10–21. Although this approach circumvents nucleation issues, the complex transfer process often leaves residues that cause interfacial roughness and traps, while microdefects generated during film release and stacking can lower breakdown fields (typically < 10 MV·cm⁻¹; Supplementary Table 1) and degrade device yield and reliability. The second strategy employs evaporated organic molecules, e.g., phthalocyanine and perylene-3,4,9,10-tetracarboxylic dianhydrides, or metal-oxide particles, e.g., SiO₂, Al₂O₃, HfO₂, and Sb₂O₃, as nucleation centres to promote atomic layer deposition (ALD) of high-κ oxides on 2D materials^22–26. Although producing dielectrics with higher strength in a more complementary-metal-oxide-semiconductor (CMOS) compatible fashion, these seed layers employed so far have intrinsic limitations: Organic seeds, applied via thermal evaporation, lack thickness control for achieving complete surface coverage with monolayers. They decompose or undergo phase transformation below 220 °C^27,28, far below the minimum 400 °C thermal budget required for even back-end-of-line integration. Metal-oxide seeds, grown following the Volmer-Weber mode on 2D material surfaces, produce discrete 3D island topologies that compromise uniformity and increase leakage, with their surface dangling bonds leading to typically high interfacial trap density (D_it). The formation of metal-oxide seeds by physical vapour deposition also risks physiochemical damages to underlying 2D channels^25,29. Native oxides of certain 2D materials, e.g., HfS₂ and Bi₂O₂Se, have been used as the seeding layer or dielectrics^30–32, but their use is constrained by oxidation selectivity, oxidative defect formation, and inapplicability to monolayer channels.

In this article, we demonstrate that coal-derived, graphene-like carbon dots can be assembled under mild conditions into a closely packed, uniform, and atomically thin (about 0.4 nm) monolayer that binds non‑covalently to 2D surfaces and serves as a robust seeding layer for ALD growth of smooth, ultrathin high-κ oxides. The resulting carbon dot/HfO₂ bilayer dielectric achieves an EOT down to 0.6 nm, while maintaining a low leakage current density below 10⁻⁴A·cm⁻², high breakdown field of 28 MV·cm⁻¹, and thermal stability to at least 400 ^oC, surpassing IRDS requirements⁶. Deposited at low temperature from solution dispersions, the graphene-like carbon dots form clean van der Waals interfaces between their basal plane and 2D channels, enabling top-gated graphene and molybdenum disulfide (MoS₂) transistors with high on-state current density, sharp SS down to the thermionic limit of 60 mV·dec⁻¹, and hysteresis below 30 mV. The high-quality interface without chemical hybridisation also yields near-zero, positive average V_T with a narrow distribution of 60 mV and exceptional bias-stress stability with maximum V_T drift below 25 mV. The combination of sharp transition and near-zero V_T, enabled by the sub-nanometre EOT and clean interface with MoS₂, allows construction of multi-transistor logic gates operating at a low drive voltage (V_DD) of 0.5 V. These results establish a broadly applicable and CMOS‑compatible route for integrating high‑κ dielectrics with 2D nanomaterials, addressing a central bottleneck in the development of high‑performance 2D electronics.

Results

Carbon-dot monolayer seeds and high-κ oxides on 2D channels

Figure 1a outlines the process used to form the hybrid dielectric on 2D materials. Graphene-like carbon quantum dots, derived from coal and possessing a single-layer of graphite structure, are synthesised by oxidative cutting of coal char, followed by repeated purifications to remove ionic impurities, and then functionalisation with oleylamine to produce a high-purity, stable suspension in toluene (see “Methods”)^33,34. This carbon-dot suspension is then dispersed onto a water subphase, where individual carbon dots spread spontaneously across the water surface, driven by surface tension. After toluene evaporation, lateral compression using movable barrier bars assembles the floating dots into a Langmuir monolayer through multiple isotherm cycles³⁵. This closely packed film is then horizontally transferred onto 2D materials via the Langmuir–Schaefer method, preserving the atomic flatness of the underlying 2D substrate as confirmed by atomic force microscopy (AFM) imaging after transfer onto exfoliated MoS₂ (Fig. 1b). Scanning tunnelling microscopy (STM) further confirms uniform monolayer formation under these mild conditions, with > 95% surface coverage and a predominant (> 90%) monolayer of carbon dots with a thickness of 0.4 ± 0.2 nm (Fig. 1c) and lateral dimensions of 1–5 nm (Supplementary Fig. 2). The surface area roughness of the carbon-dot monolayer is 0.13 nm as measured by STM. Unlike graphene, the assembled carbon‑dot monolayer is electrically insulating. Quantum confinement in the 1–5 nm carbon dots leads to a substantial widening of the electronic bandgap, while sp³-rich edge terminations disrupt π-conjugation and reduce inter-dot electronic coupling, thereby suppressing charge transport across the assembled monolayer. Two-terminal measurements across a 100 nm channel show currents below the measurement noise floor and indistinguishable from an open-circuit control, confirming the absence of measurable conduction and thus possible contribution to the device off-state leakage current (Supplementary Fig. 3).

Fig. 1. Formation of ultrathin carbon dot/HfO₂ hybrid dielectric on 2D materials.

a Schematic illustrating atomic layer deposition (ALD) growth of a uniform high-κ dielectric film on a dangling-bond-free MoS₂ surface, with a carbon-dot monolayer providing nucleation centres. b Atomic force microscopy (AFM) image of a carbon-dot monolayer on an exfoliated MoS₂ flake. Scale bar: 2 µm. c Height histogram of a carbon-dot monolayer on graphite, with the graphite surface defined as the zero-height reference. The red shaded area highlights about 90% monolayer coverage with about 0.1 nm roughness. Inset: Corresponding scanning tunnelling microscopy (STM) micrograph of the carbon-dot monolayer. Scale bar: 5 nm. d, e AFM images of exfoliated MoS₂ after deposition of about 1.6 nm HfO₂ with (part d) and without (part e) the carbon-dot seeding layer. White dashed lines mark the line-cut positions. Insets: line-cut height profiles showing surface roughness. Scale bars: 200 nm. f, g Cross-sectional scanning transmission electron microscopy (STEM) micrographs at low (part f, scale bar: 5 nm) and high (part g, scale bar: 1 nm) magnifications. White dashed lines serve as a visual guide to mark the interfaces. h Raman spectra of graphene before (black) and after integration with carbon dots (red) and carbon dot/HfO₂ (blue) dielectrics. i–k Raman (part i), photoluminescence (part j), and X-ray photoelectron spectroscopy (XPS, part k) spectra of MoS₂ before (black) and after integration with carbon dots (red) and carbon dot/HfO₂ (blue) dielectrics.

Vacuum annealing at 250 ^oC and 400 ^oC, compatible with back-end-of-line integration thermal budget, drives off chemisorbed water and oleylamine functionalisation. Carbonyl and amide functional groups around the carbon-dot edges act as dense, uniformly distributed nucleation sites for ALD, enabling deposition of ultrathin (down to about 1.6 nm), pin-hole-free HfO₂ films on MoS₂ (Fig. 1d and Supplementary Fig. 4) and graphene (Supplementary Fig. 5). After ALD HfO₂ growth, the resulting surfaces remain atomically flat, exhibiting a roughness of approximately 0.1 nm, comparable to the about 0.1 nm roughness of the underlying carbon-dot monolayer and indicating that the ALD process preserves the morphology of the seed layer. Compared with the STM images in Fig. 1c inset, the apparent absence of bilayer features in the AFM images (Fig. 1b, d) arises primarily from the different vertical scale contrast and measurement modalities, rather than from a change in surface morphology during dielectric deposition. In contrary, control samples without carbon-dot seeds form rough, porous HfO₂ films comprising aggregated oxide islands, likely nucleated from structural defects in the 2D materials (Fig. 1e). Samples subjected only to solvent treatment or thermal annealing likewise exhibited discontinuous, island-like HfO₂ growth (Supplementary Fig. 6), confirming that the enhanced dielectric nucleation originates from the carbon-dot monolayer rather than from process-induced MoS₂ surface modification. Cross-sectional scanning transmission electron microscopy (STEM, Fig. 1f, g), together with energy dispersive X-ray (EDX) spectroscopy mapping (Supplementary Fig. 7), confirms the formation of a smooth HfO₂ and carbon-dot bilayer on MoS₂ crystal. The interfacial carbon-dot layer atop the MoS₂ lattice is about 0.4‒0.6 nm thick, consistent with STM measurements, and facilitates homogenous growth of about 1.6 nm HfO₂ to yield an ultrathin overall EOT with good uniformity, as confirmed with high-resolution STEM analysis acquired from multiple locations (Supplementary Fig. 7).

Since the carbon-dot seeding layer is formed through a mild, solution-based process without involving energetic particles, the underlying 2D materials remain intact, with van der Waals bonding in between that minimises chemical hybridisation and suppresses interfacial traps. For graphene, Raman spectra show an increased disorder D band intensity after carbon-dot deposition, arising from carbon-dot edge rich in sp³ carbon; while the D + D″ band, which is characteristic of defected but continuous graphene, remains unchanged (Fig. 1h)³⁶. This indicates that disorders are confined to the carbon-dot monolayer. For MoS₂, the in-plane E_2g and out-of-plane A_1g Raman modes, which are sensitive to defect density through phonon‑confinement effects, show negligible change upon incorporation of the carbon‑dot layer (Fig. 1i). The densely packed carbon-dot monolayer further shields both graphene and MoS₂ from attack by reactive metal-organic precursors during ALD growth^25,37. Photoluminescence spectra also exhibit unchanged position, linewidth, and intensity of characteristic excitonic peaks A and B (Fig. 1j), confirming that integration with the hybrid dielectric does not introduce additional radiative recombination centres in MoS₂^38,39. X-ray photoelectron spectroscopy (XPS) of MoS₂ shows only a very small (<0.16 eV) Mo 3d_3/2 binding energy shift (Fig. 1k), while no measurable shift is observed in the S 2p peaks. This behaviour is consistent with a change in the local dielectric environment rather than charge-transfer doping. This shift is far smaller than the 1.1–1.3 eV shifts in both Mo 3d and S 2p peaks observed for direct ALD growth of HfO₂ on MoS₂⁴⁰. These results suggest that the interaction between the carbon-dot monolayer and MoS₂ is weak and induces negligible charge-transfer doping, consistent with a predominantly van der Waals interface⁴¹. X‑ray fluorescence (XRF) analysis performed on the wafer surface immediately after carbon‑dot monolayer deposition shows no detectable contamination (Supplementary Fig. 8), confirming that the process is compatible with CMOS fabrication requirements.

Dielectric properties evaluated with graphene transistors

To evaluate the dielectric properties of the ultrathin carbon-dot/HfO₂ bilayers grown on 2D materials, we first fabricated graphene transistors in a double-gate configuration as test structures (Fig. 2a). The 90 nm thermal oxide and heavily doped silicon substrate serve as the global back-gate stack, while the hybrid dielectric and gold metal electrode form the top-gate stack as counterpart, with monolayer graphene grown by chemical vapour deposition (CVD) sandwiched between them. The device channel width W is 1 µm, and the gate length L_g varies from 2 to 6 µm (Fig. 2b). Modulation through the top gate bias enables a low gate-voltage swing below 1 V down to ±0.5 V and small hysteresis of 15 mV (Fig. 2c, d, under scanning rate of 0.2 V·s⁻¹), both markedly reduced compared to bottom-gate control (Supplementary Fig. 9). The Dirac point remains close to 0 V, exhibiting only an about 0.1 V shift, which is far smaller than the about 1.15 V Dirac-point shift reported for graphene devices employing nanoparticle-seeded HfO₂ dielectrics⁴², indicating negligible charge-transfer doping from the carbon-dot/HfO₂ stack^43,44.

Fig. 2. Properties of the carbon dot/HfO₂ hybrid dielectric evaluated with graphene transistors.

a Schematic of the double-gate graphene transistor. S: source; D: drain; G: gate. b Scanning electron microscopy (SEM) micrograph (scale bar: 50 µm) with a false-coloured zoom-in view (scale bar: 2 µm) of the graphene transistor. c Transfer characteristics showing the change of source-drain current (I_DS) as a function of top-gate voltage (V_TG) at back-gate voltage V_BG = 0. Arrows indicate V_TG sweep direction. Applied source-drain bias (V_DS) is 0.4 V. Inset: magnified view highlighting 15 mV hysteresis. d Transfer curves measured under varying V_BG, with the curve colour gradually shifting from red to green representing the V_BG swept from − 40 to + 30 V in a step of 10 V. Applied V_DS is 0.2 V. e Top-gate Dirac-point voltage (V_Dirac,TG) of the graphene transistor test structure as a function of V_BG. The red dashed line is a linear fit to the data, yielding a slope of −0.0071 ± 0.0001, equivalent oxide thickness (EOT) of 0.64 ± 0.01 nm, and corresponding top-gate capacitance (C_TG) of 5.4 ± 0.1 µF·cm⁻². The back gate oxide is 90 nm SiO₂, providing a back-gate capacitance (C_BG) of 0.038 µF·cm⁻². f Leakage current density as a function of V_TG for hybrid dielectrics with HfO₂ thickness of 1.6 nm (black) and 3 nm (red), respectively. Applied V_DS is 0.1 V. The blue dashed line serves as a visual guide to mark the gate leakage current density limit of 10⁻²A·cm⁻² for low-power electronics. g Electric-field dependent leakage current density for hybrid dielectrics with HfO₂ thickness of 1.6 nm, showing high breakdown strength. Data from eight devices biased with both polarities are plotted together with each represented by a different colour. h Comparison of field-effect mobility in bottom-gated graphene transistors with 90 nm SiO₂ gate oxide (orange) and top-gated devices with carbon dot/HfO₂ bilayer dielectrics (green). Dotted lines are Gaussian fits to the data.

This double-gate configuration allows accurate extraction of the top-gate capacitance and EOT^{15,21,23–26}. In a double-gate configuration, the carrier density in the 2D channel is controlled simultaneously by the top-gate and back-gate capacitors. As a result, the transfer curves under top-gate bias (V_TG) modulation shifts with the applied back-gate voltage (V_BG, Fig. 2d). Quantitatively, the slope dV_TG/dV_BG gives the ratio of the back-gate (C_BG) and top-gate (C_TG) capacitances, because, in the linear regime, the induced charge must be balanced as C_TGΔV_TG = − C_BGΔV_BG to maintain the same channel conductance, for example at the Dirac-point (Fig. 2e). Since the back-gate oxide thickness (90 nm thermal SiO₂) and its EOT (90 nm, 0.038 µF cm⁻²) are known precisely, the top-gate EOT and corresponding capacitance can be determined directly from the measured slope of −0.0071 ± 0.0001. For a device with HfO₂ thickness t_ox of 1.6 nm, the extracted EOT is 0.6 ± 0.1 nm with an effective relative dielectric constant (ε_r) of 13, showing good uniformity and reproducibility (Supplementary Fig. 10). Increasing the HfO₂ thickness to 3 nm yields an EOT of 0.9–1 nm, consistent with direct capacitance-voltage measurements (Supplementary Fig. 11)⁴⁵. From EOT–t_ox scaling using 1.6 nm and 3 nm HfO₂ layers, the y‑intercept is about 0.3 nm, indicating the additional EOT introduced by the carbon‑dot seeding layer and the van der Waals interfacial gap⁴⁶. For the about 0.4 nm physical thickness of the carbon‑dot monolayer, this corresponds to a lower-bound estimate of the effective ε_r (about 5) of the carbon-dot monolayer, consistent with values reported for diamond‑like carbon materials⁴⁷. The higher ε_r of carbon dots than organic seeding layers, whose ε_r = 1.9–3.1^23,48, enables lower EOT for hybrid dielectrics of comparable thickness^22,23. The extracted ε_r of ALD HfO₂ (about 18) matches literature values⁴⁹.

Leakage current characteristics across the graphene/carbon dots/HfO₂/Au gate stack are plotted in Fig. 2f. With 3 nm HfO₂ layer (EOT ≈ 0.9–1 nm), the leakage current density stays below 10⁻⁴A·cm⁻², limited by measurement sensitivity. Reducing the HfO₂ thickness to 1.6 nm (EOT ≈ 0.6 nm) increases the leakage current, likely due to enhanced tunnelling. However, the leakage remains relatively low, at or below 10⁻⁴A cm⁻² when V_TG is swept between ± 0.5 V, which is sufficient for effective device modulation (Fig. 2d). Moreover, across the full operating gate-voltage range of ± 1 V, corresponding to a gate electric field of up to 5 MV cm⁻¹, the leakage current density remains below the 10⁻²A cm⁻² limit for low-power electronics. The breakdown voltage of 4 ± 0.8 V corresponds to a dielectric strength of 28 MV·cm⁻¹ (Fig. 2g), confirming the reliability ensured by the high dielectric and interface qualities of ultrathin HfO₂ grown on a carbon-dot seeding layer offering dense nucleation centres. The achieved effective ε_r, dielectric strength, and EOT are well-balanced and all among the best reported for top-gate dielectrics on 2D materials (Supplementary Table 1).

Thermal stability tests further show unchanged device characteristics and EOT after annealing at 400 ^oC for 10 min, with leakage current remaining well below 10⁻²A·cm⁻² and no obvious top-gate Dirac-point voltage (V_Dirac,TG) shift (Supplementary Fig. 12), confirming stability and robust interfaces across the gate stack. We performed these tests on graphene transistors because graphene–metal contacts remain comparatively stable under these annealing conditions, enabling direct evaluation of the dielectric stack. In contrast, annealing at this temperature can significantly modify the electrical properties of commonly used MoS₂–metal contacts through interfacial reactions and sulphur-vacancy formation, making it difficult to unambiguously evaluate the intrinsic thermal robustness of the gate dielectric stack.

Finally, we compare the effective mobility μ of graphene transistors operated through the bottom and top gates. Incorporation of the carbon-dot/HfO₂ top-gate dielectric enhances μ by approximately threefold on average, from 1000 ± 200 cm²V⁻¹s⁻¹ to 3200 ± 500 cm²V⁻¹s⁻¹ (Fig. 2h), with similar parasitic resistance (2R_c = 3–4 kΩ·µm) extracted using the transmission-line method (Supplementary Figs. 9, 13). The increased mobility and reduced hysteresis suggest that the formation of van der Waals interface, with structural coherence between the basal plane of the graphene-like carbon-dot monolayer and graphene channel, reduces interfacial trap density and scattering, thereby facilitating more efficient carrier transport.

MoS₂ transistors with carbon dot/HfO₂ top-gate dielectrics

We next applied the ultrathin carbon dot/HfO₂ hybrid dielectric to few-layer exfoliated MoS₂, a representative 2D semiconductor. The device structure is illustrated in Fig. 3a. To preserve high-quality MoS₂–metal contacts, which can be degraded by thermal annealing during and after ALD, we first defined SiO₂ dummy contacts on MoS₂ and replaced them with silver contacts after completing the gate stack (“contact-last” scheme; Supplementary Fig. 14 and “Methods”). To enable selective etching of the SiO₂ dummy contacts, the back-gate oxide is changed to 30‒40 nm annealed HfO₂, in contrast to the graphene transistor configuration (Fig. 2a).

Fig. 3. Transistors with ultrathin carbon dot/HfO₂ as top-gate dielectrics on exfoliated MoS₂.

a, b Schematic (part a) and false-coloured SEM image (part b, scale bar: 500 nm) of the MoS₂ transistor with carbon-dot/HfO₂ hybrid dielectrics. c Transfer characteristics of the MoS₂ transistor. Applied V_DS is 0.1 V, and V_BG is 1 V. Arrows indicate V_TG sweep direction. Red dashed line marks the fitting to extract SS. d Subthreshold swing (SS) as a function of I_DS extracted from transfer curves. Each colour represents data extracted from one device. The black dashed line marks the room-temperature thermionic limit of 60 mV·dec⁻¹. e Current-voltage characteristics with the applied V_TG decreasing from 2 to 0 V from top to bottom in 0.5 V steps. Applied V_BG is 2 V. Arrows indicate V_DS sweep direction. f Transfer curves measured at V_BG changed from 1.5 V (green) to 2 V (yellow), 2.5 V (orange), and 3 V (red) in a step of 0.5 V. Applied V_DS is 0.1 V. g Top-gate threshold voltage (V_T,TG) of the MoS₂ transistor as a function of V_BG. The red dashed line is a linear fit to the data, yielding a slope of − 0.084 ± 0.003 and C_TG of 3.9 ± 0.1 µF·cm⁻², corresponding to an EOT of approximately 0.8–0.9 nm. The physical thickness of HfO₂ (t_ox) is about 3 nm and 40 nm for top and bottom gate dielectrics, respectively. h Top-gate leakage current (I_TG) as a function of V_TG for MoS₂ transistors. Applied V_DS is 0.1 V. Each colour represents data extracted from one device. The black dashed line marks the gate leakage current density limit of 10⁻²A·cm⁻² for low-power electronics.

The completed devices have W and channel length (L_ch) of about 1 µm, determined by both lithography and MoS₂ flake size (Fig. 3b). The transistors exhibit SS below 90 mV·dec⁻¹ with hysteresis of 26 mV at I_DS of 1 nA (Fig. 3c), and the minimum SS approaches the Boltzmann limit of 60 mV·dec⁻¹ (Fig. 3d), consistent with the clean van der Waals interface between MoS₂ and the carbon-dot monolayer. Output characteristics show linear behaviour at low bias with high normalised channel conductivity (σ_on = I_DS/V_DS× L/W) of 26 µS, enabled by both the high-quality MoS₂–dielectric interface and the pristine ohmic MoS₂–Ag contact formed through the contact‑last process (Fig. 3e). At higher bias, the devices exhibit clear current saturation with output current density reaching 23 µA·µm⁻¹. As in graphene transistors, applying V_BG shifts the threshold voltage under top-gate modulations (V_T,TG, Fig. 3f), and the slope of this correlation corresponds to a consistent top-gate EOT of about 0.8‒0.9 nm for t_ox = 3 nm (Fig. 3g).

For these top-gated MoS₂ transistors with sub-nanometre EOT, the top‑gate leakage current remains below the detection limit across the normal operation voltage range of V_TG to 1 V, giving an upper bound of 10⁻⁴A·cm⁻². Even under a high gate bias of 2 V, top-gate leakage remains below the low-power limit of 10⁻²A·cm⁻² (Fig. 3h). All these performance metrics are among the best reported for top-gated MoS₂ transistors, while avoiding many limitations of established dielectric‑integration methods (Supplementary Table 1).

Beyond exfoliated MoS₂ flakes, the ultrathin carbon-dot/HfO₂ hybrid dielectric (t_ox = 3 nm) is also compatible with large-area monolayer MoS₂ grown by CVD on sapphire and transferred to the same HfO₂/silicon substrate, enabling scalable fabrication of top-gated MoS₂ transistor arrays with > 90% yield (no gate failure). These devices exhibit performance comparable to exfoliated MoS₂, with hysteresis of 24‒29 mV (Fig. 4a), substantially smaller than that of back-gate modulation through 40 nm HfO₂, and consistently maintained across different V_DS applied from 0.4‒1 V (Supplementary Fig. 15). One possible origin of the even smaller hysteresis observed in CVD-grown MoS₂ devices is differences in surface condition arising from the transfer process. The CVD monolayer was protected by a poly(methyl methacrylate) (PMMA) support layer during transfer, whereas exfoliated MoS₂ flakes were directly exposed to Scotch‑tape adhesives, which can leave hard-to-remove polymeric residues that introduce interfacial trap states prior to top-gate dielectric integration. This difference in initial surface condition may contribute to the reduced hysteresis observed in the CVD-MoS₂ devices despite their comparatively lower crystalline quality, consistent with the trend observed in bottom-gated control devices prior to top-gate dielectric integration (Supplementary Fig. 15).

Fig. 4. Transistors with ultrathin carbon dot/HfO₂ as top-gate dielectrics on chemical vapour deposition (CVD)-grown monolayer MoS₂.

a Transfer characteristics of a representative CVD-MoS₂ transistor (channel width W and channel length L_ch are both 1 µm). Applied V_DS varies from 0.4 V (black) to 0.7 V (red), and 1 V (blue) and V_BG is 1 V. Arrows indicate V_TG sweep direction. Inset: magnified view highlighting hysteresis up to 29 mV at I_DS = 1 nA. b Collection of transfer curves of 28 transistors in the array. Applied V_DS is 0.4 V. c SS as a function of I_DS extracted from transfer curves. Each colour represents data extracted from one device. d Variation of SS across 28 transistors extracted from an I_DS modulation range from 10⁻¹¹ to 10⁻⁸A. e Power spectral density (PSD) as a function of frequency for interfacial trap density (D_it) extraction, measured under applied V_TG of − 50 mV (green), 0 V (yellow), 50 mV (orange), and 100 mV (red) in the subthreshold region. f‒h Histograms showing the distributions of V_T,TG (part f), on/off ratio (part g), and device on-state current (I_on, part h). The red dashed lines represent Gaussian fits to the data. i, j Positive bias stress (PBS, part i) and negative bias stress (NBS, part j) measurements over 2 h top-gate stress bias (V_TG,Bias) of ±1 V and source-drain stress bias (V_DS,Bias) of 0 V. The silicon substrate (V_BG) was grounded. The curve colour gradually shifts from green to red, representing the bias stress time from 0 s to 2 hours. k Corresponding shift of the top-gate threshold voltage (ΔV_T,TG) as a function of stress time for PBS (black) and NBS (red) tests, with data connected with basis spline curves. l Transfer curves of a representative top-gated MoS₂ measured continuously over 100 sweeping cycles, showing negligible change in electrical characteristics and excellent operational stability. Each colour corresponds to data from a single V_TG sweeping cycle.

Across 28 devices fabricated, transfer curves show on/off ratios up to 10⁸ (Fig. 4b). Minimum SS reaches 60 mV·dec⁻¹ (Fig. 4c). Most devices exhibit an SS below 140 mV·dec⁻¹, with an average of 120 ± 20 mV·dec⁻¹ (Fig. 4d). The SS was extracted from the linear region of the semi-logarithmic transfer curve over an I_DS range of 10⁻¹¹–10⁻⁸A, which lies well above the measurement noise floor (about 10⁻¹³A) while remaining below the device on-state current range of 10⁻⁷–10⁻⁶A (Fig. 4d). Extending the fitting range above 10⁻⁸A inevitably incorporates data outside the subthreshold region, resulting in a deviation from the linear subthreshold transfer characteristic and higher SS values. We determined the interface trap density D_it = 4 ± 1 × 10¹²eV⁻¹cm⁻² by the 1/f noise method (Fig. 4e)⁵⁰. This value is approximately 3–10× lower than values typically reported for MoS₂/HfO₂ interfaces formed using conventional metal-oxide seeding layers (1‒4 × 10¹³eV⁻¹cm⁻²)⁵¹ and approximately six times lower than the D_it measured in our back-gated control devices (2.6 × 10¹³eV⁻¹cm⁻², Supplementary Fig. 15). It is comparable to the values reported for MoS₂ interfaced with transferred single-crystalline SrTiO₃ (4.3 × 10¹²eV⁻¹cm⁻²)¹⁰ and MoS₂ devices employing van der Waals organic seeding layers (around 10¹²eV⁻¹cm⁻²)²³, consistent with the observed small hysteresis and sharp SS.

V_T,TG, extracted using the constant off-current method at I_off of 0.1 nA·µm⁻¹ are positive and near-zero on average, with a narrow distribution of 0.02 ± 0.06 V (Fig. 4f). This indicates the absence of unintentional doping and corroborates the suppression of chemical interactions and trap formation at the van der Waals interface with the carbon-dot monolayer⁵². In contrast, most previously reported top-gated MoS₂ transistors, except those using h-BN with van der Waals interface¹⁹, exhibit negative V_T,TG (Supplementary Table 1)^{11–17,20–26,30}. The median off-state current density at zero top-gate bias is 0.07 nA·µm⁻¹, meeting the IRDS target of < 0.1 nA·µm⁻¹ for low-power devices. Thinner HfO₂ layers can produce devices with an EOT of approximately 0.6 nm (Supplementary Fig. 16), while maintaining excellent transistor characteristics, including hysteresis ΔV_T = 26 mV, an on/off ratio exceeding 10⁵, and SS below 90 mV·dec⁻¹. However, these devices exhibit a significantly higher gate-failure probability, indicating that further EOT scaling provides only modest performance gains while reducing device yield.

The statistical distributions of the device on/off current ratios and on-state current I_on are shown in Fig. 4g, h, respectively. They are statistically comparable to state‑of‑the‑art MoS₂ transistors with thin EOT employing transferred dielectrics or metal-oxide seeding layers (Supplementary Table 2), indicating the excellent channel–dielectric interface quality and strong gate electrostatic control enabled by carbon-dot/HfO₂ nanodielectrics. Unlike graphene transistors, top-gated MoS₂ devices exhibit lower apparent $\mu$ and average I_on than the corresponding bottom-gated devices (Supplementary Fig. 17), despite substantially lower D_it. This behaviour is commonly observed in top-gated MoS₂ transistors and is primarily attributed to parasitic contact resistance arising from ungated source/drain access regions and the lack of electrostatic modulation beneath the metal contacts^53,54. Consequently, the extracted $\mu$ in the top-gated configuration is strongly influenced by series resistance. Therefore, the lower extracted mobility should not be interpreted as evidence of a degraded channel–dielectric interface. This behaviour contrasts with graphene devices, where the influence of contact resistance on the extracted $\mu$ is generally less pronounced because graphene lacks a bandgap and is generally less susceptible to contact-resistance-limited transport.

V_T drift under gate-bias stress is a critical metric for device reliability and often attributed to charge trapping at the channel–dielectric interface⁵⁵. We subjected top-gated MoS₂ transistors with carbon dot/HfO₂ hybrid dielectrics to continuous positive (PBS, Fig. 4i) and negative (NBS, Fig. 4j) bias stress with a high stress field exceeding 3 MV·cm⁻¹. Remarkably, V_T drift (ΔV_T,TG) remains smaller than 25 mV (Fig. 4k), which is over 30 times smaller than in back-gated MoS₂ transistors we fabricated (Supplementary Fig. 18) and 10 times smaller than MoS₂ transistors employing non van der Waals seeding layers such as SiO₂⁵⁶. The direction of ΔV_T,TG suggests that the instability is likely related to migration of protons, which is intrinsically present in ALD-grown HfO₂, rather than electron trapping at the MoS₂–dielectric interface, which is in contrary to bottom-gated counterparts (Supplementary Fig. 18)⁵⁷. Repeated sweeping of the transistor for 100 cycles exhibited minimum performance fluctuations with the standard deviation of V_T,TG less than 8 mV and no observable drift in SS, hysteresis, or on‑current (Fig. 4l), further demonstrating the excellent stability and reliability of the device and dielectric.

Integrated logic circuits operating at low drive voltage

For integrated circuits, the IRDS roadmap demands reducing the V_DD to 0.6 V by 2031 for lower power consumption. Achieving such low‑voltage operation requires not only sharp SS and sub-nanometre EOT, but also a positive V_T to suppress leakage current at zero gate bias⁵⁸. The high yield of CVD MoS₂ transistors incorporating ultrathin carbon dot/HfO₂ hybrid dielectric enables connection of these individual transistors operating in the desired enhancement mode into functional low-voltage circuits. Using three transistors, we fabricated an enhancement-load inverter (Fig. 5a), where two drive transistors were placed in parallel to provide an effective width ratio (W_D/W_L) of 2 between drive and load transistors (Fig. 5b). Under V_DD of 0.5 V, the voltage transfer curve shows a switching threshold voltage V_M near 0.24 V ($\left[V_{\mathrm{DD}}-V_T+V_{\mathrm{T}}\left(1+\sqrt{W_{\mathrm{D}}/W_{\mathrm{L}}}\right)\right]/1+\sqrt{W_{\mathrm{D}}/W_{\mathrm{L}}}=0.22\mathrm{V}$ expected) and a voltage gain of 1.75 V/V ($\sqrt{W_{\mathrm{D}}/W_{\mathrm{L}}}=1.41\mathrm{V}/\mathrm{V}$ expected), confirming proper low-voltage operation (Fig. 5c). Compared with representative state-of-the-art MoS₂ inverters employing thin-EOT gate dielectrics, our inverter demonstrates three key advantages: operation at an ultralow supply voltage of V_DD = 0.5 V, enhancement-mode logic enabled by the positive near-zero V_T of the MoS₂ transistors, and therefore a well-centred switching threshold of V_M ≈ 0.24 V, corresponding to V_M/V_DD = 0.48. The latter is close to the ideal value of 0.5 and is substantially improved compared with previously reported depletion-mode MoS₂ inverters, whose negative transistor V_T results in typically negative V_M substantially displaced away from the optimal logic operating point (Supplementary Table 3). These results demonstrate that the carbon-dot/HfO₂ dielectric simultaneously enables strong electrostatic control and favourable V_T engineering, translating directly into improved circuit-level functionality. We further realised a NOR gate comprising five transistors (Fig. 5d), which also successfully performs the intended logic functions at V_DD of 0.5 V (Fig. 5e), while individual transistors can withstand a much higher V_DD ≥ 1.5 V (Fig. 3e). These results demonstrate that the carbon-dot/HfO₂ nanodielectric enables robust low-voltage enhancement-mode 2D logic circuits.

Fig. 5. Logic circuits comprising top-gated, enhancement-mode MoS₂ transistors with ultrathin carbon dot/HfO₂ dielectrics.

a, b Optical micrograph (part a) and circuit diagram (part b) of the inverter. c Voltage transfer characteristics (left axis, black) and the associated voltage gain (right axis, red) of the inverter. d Optical micrograph of the NOR gate. e Input-output characteristics of the NOR gate. logic (00): black; (01): red; (10): blue; (11): green. Inset: NOR gate circuit diagram. Scale bars: 50 µm. V_DD: drive voltage; GND: ground; V_in: input voltage; V_out: output voltage; V_A: input voltage A; V_B: input voltage B.

Discussion

We have demonstrated using an assembled monolayer of carbon quantum dots as an atomically thin, uniform seeding layer for the growth of high-quality top-gate dielectrics on 2D materials with a clean interface. The carbon dot/HfO₂ gate dielectric achieves an effective ε_r > 12, sub-nanometre EOT, a breakdown field of 28 MV·cm⁻¹, and low leakage current density below 10⁻⁴A·cm⁻². Top-gated graphene and MoS₂ transistors incorporating this hybrid dielectric exhibit hysteresis < 30 mV, with MoS₂ devices showing a high normalised on-state channel conductivity of 26 µS and graphene devices achieving field-effect mobility exceeding 3000 cm²V⁻¹s⁻¹. MoS₂ transistors further show sharp SS approaching 60 mV·dec⁻¹, on/off ratio up to 10⁸, near-zero V_T, and excellent bias-stress stability with V_T drift < 25 mV, enabling integration into logic circuits operating under a low V_DD of 0.5 V. This method provides an attractive solution to the long‑standing challenge of integrating ultrathin, high‑κ dielectrics with 2D semiconductors, particularly given that carbon nanomaterials have been proven compatible with commercial CMOS foundry⁵⁹.

Methods

Synthesis of coal-derived carbon quantum dots

Carbon quantum dots were synthesised by oxidative cutting of Blue Gem coal char using a mixture of concentrated sulfuric and nitric acids³⁴. Blue Gem coal char was first ground into fine powder, and 5 g of the char powder was added to 200 mL of concentrated H₂SO₄ (95‒98%) and HNO₃ (70%) in a 3:1 volume ratio under stirring. The mixture was heated at 105 °C for 24 h, yielding a brown-red solution. After cooling to room temperature, the solution was diluted to 3 L with deionised water and neutralised with 5 mol·L⁻¹ NaOH to pH around 12. To isolate the carbon dots with desired diameter of 1‒5 nm, the dispersion was purified by tangential crossflow ultrafiltration (Spectrum® KR2i/ KMPi TFF Systems, Repligen). The solution passing through a 50 kilo Dalton (kDa) filtration membrane was collected, diluted to 4 L with deionized water, and diafiltrated using tangential crossflow ultrafiltration again through a 3 kDa membrane for three times to remove soluble Na₂SO₄ and NaNO₃ salts. The resulting solution was acidified with 2 mol·L⁻¹ HCl to pH around 2, diluted with deionized water to 4 L, and diafiltrated three additional times with a 3 kDa membrane for ion exchange/protonation, converting carboxylate functional groups (–COO⁻Na⁺) on the edges of carbon dots to carboxylic groups (–COOH), which are required for subsequent amine functionalisation via amidation. Excess HCl was removed by three further diafiltration cycles. The final product was a stable aqueous dispersion of coal-derived carbon quantum dots with a typical yield of about 12 wt% and concentration of about 2 mg·mL⁻¹.

Functionalisation of coal-derived carbon dot with oleylamine

To functionalise the as-synthesised carbon dots dispersed in water, 200 mg of oleylamine dissolved in 10 mL ethanol was added to a 100 mL aqueous solution of 1 mg·mL⁻¹ carbon quantum dots under vigorous mixing (oleylamine to carbon dot ratio of 2:1 by weight). The mixture was then heated to 80 °C under magnetic stirring for 2 h on a hotplate. After cooling, the mixture was vacuum filtered through a 1 µm membrane, and the collected solids were washed and baked at 130 °C for 1 h to drive the amidation reaction to completion. The functionalised carbon dots were dispersed in a mixture of toluene and ethanol (toluene to ethanol volume ratio of 20:1) at a final concentration of 4 mg·mL⁻¹. Specifically, 84 mg of functionalised carbon dots was added to a mixture of 5 mL toluene and 1 mL ethanol and manually shaken for 3 min to disperse the solids. Additional toluene was subsequently added in 5 mL increments, with manual shaking for 3 min after each addition. Toluene was then added in 5 mL increments, with 3 min shaking after each addition, until a final volume of 21 mL was reached, yielding a stable dispersion.

Langmuir-Schaefer assembly of carbon-dot monolayer

A 100 µL aliquot of prepared carbon-dot suspension with a concentration of 0.02 mg·mL⁻¹ was dispersed dropwise onto the water surface of a Langmuir trough (Biolin Scientific KSV Nima KN 2002). After 15 min to allow complete evaporation of the organic solvent, the carbon dots floating at the water-air interface were compressed at a rate of 5 mm per min through multiple isotherm cycles until a solid‑like, incompressible monolayer was formed, as evident from the surface‑pressure isotherm curve (Supplementary Fig. 1). Surface tension during compression was monitored using a Wilhelmy paper plate. The assembled carbon-dot monolayer was then horizontally transferred onto wafers carrying 2D materials using the Langmuir-Schaefer method. Compared with vertical transfer or the Langmuir-Blodgett method, horizontal transfer yielded a cleaner interface with 2D materials without trapping water. The transferred films were vacuum annealed at 250 ^oC overnight at a base pressure of 10⁻⁵ torr to remove the adsorbed water, followed by annealing at 400 ^oC to eliminate residual surfactants.

STM characterisation of the carbon-dot assembly

STM measurements were performed using an integrated surface analysis system built by Omicron Nanotechnology GmbH at 77 K with a bias voltage of + 1.0 V. We used highly oriented pyrolytic graphite (HOPG) as the substrate, and carbon dots were deposited on top of its graphene surface. Prior to imaging, the sample was cleaned by annealing at 400 K in vacuum to remove adsorbed contaminants.

ALD growth of HfO₂

HfO₂ films were deposited with a Savannah S100 hot-wall benchtop ALD reactor from Cambridge Nanotech, using tetrakis(dimethylamido)hafnium (TDMAHf) and water vapour as precursors. The substrate temperature was maintained at 250 °C with nitrogen as the carrier gas. TDMAHf and H₂O pulse durations were 300 ms and 50 ms, respectively, each followed by a 60 s nitrogen purge. Film thickness was controlled by varying the number of ALD deposition cycles and verified using both AFM and ellipsometry.

Cross-sectional STEM characterisations

Cross-sectional specimens of the carbon dot/HfO₂ hybrid dielectric on exfoliated MoS₂ flakes were prepared using a Thermo Scios2 Dual-Beam SEM/focused-ion beam (SEM/FIB), with a 10 nm electron-beam evaporated aluminium layer serving as surface protection. STEM cross-sectional micrographs were acquired with a FEI Themis Z analytical TEM/STEM equipped with a high brightness Schottky field-emission electron source operating at 300 kV. Images were collected using a high-angle annular dark-field (HAADF) STEM detector with a beam convergence angle of 18 mrad and a camera length of 115 mm.

Graphene device fabrication and characterisation

Monolayer graphene grown by CVD on copper foils was transferred onto 90 nm SiO₂/Si wafer substrates with predefined alignment marks. Source and drain electrodes were patterned by lithography and metal lift-off, using 0.2 nm Ti/20 nm Pd/10 nm Au deposited by electron-beam evaporation (Temescal) as the contact stack. A second lithography step defined a photoresist mask over the active channel of each device. Oxygen plasma etching removed graphene in unprotected areas, providing device isolation and defining device W. The photoresist was then stripped by soaking the substrate in acetone. After deposition of the carbon-dot monolayer and ALD HfO₂, an additional lithography step wrote the gate pattern into the photoresist with precise alignment to the source and drain electrodes. Electron-beam evaporation of 0.2 nm Cr/40 nm Au, followed by lift-off in acetone, formed the gate metal. For graphene transistors, the total resistance R_T was modelled as

$$R_T=2R_c+\frac{L_g}{We\mu \sqrt{n_0^2+n^2}}$$ 1

where 2R_c is the contact resistance, e is the elementary charge, n₀ and n are the residual and induced carrier concentration, respectively. n is related to the gate dielectric capacitance C_g by

$$V_g-V_{Dirac}=\frac{e}{C_g}n+\frac{\hslash v_F\sqrt{\pi n}}{e}$$ 2

where ℏ is the reduced Planck constant and v_F ∼ 10⁸cm·s⁻¹ is the Fermi velocity of carriers in graphene. The µ and n were extracted by curve fitting following established procedures⁶⁰.

Exfoliated MoS₂ device fabrication with contact-last scheme

The process is schematically illustrated in Supplementary Fig. 14a. A 30‒40 nm HfO₂ layer was first grown by ALD on heavily doped silicon substrates and annealed at 600 ^oC in forming gas to enhance resistance against buffered oxide etchant (BOE). Few-layer MoS₂ flakes were exfoliated from bulk crystals and transferred onto HfO₂/Si wafer substrates with predefined alignment marks. After transfer, samples were annealed in vacuum (pressure about 10⁻⁵Torr) at 250 ^oC overnight to remove adsorbed water, followed by annealing at 400 ^oC in nitrogen to remove organic residues. Device contact patterns were written into PMMA A4 photoresist by electron-beam lithography, followed by electron-beam evaporation (Temescal) of 15 nm SiO₂. Lift-off in acetone formed SiO₂ dummy contacts. After Langmuir–Schaefer deposition of the carbon-dot monolayer assembly, HfO₂ was grown by ALD. Another electron-beam lithography then wrote the gate pattern into the PMMA photoresist, and blanket electron-beam evaporation of 0.4 nm Cr/50 nm Au formed the top-gate electrode after lift-off. A final lithography step defined the source-drain contact openings into PMMA photoresist. An inductively coupled plasma reactive-ion etching (ICP-RIE) performed with a chamber pressure of 5 mTorr, 5 s.c.c.m. flow of argon, and 10 s.c.c.m. flow of CHF₃ under ICP and RIE power of 300 and 200 W, respectively, etched away the carbon dot/HfO₂ hybrid dielectric above the SiO₂ dummy contacts. The exposed SiO₂ dummy contacts were then removed with 1:6 BOE, stopping cleanly on MoS₂ without affecting the structural integrity of the 2D semiconductor (Supplementary Fig. 14b). After drying, 50 nm Ag was deposited by sputtering. Lift-off in acetone formed the final source-drain contacts, completing MoS₂ device fabrication. The silver contacts were intentionally recessed by about 50 nm relative to the dummy contacts while maintaining similar line-edge roughness (Supplementary Fig. 14c, d). The SiO₂ dummy contacts protected the MoS₂ surface and enabled MoS₂‒Ag contacts to be formed only after gate-stack growth, thereby avoiding thermal or chemical damage.

CVD MoS₂ device fabrication

High-quality monolayer MoS₂ was grown on sapphire by CVD. A PMMA layer was spin-cast on top to provide mechanical support. The PMMA/MoS₂ bilayer was released by etching in aqueous ammonia at 80 ^oC, then transferred onto HfO₂/Si substrates. Adhesion and flatness were improved by annealing at 120 ^oC for 30 min after transfer. PMMA was removed by soaking in hot (60 ^oC) acetone for one hour, followed by annealing in nitrogen at 300 ^oC for 10 min. Isolation patterns were written by photolithography in photoresist, protecting the transistor channel regions and defining device W. Oxygen RIE, performed with a chamber pressure of 200 mTorr sustained by 20 s.c.c.m. flow of oxygen at 150 W for 35 s, removed MoS₂ in exposed regions. After stripping the photoresist, device fabrication proceeded identically to the exfoliated MoS₂ transistors. For scalability to large-area CVD MoS₂, carbon-dot monolayers were also formed by spin casting. A carbon-dot dispersion in toluene was diluted to a concentration of 0.1 mg·mL⁻¹, dispensed onto the substrate, and spin-cast at 3000 r.p.m. for 60 s, followed by annealing in nitrogen at 120 ^oC for 10 min and 400 ^oC for 10 min.

Instrumentation

AFM topography was obtained using an Asylum Research Cypher AFM in tapping mode with S-Tap300Al tapping tips from BudgetSensors. SEM micrographs were acquired using a Hitachi S4800 microscope. Raman and photoluminescence spectra were collected using a Nanophoton Raman 11 high-resolution confocal Raman/photoluminescence microscope under 532 nm laser excitation. XPS spectra were obtained with a PHI VersaProbe III instrument. The energy scale of the XPS spectra was calibrated by setting the 1 s line O from the SiO₂ substrate at 533 eV. XRF spectrum was acquired using a Shimadzu EDX-7000 energy-dispersive X-ray fluorescence spectrometer with a non-monochromatic rhodium X-ray source up to 50 kV under a helium environment, and the results were analysed with Rigaku semi-quantitative analysis (SQX) programme using the fundamental parameter method. Direct-current and capacitance-voltage measurements were performed using a manual probe station (LakeShore Cryotronics CRX–6.5 K) connected with a semiconductor parameter analyser (Keysight B1500A), which is equipped with integrated high-resolution source-measurement units (Keysight B1517A) and a multi-frequency capacitance-measurement unit (Keysight B1520A). Ellipsometry spectra were recorded using a J.A. Woollam VASE ellipsometer. Photoresist (PMMA or AZ 5214) was patterned with either an Elionix ELS-G150 150 keV electron-beam lithography system or a Heidelberg MLA150 aligner,

Author contributions

Q.C. and C.M. conceived the ideas and supervised the project. S.W., F.A. and Y.W. performed the device fabrications and characterisations. C.W. and R.L.T. synthesised the carbon dots. V.H.P. improved the synthesis and processing of carbon dots. Y.L. and Y.G. carried out carbon-dot characterisations. F.A., K.Y., H.H. and J.Z. performed cross-sectional STEM characterisations. J.L. performed the STM characterisations. Y.L. performed the XPS measurement. S.W., F.A., C.W., V.H.P., R.LT. and Q.C. wrote the manuscript. All authors discussed the results and commented on the manuscript.

Peer review

Peer review information

Nature Communications thanks Congwei Tan and the other anonymous reviewer(s) for their contribution to the peer review of this work. A peer review file is available.

Funding

This project was funded by the U.S. Department of Energy (DOE), National Energy Technology Laboratory, in part, through a site support contract and U.S. National Science Foundation grants 2139185 and 2231625. Significant aspects of the material characterisations and device fabrications were performed using the shared user facilities of the University of Illinois Seitz Materials Research Laboratory and Holonyak Micro and Nanotechnology Laboratory. Work performed at the Centre for Nanoscale Materials, a U.S. Department of Energy Office of Science User Facility, was supported by the U.S. DOE, Office of Basic Energy Sciences, under Contract No. DE-AC02-06CH11357. F.A. acknowledges the support of the PPG-MRL Graduate Research Assistantship programme.

Data availability

The Source Data underlying the figures of this study are available with the paper. All raw data generated during the current study are available from the corresponding authors upon request. Source data are provided in this paper.

Competing interests

The authors declare no competing interests.

Supplementary information

The online version contains supplementary material available at https://doi.org/10.1038/s41467-026-78053-3.