Gate-level three-dimensional integration of two-dimensional logic cells

Abstract

Monolithic three-dimensional (M3D) integration is a promising strategy to increase logic density within a limited footprint. Conventional M3D circuits rely on transistor-level partitioning, in which logic functions are constructed through interconnections among numerous transistors across different tiers, limiting circuit compactness. Here, we propose a gate-level M3D integration architecture based on two-dimensional (2D) logic cells (LCs), in which the basic interlayer connection unit is shifted from an individual transistor to a logic gate. Through multidimensional modulation of carrier transport in the WSe₂ channel, LCs can realize eight distinct logic functions, markedly expanding the functional reconfigurability of 2D logic devices. Building on this architecture, we experimentally demonstrate stacking of two-tier LCs, realizing complex 3D logic circuits with unprecedented compactness. Across all demonstrated logic functions, only 4 devices are required, whereas a conventional CMOS design would require 79 transistors. This gate-level M3D integration provides a scalable pathway for constructing highly compact and multifunctional electronics.

Monolithic three-dimensional integration can raise logic density, but transistor-level connections limit circuit compactness. Zhao et al stacked reconfigurable two-dimensional logic cells at the gate level, creating complex circuits with markedly fewer devices.

Introduction

Increasing the logic density of integrated circuits has long been a central driver of semiconductor technology^1,2. As planar silicon transistors approach their physical limits, the traditional planar scaling strategy is encountering fundamental bottlenecks^3,4. Three-dimensional (3D) integration offers a promising pathway to enhance logic density by stacking functional layers vertically, enabling compact layouts and increased logic density^5–7. Among existing approaches, through-silicon via (TSV) technology is currently the prevailing method for vertically interconnecting planar circuits, thereby boosting the logic density^8,9. However, the micron-scale dimensions of TSVs introduce a non-negligible silicon footprint and routing overhead, which hinder further optimization of circuit area and logic density. Despite extensive optimization efforts, the footprint of a typical TSV remains nearly five times larger than that of a standard logic unit, resulting in a TSV-induced area overhead of 15%–30% at the chip level^10–12. Therefore, the potential of TSVs to improve logic density remains fundamentally constrained.

Monolithic three-dimensional (M3D) integration, which vertically stacks devices on the same wafer using inter-metal vias, provides a more compact route toward high-density logic integration^13–15. Nevertheless, conventional silicon-based M3D processes often exceed thermal budget limits, deteriorating the performance of the underlying devices^16,17. Two-dimensional (2D) semiconductors, owing to their atomic thinness and low-temperature processes, have emerged as promising candidates for M3D integration^18–20. As shown in Fig. 1a, complementary field-effect transistors (CFETs) reduce the circuit footprint by vertically stacking different tiers of p-type and n-type transistors^21,22. However, current M3D circuits still follow a transistor-level integration paradigm inherited from silicon technology^20,23. In this paradigm, the basic integration unit remains the individual transistor, so the logic functions must be composed of multiple unipolar transistors^24,25. In addition, performance asymmetry between p-type and n-type transistors necessitates area compensation, while complex logic functions still demand multiple devices and interconnection²⁶. While stacking multiple layers of 2D circuits can enhance logic density, cumulative fabrication imperfections in multilayer circuits lead to exponential performance degradation²⁷. These challenges suggest that simply stacking more transistor layers is not sufficient to fully exploit the density potential of M3D integration.

Fig. 1. Design and concept of the gate-level integration.

a Transistor-level integration based on complementary field-effect transistors (CFET). In CFET-based architectures, n- and p-type transistors are vertically stacked, and logic gates are constructed by interconnecting multiple individual transistors across tiers. b Gate-level 3D integration based on logic cells (LC). This architecture shifts the basic interlayer connection unit from an individual transistor to a multifunctional LC, allowing vertically stacked logic-function units to be interconnected at the circuit level. c Comparison of logic function based on CFET and LC. CFET architectures primarily form complementary transistor pairs such as inverters, whereas LCs directly embed multiple Boolean functions, including NAND, OR, XNOR, and half-adder operations.

Here, we propose a gate-level M3D integration architecture based on multi-gated WSe₂ logic cells (LCs), as shown in Fig. 1b. In this architecture, Boolean operations are mapped within individual LCs through multi-gate electrostatic modulation, and different LCs are then vertically arranged and interconnected to construct 3D logic circuits. This design shifts the basic interlayer connection unit from an individual transistor to a logic gate. Multi-gate LCs provide an effective implementation route for this concept because a single LC can replace a conventional multi-transistor network for specific Boolean functions, thereby reducing device count and local interconnection complexity while enabling compact circuit layouts and enhanced logic density (Fig. 1c and Supplementary Fig. 1). This strategy shifts M3D integration from transistor stacking to logic-function stacking, providing a scalable design paradigm for compact, logic-dense, and multifunctional electronic systems.

Results and discussion

Fabrication of LC-based gate-level 3D circuit

Figure 2a illustrates a three-dimensional schematic of the two-tier WSe₂-based LC arrays. To preserve the electrical characteristics of the underlying tier, all processing steps were performed below 180 °C, avoiding high-temperature or aggressive processes directly applied to the 2D semiconductor. The detailed process flow is outlined in Supplementary Fig. 2 and “Methods”. Briefly, local bottom gates were first patterned, followed by sequential deposition of HfO₂ and Sb₂O₃ dielectrics for the 1st-tier logic cell. Few-layer WSe₂ was then transferred and patterned as the channel, followed by source/drain electrode and top-gate deposition. The 2nd-tier logic cell was subsequently constructed through repeated dielectric, channel, and gate formation, followed by via-hole etching and interconnect metallization. The corresponding device optical image is shown in Supplementary Fig. 3.

Fig. 2. Structural and electrical characterization of vertically stacked LCs.

a Schematic diagram of the fabricated two-tier 3D LCs array. b Scanning electron microscopy images of the two-tier 3D LCs. The two-tier devices share the same middle gate (MG) and source electrode (S). The polarity-source gate (PS) and polarity-drain gate (PD) are located near the source and drain contact regions, respectively. D, BG and TG denote the drain electrode, bottom gate and top gate, respectively. c Cross-sectional scanning transmission electron microscopy image of the stacked device. Bottom: enlarged image with corresponding energy dispersive spectroscopy showing the 1st-tier channel encapsulated between two dielectric layers. d, e Reconfigurable N-type (d) and P-type (e) transport characteristics of 1st- and 2nd-tier LCs. f–h Statistical summary of threshold voltage (f), on-state current (g), and on-off ratio (h) for 1st-tier, 2nd-tier, and planar LCs. Boxes represent the interquartile range, with the center line indicating the median and the box limits indicating the 25th and 75th percentiles. Filled circles denote mean values extracted from 27 devices, and whiskers indicate the 10th–90th percentile range.

The enlarged top-view false-colored scanning electron microscopy (SEM) of the gate-level 3D circuit with two tiers is shown in Fig. 2b. The channel material used is a few-layer WSe₂, with detailed structural and spectroscopic characterizations provided in Supplementary Fig. 4. The LC adopts a vertically multi-gated structure that combines channel control and polarity control within a compact footprint. The additional polarity gates, located primarily in the source and drain contact region (PS and PD gates), modulate the carrier injection barriers and enable reversible switching between electron- and hole-dominated transport. The vertical control gates (CG) regulate carrier concentration in the main channel and determine the on/off state of the device. In the two-tier structure, the top gate (TG) and middle gate (MG) are used as control gates for the 2nd-tier LC, and the bottom gate (BG) and MG are used as control gates for the 1st-tier LC. The shared MG serves as the common control electrode, simplifying inter-tier signal routing and enabling synchronized modulation of the stacked logic cells. When combined with the polarity gate, the LC supports switching between transistor and logic gate modes.

To characterize the interface performance, the channel region was sectioned along the red line in Fig. 2b using focused ion beam milling. The resulting cross sections were then examined via aberration-corrected scanning transmission electron microscopy (STEM), as shown in Fig. 2c. The image clearly shows each layer of the gate electrode, dielectric stack, and WSe₂ channel, all exhibiting clean and high-quality interfaces. Supplementary Fig. 5 provides additional STEM characterization. The enlarged STEM image and energy dispersive spectroscopy (EDS) elemental mapping in Fig. 2c reveal that both the top and bottom of WSe₂ are encapsulated by Sb₂O₃. The Sb₂O₃ layer is pre-deposited as a buffer to mitigate the doping influence of the top HfO₂ gate dielectric²⁸. Additionally, Sb₂O₃ is deposited on the bottom gate to ensure both the top and bottom gates have similar dielectric environments, thereby ensuring the proper execution of logic functions.

Electronic characterization of 3D LCs

To demonstrate the low thermal budget and damage-free advantages of our M3D integration, we evaluated the transport characteristics of each LC layer. When BG and TG are operated in conjunction with the polarity gate, the LC exhibits reversible switching between P-type and N-type transistor modes. As shown in Fig. 2d, both the 1st-tier and 2nd-tier LCs exhibit excellent N-type transport with on/off ratios greater than 10⁶ under the polarity gates of 2 V. All curves are measured at a source-drain voltage of 1 V, unless otherwise specified. Figure 2e shows the P-type transport characteristics of each layer of the LCs at the polarity gates of −2 V. The on-state currents remain comparable between the two tiers, with variations within less than one order of magnitude for N-type operation and approximately one order of magnitude for P-type operation, confirming that the sequential integration process does not substantially degrade the electrical characteristics of the underlying LC layer. Notably, the on-state currents of the N-type and P-type transistors exhibit slight asymmetry. This asymmetry results from the formation of a Schottky barrier at the interface between the source electrode and WSe₂, where the electron and hole injection barriers have different heights. We also note that recent improvements in 2D FET performance, including enhanced P-type WSe₂ operation through NO doping^29,30, mainly arise from process-level optimizations such as contact engineering^31,32. These strategies are compatible with our LC architecture and could further improve its device performance.

We further measured the electrical performance of 36 devices in the middle of the monolithic area. The transport characteristics of 25 devices are presented in Supplementary Fig. 6, showing an overall positive shift in threshold voltage for the 2nd-tier LCs compared to the 1st-tier counterparts in both P-type and N-type transport. The 2nd-tier LCs also exhibit improved uniformity, highlighting the structural integrity and reproducibility of the low-temperature integration process. We further benchmarked the electrical performance of each tier by extracting the threshold voltage, on-state current, and on-off ratio, and comparing these metrics with those of planar LCs, as shown in Fig. 2f–h. The improved performance of the 2nd-tier device is likely related to the reduced number of subsequent fabrication steps. Additionally, the bottom-contact configuration of the device prevents damage from hot metal atoms during the metal evaporation, resulting in weaker Fermi pinning effects and lower Schottky barriers^33–35. These results indicate that the low-temperature integration process preserves the transport characteristics of both tiers and supports reversible polarity control in the stacked LC architecture. The present device yield is approximately 75%, suggesting that further improvements in contact engineering, transfer uniformity, and material quality will be important for scaling this platform toward larger arrays.

In addition, the operational stability of the LCs was evaluated through repeated input cycling, hysteresis characterization, and bias-stress measurements (Supplementary Fig. 7). With the polarity gates fixed at 2 V, the back and top gates were synchronously switched between −2 and +2 V using an alternating voltage-pulse sequence. The transfer characteristics remain stable after 500, 800, and 1300 switching cycles. Double-sweep transfer measurements show limited hysteresis, while positive and negative bias-stress tests up to 1000 s further confirm stable device operation under prolonged gate bias. These results indicate that the LCs maintain good operational stability under repeated input modulation and electrical stress.

Logic reconfiguration in LCs-based 3D circuit

Building on the demonstration of P/N-type transistors, we further explored logic functions enabled by LC-based gate-level integration. Figure 3a illustrates configurations of the 1st-tier LC for implementing various logic functions. Here, two gates (BG and MG) are used as logic input A and logic input B. Notably, by using the polarity gate as logic input C under specific configurations, the logic functionality can be extended to realize three-input logic gates. Under different gate-bias configurations, a single LC can implement multiple logic functions, including two-input AND, NOR, NIMP, and XNOR gates, as well as three-input AND and NOR gates. The corresponding current output results are shown in Supplementary Fig. 8.

Fig. 3. Reconfigurable logic functions of LCs.

a Schematic diagram of 1st-tier LC structure. b Output waveforms of various logic functions, including NAND, NOR, XOR, 3-input NAND, and 3-input OR. The polarity gates, PS and PD, serve as polarity control gates (P), where applied voltages of −2 and 2 V represent logic “0” and “1”, respectively. Logic states P-00, P-01, and P-11 correspond to different combinations of control signals (where the first and second digits represent the PD and PS gate configurations, respectively). c Transfer curves of LC under different middle gate biases at polarity gates of V_PS = V_PD = 2 V. The red and blue lines represent the current values for middle gate voltages of 2 and −2 V, respectively. d Voltage transfer characteristics of the LC-based complementary inverter. BG, TG and MG are electrically connected and used as the input. e The voltage gain of the inverter as a function of the input voltage. Inset: the power consumption of the LC-based inverter. f Comparison of the number of achievable logic functions and the corresponding transistor count in representative dual-gate, polarity-gate, floating-gate, and split-gate transistors.

To convert the current response into a voltage output, the WSe₂-based LC was connected in series with a resistor. In this configuration, the LC can be used as a driver transistor to perform logic inversion, and a voltage follower can be constructed by configuring the polarity gates. Figure 3b presents the output results of different reconfigurable logic functions. Due to the synergistic regulation strategy of the multi-gate, the two-layer LC successfully implements various logic functions. Supplementary Figs. 9 and 10 illustrate the logic functions of the planar and 2nd-tier LC under different voltage configurations.

To reveal the working mechanism of the LCs, we tested the transfer characteristics of the 1st-tier device under different gate voltage configurations. When BG is swept from −2 to +2 V under different MG biases, the LC in the N-type mode exhibits gate-dependent switching characteristics. As shown in Fig. 3c, when the PD and PS gates are set to 2 V and the top gate voltage is varied from 2 to −2 V, the on-state current of the device decreases from 3 × 10⁻⁶ A/μm to 1.4 × 10⁻¹³ A/μm, while the off-state current remains relatively unchanged, and the on-off ratio drops from 2.1 × 10⁷ to 1. This produces a high-current output only for the input state (1,1), whereas the (1,0), (0,1), and (0,0) states remain in the low-current regime, corresponding to NAND logic. When the PD and PS gates are at −2 V, the LC shows lower currents at high levels (1,0), (0,1), and (1,1), and has higher currents only at low levels (0,0), which corresponds to the OR gate.

Furthermore, we developed a TCAD model to gain more insights into the multi-gate structure. The simulated transfer characteristics agree well with the experimental results under different control-gate biases (Supplementary Fig. 11). The polarity gate significantly modulates the contact barrier, while the introduction of an asymmetric MG and BG gate structure plays a key role in achieving both switching characteristics. At positive (negative) voltages for both the MG and BG gates, the energy band of 2D WSe₂ moves down (up), and the potential barrier in the middle of the channel decreases (increases), corresponding to the on (off) state. Due to the incomplete coverage of the channel by the bottom gate field, the negative MG bias further depletes the uncovered region, causing the device to remain in the off state. In addition, when the bottom gate voltage is negative, a high electronic barrier remains in the middle of the channel even under a positive MG voltage, as the bottom gate exerts stronger electrostatic control than the middle gate, thereby keeping LC in the off state. Supplementary Figs. 12 and 13 show the transfer characteristic curves and the corresponding channel carrier distribution under different gate voltage configurations. Notably, the bottom and top gates provide asymmetric electrostatic control over the channel, which is essential for achieving valid logic operation. By contrast, symmetric gate regulation fails to produce the required input-dependent switching behavior, leading to invalid logic operation, as shown in Supplementary Fig. 14.

As mentioned earlier, our device process is similar to the CMOS process and achieves stable N-type and P-type transport characteristics. This indicates that the device also has the ability to construct complementary logic units such as inverters. Figure 3d shows the voltage transfer curves for LC with two layers of control gate shorting as inputs. As shown in Fig. 3e, the inverter achieves a peak gain of approximately 169 at V_DD = 2 V. Power consumption is calculated and plotted in the inset of Fig. 3e, where the static power consumption is determined to be 36 pW. This low power consumption can reasonably be attributed to the excellent off-performance in both p-type and n-type FET states. Among these, the LC-based complementary inverter shows clear voltage inversion with high gain^{14,22–25,27,36,37}. Based on the LC inverter, complementary LC-based logic gates and cascaded logic circuits were further demonstrated. By configuring the polarity gates of the pull-up and pull-down LCs, the same complementary circuit can be reconfigured between NAND and NOR operations (Supplementary Fig. 15). In addition, a two-stage cascaded LC circuit was constructed by directly connecting the output of the first LC logic stage to the input of the second stage. These results demonstrate that the LC architecture can support complementary logic implementation and inter-stage signal transfer.

Notably, the planar inverter shows rail-to-rail output, owing to its simpler processing (Supplementary Fig. 16). Compared to the single-gate configuration, the dual-gate inverter shows the shift voltage changed from −0.5 to 0.7 V, facilitating the construction of more complex circuits. This is because the dual-gate transistors exhibit enhanced electrostatic control, resulting in better performance than single-gate transistors, as shown in Supplementary Fig. 17. Together, the complementary logic and reconfigurable logic functions demonstrate that vertically stacked LCs can operate as interlayer logic-connection units, rather than merely as isolated reconfigurable transistors. This gate-level operation allows Boolean functions to be embedded within individual LCs and interconnected across tiers, instead of assigning each operation to a fixed CMOS transistor network. As a result, LC-based circuits can integrate more functional units within the same chip footprint, providing a key advantage for high-density integrated electronics. Compared with conventional CMOS implementations, the LC-based circuits reduce the transistor count by 83% for AND gates, 75% for NOR gates, and 90% for XOR gates, respectively.

Beyond this transistor-count comparison, we further evaluated the implementation overhead associated with LC-based circuits, as shown in Supplementary Table 1. This analysis shows that the advantage of LC-based implementation should not be understood as a universal reduction in every layout metric for all elementary gates. For simple logic gates, the additional control and bias-routing overhead can partially offset the benefit of reduced device count. However, as the implemented Boolean function becomes more complex, the multifunctional LC can embed part of the logic operation within fewer LCs, thereby reducing intermediate signal-transfer nodes, logic depth, and intra-circuit interconnection complexity. As shown in Supplementary Fig. 18, the layout-level comparison based on the RSSB logic function in a representative 2D-CMOS one-instruction-set computer shows that the LC-based implementation reduces the estimated layout footprint by approximately 22% compared with the planar CMOS implementation, after including the additional control, bias and routing requirements. These results indicate that the practical advantage of the LC architecture lies in gate-level functional compactness rather than simple transistor-count reduction.

More importantly, the LCs also advance the reconfigurability of 2D reconfigurable electronics. As summarized in Fig. 3f and Supplementary Table 2, this architecture not only maintains competitive device metrics but also expands a dual-gate logic element from a single operation to eight distinct logic functions^38–46. These results highlight LC-based M3D integration as a promising route towards compact and high-density reconfigurable logic circuits. Although multi-gate devices introduce additional control gates compared with single- or dual-gate transistors, recent 2D CMOS with backside power delivery provides a useful strategy for interconnect and power-routing optimization⁴⁷. By separating power delivery from front-side signal routing, backside power delivery can release front-side routing resources and help accommodate the more complex control and signal-routing networks required by multi-gate LC architectures. For future large-scale LC-based 3D circuits, deterministic state addressing and configuration management could be implemented in an FPGA manner by separating configuration routing from logic-signal routing. Rather than independently controlling every LC in real time, the configuration terminals of LCs could be connected to predefined shared configuration buses or bias rails, while peripheral selection circuits choose the required bus combination to define the logic function of each LC group before operation. Once configured, these lines remain static, and logic signals propagate through the circuit as in conventional logic operation. This shared-bus configuration scheme reduces routing redundancy and provides a practical route toward scalable LC-based 3D circuits.

Scalable function of LC-based 3D circuits

To demonstrate the advantages of gate-level integration at the circuit level, we constructed two-tier 3D circuits comprising serially connected LCs and resistors. The polarity gates of each tier (P1 and P2) are configured independently to realize distinct logic functions. Figure 4a shows the circuit schematic of a parity checker and half-adder. When the 1st- and 2nd-tier polarity gates are set to P1-00 (where the first and second digits represent the PD and PS gate configurations, respectively) and P2-01, the two tiers of LC are configured as an OR gate and an XOR gate, corresponding to the check and zero bits, respectively. Figure 4b shows the output waveforms of the corresponding parity checker, which are consistent with the truth table shown in Fig. 4c. The LC-based 3D circuit can achieve the half-adder when programmed to P1-01 and P2-11. The corresponding output waveforms and truth table are shown in Fig. 4d, e. These results establish vertically stacked LCs as reconfigurable circuit primitives that can be programmed into distinct complex functions. More importantly, they experimentally verify that interlayer circuit construction can be performed by connecting logic-function units, rather than by only interconnecting individual transistors across tiers. Compared with previously reported 3D integration approaches^{14,22,24,27,36,37,48}, the gate-level integration architecture offers a superior strategy for achieving an unprecedented circuit scale, as shown in Fig. 4f. A summary of the reported works is provided in Supplementary Table 3. Here, the circuit scale is quantified by the number of transistors required for implementation.

Fig. 4. Scalable functions of LC-based gate-level 3D circuits.

a Schematic illustrations of 3D circuits implementing a half-adder and a parity-checker under distinct voltage configurations. The 1st tier provides the carry for the half-adder and the zero for the parity-checker, whereas the 2nd tier provides the sum for the half-adder and the checker output for the parity-checker. b The output waveform of the parity-checker. c The truth table of the parity-checker. d, e The output waveform and truth table of a half-adder. f Comparison of circuit scale between the LC architecture and previously reported 3D integrated devices. g Comparison of circuit area across different logic functions implemented using various architectures.

The functional compactness of the LC-based architecture is further evaluated by comparing the number of active units required to implement the demonstrated logic functions. The LC-based 3D circuits realize parity-check and half-adder functions with 75% and 71.4% fewer transistors than the CMOS circuits, which require more than 16 and 14 transistors (Supplementary Fig. 19). Across the demonstrated functions, spanning elementary logic gates and complex logic operations, conventional CMOS implementations require more than 79 transistors, whereas the LC-based architecture achieves the same functionality using only four devices (Table 1), highlighting its substantial advantage in circuit footprint and functional density. As benchmarked in Fig. 4g, the LC-based architecture provides the most compact implementations of logic functions, including NAND, OR, XOR, half-adder and parity-check, compared with planar transistors, CFETs, and previously reported reconfigurable transistors.

Table 1.

Comparison of device counts in CMOS and LC-based circuits

Logic function	Number of devices
	CMOS circuits	LCs-based circuits
INV	2	2
BUF	4
NAND	4
OR	6
RNIMP	8
XOR	11
3-NAND	6
3-OR	8
Half-adder	14	4
Parity-check	16

In addition to area scaling, the reduced transistor count is expected to lower the power overhead associated with signal transmission. The LC-based 3D circuit consumes only 6.44 nW of static power per cycle during half-addition operation (Supplementary Fig. 20). Details of the power consumption are provided in the Supplementary Table 4. To provide a more complete circuit-level evaluation, we also extracted the energy-delay product (EDP) for different logic functions by considering both the on current and the estimated capacitive switching cost (Supplementary Fig. 21). The dynamic performance of the LCs is further evaluated. The switching behavior of the LC was investigated using square-wave input signals with a voltage swing of 2 V over a frequency range from 10 Hz to 1 kHz, as shown in Supplementary Fig. 22. Moreover, by optimizing load networks, further reductions in delay can be achieved, highlighting the scalability of this approach toward larger and more complex systems (Supplementary Fig. 23). In addition, the device maintained stable logic operation under different load conditions after load-network optimization (Supplementary Fig. 24). These results provide a more realistic assessment of the output-driving behavior of the LC logic gate under fan-out-like capacitive loading.

In conclusion, we demonstrate gate-level monolithic 3D integration based on 2D WSe₂ LCs. Unlike conventional transistor-level integration, in which Boolean functions are constructed by interconnecting networks of individual transistors, the LC architecture achieves multiple logic functions through multi-gate control. Using this strategy, we experimentally realize two-tier 3D circuits in which only four LCs implement a set of functions corresponding to 79 transistors in conventional silicon implementations. These results establish a gate-level integration approach that improves functional compactness and logic density by shifting the basic interlayer connection unit from individual transistors to logic-function units, thereby moving 3D integration from transistor stacking toward logic-function stacking.

Methods

2D WSe₂ material growth

WSe₂ single crystals were synthesized using a typical physical vapor deposition method. Precisely weighed 3.0 g of WSe₂ powder (purity ≥ 99.8%, Sigma-Aldrich) was evenly distributed in a quartz boat and placed at the center of the heating zone in a tube furnace. High-purity argon was continuously introduced. The furnace temperature was first ramped to 400 °C at a rate of 10 °C min⁻¹ and held for 20 min. Simultaneously, silicon substrates with a 300 nm thermal oxide layer were pre-cleaned via sequential sonication in acetone and ethanol (10 min each) and dried with nitrogen. The cleaned substrates were positioned downstream in the tube (15 cm away from the center of the heating zone). Following this, the temperature was further increased at a rate of 5 °C min⁻¹ to 1100 °C. After holding at the target temperature for 3–5 min, the system was allowed to cool naturally to room temperature. High-quality WSe₂ single-crystal films were obtained.

Device fabrication

To fabricate LC, Ti/Au/Ti (1 nm/5 nm/1 nm) patterned bottom electrodes were first prepared on a silicon substrate with 300 nm SiO₂ using e-beam lithography (EBL, FEI Quanta 3D). HfO₂ was deposited using commercial atomic layer deposition (Ke-micro, T-ALD) with H₂O and Tetrakis-(dimethylamino)-hafnium (TDMAHf) as precursors. Sb₂O₃ was deposited under high vacuum (10⁻⁸ torr) using a thermal evaporation deposition system (KYKY Technology). Maskless lithography (MicroWriter ML®3) and ICP (SENTECH SI 500) etching were used to remove the HfO₂ and Sb₂O₃. 2D WSe₂ was then precisely transferred onto the patterned gate/dielectric stack and patterned to define the channel region. Source and drain electrodes consisting of 30-nm-thick Au were fabricated by EBL followed by thermal evaporation. A 5 nm Sb₂O₃ buffer layer was then deposited, followed by deposition of a 15-nm-thick HfO₂ top-gate dielectric. The 30-nm-thick Au middle-gate electrodes were subsequently fabricated, completing the 1st-tier device architecture. To construct the 2nd-tier LC, 15 nm HfO₂ and 5 nm Sb₂O₃ were sequentially deposited over the middle-gate region. The 2nd-tier source and drain electrodes were then prepared, followed by transfer and patterning of the WSe₂ channel. The Sb₂O₃ buffer layer and the HfO₂ dielectric layer were sequentially deposited. The 2nd-tier top-gate electrodes were then formed, completing the vertically stacked LC architecture. Finally, via patterns were defined by maskless laser direct writing, and the vias and pad electrodes were formed by sequential thermal evaporation.

The characterization of the material and device

The Raman and PL spectra characterizations of 2D WSe₂ were performed by confocal microscopy (Horiba, JY-HR800) under a 532 nm laser at room temperature and in the ambient atmosphere. Cross sections of as-prepared devices were made using a focused ion beam tool (Thermo Scientific Scios2) cut at 30 kV, and STEM characterizations were carried out on a Grand ARM200 microscope at 200 kV. All electrical measurements of the devices were performed using a semi-automated Cascade M150 probe station at room temperature and atmospheric pressure, with an Agilent B1500A Semiconductor Parameter Analyzer.

TCAD simulations

All the device simulations were performed in Silvaco, a computer-aided design software based on a series of well-established physical models and their equations. Three-layer WSe₂ was used as channel material with a band gap of 1.4 eV, an electron affinity energy of 3.76 eV, a permittivity constant of 6, and a surface carrier concentration of 4 × 10¹² cm⁻².

Author contributions

Z.H., X.Z., Z.Z., and Y.Z. conceived the idea and designed the experiments. H.Z. constructed the devices and analyzed the data. X.W. and Y.G. were involved in the TCAD simulations and discussed the results. J.S. and K.C. provided strong support in device manufacturing and electrical measurements. H.Z. and Z.C. performed the STM and STEM characterization. K.C., Yanzhe Zhang, and S.J. provided suggestions related to the experiments. Z.H., X.W., X.Z., Z.Z., and Y.Z. participated in the manuscript revision. All authors contributed to and commented on the analysis and discussion of the results.

Peer review

Peer review information

Nature Communications thanks Saptarshi Das, Dong Li, and other anonymous reviewers for their contribution to the peer review of this work. A peer review file is available.

Funding

This work was supported by the National Natural Science Foundation of China (Grant Nos. 52188101, 52225206, 62322402, 52350301, 92463308, 62304019, 62504018), National Key Research and Development Program of China (Grant No. 2022YFA1203803), Fundamental and Interdisciplinary Disciplines Breakthrough Plan of the Ministry of Education of China (Grant No. JYB2025XDXM411), Beijing Natural Science Foundation (Grant No. JQ26010), Fundamental Research Funds for the Central Universities (Grant No. FRF-TP-22-004C2, FRF-TP-24-04C, FRF-06500207, FRF-IDRY-25-023), Postdoctoral Science Foundation (BX20250290).

Data availability

The data generated in this study are provided in the Supplementary Information/Source Data file. Source data are provided with this paper.

Competing interests

The authors declare no competing interests.

Supplementary information

The online version contains supplementary material available at https://doi.org/10.1038/s41467-026-77530-z.