A Universal van der Waals Tunneling Injector for Monolayer CMOS

ABSTRACT

Two‐dimensional (2D) semiconductors are poised to extend logic technology to the atomic‐thickness limit, yet monolayer complementary metal‐oxide‐semiconductor (CMOS) has been largely hampered by polarity‐dependent, thermionic‐emission‐dominated contacts that preclude a unified injection solution. Here, we introduce degenerately doped, crystalline SnSe₂ as a universal source‐side van der Waals (vdW) injector capable of enforcing all‐tunneling carrier injection into both p‐ and n‐type monolayer channels. The combination of a large electron affinity (∼5.1 eV), degenerate carrier density (>10¹⁹ cm⁻³), and atomically uniform vdW interfacial coupling enables polarity‐tailored tunneling mechanisms while effectively suppressing interfacial gap states. In p‐type WSe₂, a type‐III (broken gap) alignment drives efficient band‐to‐band tunneling, yielding a >1000‐fold enhancement in drive current over conventional metal electrodes. In n‐type MoS₂, the SnSe₂ injector forms a type‐I heterojunction within the sub‐depletion‐width monolayer body, enabling a gate‐tunable injection that evolves from field‐controlled Fowler–Nordheim‐like tunneling to thickness‐limited tunneling, achieving an on/off ratio > 10⁹ and a subthreshold swing below 70 mV dec⁻¹. Integrating this single‐material injector, we demonstrate a monolayer CMOS inverter with a maximum voltage gain of ∼340 at V _DD = 2 V, establishing degenerate SnSe₂ as a dual‐polarity vdW injector and providing a platform for high‐performance, low‐power 2D integrated circuits.

A universal van der Waals injector unlocks polarity‐flexible tunneling contacts for monolayer CMOS. SnSe₂, an intrinsically degenerate 2D semiconductor, establishes polarity‐specific band alignments with both WSe₂ and MoS₂ channels, enabling steep switching, high on/off ratios, and a unified route to low‐power 2D logic.

1. Introduction

Two‐dimensional (2D) materials have undergone a remarkable transformation, from exotic model systems explored in academic curiosity to implementation‐ready building blocks for post‐silicon electronics [1, 2, 3, 4]. Their atomically thin bodies offer intrinsic immunity to the short‐channel effects and mobility degradation that severely limit extremely scaled silicon transistors, positioning them as natural successors at the ultimate device scaling limit. Among the broad family of 2D semiconductors, transition metal dichalcogenides (TMDs), most notably MoS₂ and WSe₂ as prototypical n‐ and p‐type monolayer channels, have emerged as leading candidates for 2D complementary logic [5, 6, 7, 8, 9]. Rapid progress in wafer‐scale synthesis, dielectric integration, and device fabrication has brought these materials technologically closer to very large‐scale integration [10, 11, 12]. Yet as the field advances from proof‐of‐concept demonstrations toward circuit‐level functionality, a critical and increasingly recognized bottleneck has come into sharp focus: the metal/semiconductor interface. Inefficient charge injection at this interface throttles on‐state currents, inflates subthreshold swings, and masks the intrinsic electronic advantages that make 2D materials inherently appealing [13].

In common monolayer transistors, carrier injection is typically governed by non‐ideal Schottky barrier (SB) at direct metal/TMD interfaces, which is degraded by three intertwined issues. First, the energetic deposition of metal atoms readily damages the fragile 2D lattice, creates point defects, and potentially triggers localized interfacial reactions [8]. The resulting structural disorder not only increases series resistance but also generates defect‐induced gap states (DIGS) that act as scattering centers and trap charges at the interface. Second, electronic hybridization induces metal‐induced gap states (MIGS), pinning the Fermi level and limiting electrostatic control of the injection barrier [14]. Recent studies on semimetal contacts demonstrate that MIGS formation is exquisitely sensitive to interfacial wavefunction overlap: even small changes in interlayer distance at van der Waals (vdW) semimetal/TMD interfaces produce pronounced shifts in SB height and polarity selectivity [15]. This sensitivity reveals a fundamental dilemma: achieving low‐resistance contacts for one carrier polarity tends to compromise injection for the other, making a truly universal band‐alignment scheme for monolayer complementary metal‐oxide‐semiconductor (CMOS) elusive. Third, morphological and chemical inhomogeneity, arising from interface roughness, grain boundaries, and spatially varying local bonding configurations, imposes a landscape of fluctuating SB heights across the contact area. Under high bias, current then percolates preferentially through locally lowered barriers, causing contact‐limited transport with poor reproducibility and non‐optimal subthreshold swing.

In order to address these carrier injection limitations, a variety of process‐ and material‐oriented approaches have been explored, including low‐damage metallization [8, 16], phase‐engineered metallic TMDs [17], substitutional or surface‐charge transfer doping [18, 19], and vdW semimetal electrodes [14, 20]. However, they typically demand channel‐ and polarity‐specific optimization, add process complexity, and still fall short of delivering simultaneously high‐performance p‐ and n‐type contacts in a monolayer CMOS platform [6, 21]. More critically, when a single injector is applied to both polarities, the inherently asymmetric carrier transfer characteristics at the injector/channel interfaces result in unbalanced electron and hole injection efficiencies, which severely complicates inverter operation. An appealing alternative is to deliberately move away from thermionic emission and engineer tunneling‐dominant injection at vdW heterojunctions, in which a degenerately doped 2D injector supplies a large carrier reservoir with a well‐defined band edge while the vdW gap suppresses interfacial reactions and MIGS. Yet, a universal, polarity‐flexible charge injection concept where a single vdW tunneling injector can efficiently supply both electrons and holes to monolayer channels via mechanism‐appropriate pathways is still lacking for process‐compatible 2D CMOS technology.

Here, we propose a unified, tunneling‐centric injection solution: SnSe₂ [22, 23], a degenerate post‐transition metal dichalcogenide, as a universal source‐side vdW injector (Figure 1a). SnSe₂ forms atomically smooth vdW interfaces with monolayer channels of both polarities. Its large electron affinity and high intrinsic carrier density guarantee robust conductivity and efficient charge supply [24, 25, 26], while its finite bandgap and vdW‐bonded interface limit wavefunction hybridization and suppress MIGS formation. Building on these interfacial attributes, we develop a universal tunneling framework in which a single SnSe₂ injector enables polarity‐flexible charge injection through two distinct mechanisms. In p‐type monolayers such as WSe₂, SnSe₂ establishes a type‐III broken‐gap alignment that drives efficient band‐to‐band tunneling (BTBT). In n‐type channels such as MoS₂, it forms a type‐I junction where injection is governed by barrier‐shape‐dependent thermally assisted tunneling, spanning a field‐controlled Fowler–Nordheim tunneling (FNT)‐like regime to a thickness‐limited tunneling regime when the tunneling distance is constrained by the monolayer thickness. This versatility, rooted in the intrinsic band lineup and degeneracy of SnSe₂, offers a route toward low‐power monolayer CMOS technology beyond thermionic, Schottky‐dominated contacts.

FIGURE 1.

Crystalline SnSe₂ as a carrier‐type‐independent vdW injector with high conductivity and uniform interfacial properties. (a) The weakly degenerate, near‐band‐edge n‐type SnSe₂ injector (center) has a high electron affinity (EA ≈ 5.1 eV, defined from E _Vac to the conduction‐band edge), with E _C ≈ E _F. On the WSe₂ side (left), the SnSe₂ conduction band can overlap with the WSe₂ valence‐band edge under gate bias, enabling interband electron tunneling from occupied SnSe₂ conduction‐band states into empty WSe₂ valence‐band states, represented by n(E) and p(E). On the MoS₂ side (right), the SnSe₂ conduction band lies below the MoS₂ conduction band at equilibrium, forming an electron‐injection barrier; gate‐induced band bending thins this barrier and enables electron tunneling into the n‐type channel, represented by n(E). (b) Temperature‐dependent Hall measurements of carrier concentration (n) and mobility (µ), indicating degenerate n‐type characteristics and immunity to carrier freeze‐out. Inset: OM image of the Hall‐bar device (scale bar: 10 µm). (c) HR‐TEM image of a CVD‐grown SnSe₂ (scale bar: 5 nm), showing a well‐ordered lattice with an interplanar spacing of 0.33 nm corresponding to the $(10\overline{1}0)$ and $(01\overline{1}0)$ planes. The inset presents the SAED pattern. (d) Cross sectional HAADF‐STEM image of the SnSe₂ injector in contact with the monolayer MoS₂ channel. The magnified image clearly shows an atomically abrupt vdW interface, with an interfacial separation of approximately 2.15 Å (scale bars: 2 nm). (e) Vertical HAADF‐STEM intensity profile taken from the marked region in (d), further confirming the sharp SnSe₂/MoS₂ interface and the extracted interfacial spacing. (f) KPFM mapping of the surface potential for a monolayer MoS₂ contacted by evaporated metal (left) and vdW stacked SnSe₂ (right) (scale bars: 500 nm). (g) Histograms of CPD reveal a broad and inhomogeneous distribution for evaporated metal contacts, whereas vdW SnSe₂ contacts exhibit a narrow and uniform CPD distribution, indicating a homogeneous Schottky barrier height (${\varphi }_{\mathrm{B}}$).

2. Results and Discussion

2.1. Crystalline SnSe₂ as a Carrier‐Type‐Independent vdW Injector

In compound semiconductors, unintentional carriers often arise from intrinsic point defects that form dopant‐like energy levels within the bandgap and drive the Fermi level toward a stabilization energy, producing a native background carrier population even without intentional doping [27]. A similar mechanism accounts for the intrinsically high electron concentration observed in SnSe₂ with its deep‐lying conduction band minimum (CBM). Hall measurements (Figures 1b and S1; Table S1) reveal an electron concentration exceeding 10¹⁹ cm⁻³ and an electron mobility greater than 15 cm² V⁻¹ s⁻¹ at room temperature. The electron concentration remains above 10¹⁹ cm⁻³ even down to 10 K, confirming the absence of carrier freeze‐out. The weak temperature dependence of the carrier density over the measured temperature range therefore confirms the weakly degenerate, quasi‐metallic character of SnSe₂, satisfying the requirement for a highly conductive injection layer. Here, “weakly degenerate” denotes a near‐band‐edge condition in which E _F lies within a few k _BT of E _C, a regime where the Boltzmann approximation becomes quantitatively inaccurate [28, 29, 30, 31]. The temperature‐dependent mobility is likewise consistent with this assignment; the Hall mobility exhibits a broad maximum near 150 K, indicating a crossover from low‐temperature disorder‐ or boundary‐limited transport to high‐temperature phonon‐limited transport, while the carrier density remains high without exhibiting freeze‐out (Figure S2). Importantly, this high carrier density prevents electrostatic depletion under gate modulation (Figure S3), analogous to heavily doped source/drain regions in silicon CMOS that ensure a robust carrier reservoir [32]. This resistance to electrostatic carrier depletion, together with ohmic‐like linear conduction to metal contacts, is preserved in SnSe₂ layers even thinner than 10 nm (Figure S4). The ohmic‐like coupling between degenerate SnSe₂ and metal electrodes was further validated across nine transfer length method (TLM) devices fabricated via a large‐area array‐scale process, yielding a contact resistance of 0.264 ± 0.086 kΩ·µm with Ni (Figure S5). Consistent behavior was observed in a CVD‐grown SnSe₂ flake contacted with Ti (work function ∼4.33 eV [33]), which similarly exhibited near‐ohmic I–V characteristics and a comparable contact resistance of ∼0.257 kΩ·µm (Figure S6). In this sense, SnSe₂ functions as an ideal vdW‐coupled buffer, bridging the atomically thin channel and the external metal leads while shielding the fragile 2D channel from deposition‐induced damage and interfacial reactions [34].

SnSe₂ was synthesized via low‐temperature vapor‐phase growth routes, including chemical vapor deposition (CVD) at ∼270 °C and metal–organic chemical vapor deposition (MOCVD) [22] at ∼200 °C, underscoring its suitability for low‐thermal‐budget, process‐compatible integration (Figure S7). These mild growth temperatures are enabled by precursor engineering, specifically the pre‐cracking of organic molecular precursors in the MOCVD process and the use of readily decomposable SnBr₂ precursors in the CVD route, allowing precise morphology control from single‐crystalline flakes to scalable thin films. The optical microscopy (OM) image in Figure S8 shows hexagonal SnSe₂ flakes with uniform lateral geometry, while the high‐resolution transmission electron microscopy (HR‐TEM) image in Figure 1c reveals atomically ordered lattice fringes with an interplanar spacing of ∼0.33 nm, consistent with the $(10\overline{1}0)$ and $(01\overline{1}0)$ planes. The corresponding selected area electron diffraction (SAED) pattern further evidences the single‐crystalline nature of the flakes. The scanning electron microscopy energy‐dispersive x‐ray spectroscopy (SEM‐EDS) mapping (Figure S9) yields an atomic ratio close to the expected stoichiometric composition and the Raman spectrum (Figure S10) shows sharp, well‐resolved vibrational modes characteristic of SnSe₂.

Cross‐sectional high‐angle annular dark‐field scanning transmission electron microscopy (HAADF‐STEM) images in Figure 1d,e reveal a uniform, atomically abrupt interface between the monolayer channel and the vdW SnSe₂ injector, with an interlayer separation of approximately 2.15 Å. The monolayer channel remains structurally intact, with no sign of interfacial damage or amorphization. TEM‐EDS elemental mapping from the same region (Figure S11) further confirms spatially well‐defined distributions of Sn, Se, Mo, and S, with no discernible intermixing across the injector/channel junction. Together, these results demonstrate that vdW integration yields a clean, abrupt SnSe₂/monolayer‐channel interface while preserving the structural integrity of the atomically thin semiconductor.

To assess the interfacial uniformity of SnSe₂ as a carrier‐type‐independent vdW injector, we benchmarked it against a conventional evaporated Ni electrode with a nearly identical work function (Φ _SnSe2: ∼5.18 eV, Φ _Ni: ∼5.15 eV [33, 35]) (Figure 1f). Kelvin probe force microscopy (KPFM) mapping, calibrated with a tip work function of 4.9 eV, shows that Ni/2D‐channel contacts yield an average contact potential difference (CPD) of 132 meV with a large standard deviation (σ = 13 meV), reflecting substantial spatial fluctuations in local electrostatic potential. In contrast, vdW SnSe₂ injectors interfaced with the 2D channel exhibit a larger CPD (217 meV) with an order‐of‐magnitude smaller variation (σ = 2 meV) (Figure 1g). Using the relation V _CPD = (Φ _Surface−Φ _Tip)/e where Φ _Surface is the work function of the sample surface [36], Φ _Tip is the KPFM tip work function, and e is the elementary charge, the corresponding surface work functions are extracted to be 5.03 eV for Ni and 5.12 eV for SnSe₂. These values closely match reported and calculated work functions, validating the reliability of CPD‐based analysis [36, 37]. The broad CPD distribution at Ni contacts originates from deposition‐induced damage, morphological roughness, and non‐uniform chemical bonding, while the vdW junction between crystalline SnSe₂ and the monolayer preserves an atomically smooth and electrostatically homogeneous potential landscape [34, 38]. As a layered semiconductor, SnSe₂ possesses a large electron affinity and a correspondingly high work function, which remain nearly invariant from the few‐layer regime to the bulk (Figure S12). This distinctive electronic property underpins the favorable band alignment required for carrier‐type‐independent tunneling injection, as discussed in the following subsection.

2.2. Dual‐Polarity Carrier Injection via Band‐Engineered SnSe₂ Interfaces

To clarify how crystalline SnSe₂ enables carrier‐type‐independent injection, we first examine its band alignment with monolayer WSe₂ and MoS₂, using the calculated band structure of SnSe₂ and the vacuum‐level‐aligned band offsets in the corresponding heterostructures. As shown in Figures 2a and S13 for the p‐type case (WSe₂), density functional theory (DFT) indicates that bulk SnSe₂ possesses deep‐lying band edges, with its CBM and valence band maximum (VBM) located at −5.25 eV and −6.26 eV relative to vacuum, respectively. The VBM of WSe₂ thus lies slightly above the SnSe₂ CBM around −5.24 eV, while the SnSe₂ valence band sits substantially deeper, producing a type‐III (broken‐gap) configuration. In the broken‐gap WSe₂/SnSe₂ heterostructure, current is governed by electron tunneling across the valence‐to‐conduction band overlap.

FIGURE 2.

Distinct carrier injection pathways enabled by crystalline SnSe₂ for both p‐type and n‐type monolayer channels. (a) DFT‐calculated band structures and vacuum‐level‐aligned band alignment of bulk SnSe₂ with monolayer WSe₂. (b) Calculated DOS after contact formation between a 3L‐SnSe₂ and a WSe₂ monolayer, alongside the schematic band diagram, highlighting BTBT injection mechanism at the SnSe₂/WSe₂ interface. (c) Transfer characteristics of monolayer WSe₂ channels contacted with SnSe₂ versus Ni, showing more than a 1000× enhancement in I _on. The devices were fabricated on a 300 nm SiO₂/p ⁺⁺ Si back‐gate configuration, with comparison devices prepared on the same sample. (d) DFT‐calculated band structures and vacuum‐level‐aligned band alignment of bulk SnSe₂ and monolayer MoS₂. (e) DOS after contact formation between a 3L‐SnSe₂ and a monolayer MoS₂, and schematic band diagrams illustrating the bias‐dependent injection barrier geometry at the SnSe₂/MoS₂ interface. The barrier evolves from a triangular FNT‐like profile at lower gate bias to a thickness‐limited tunneling profile under stronger accumulation, with both TFE and FE carrier injection components coexisting in each regime. (f) Transfer characteristics of monolayer MoS₂ channels contacted with SnSe₂ versus Ni, demonstrating a S.S reduction by more than fivefold. The devices were fabricated on a 300 nm SiO₂/p ⁺⁺ Si back‐gate configuration, with comparison devices prepared on the same sample.

As shown in Figure 2b, the density of states (DOS) analyses of the 3L‐SnSe₂/WSe₂ heterostructure show a complete closure of the interfacial band gap, confirming that the interface forms a clean type‐III broken‐gap alignment that naturally supports efficient BTBT from SnSe₂ into WSe₂ under hole‐accumulating bias [26, 39]. These conclusions are further corroborated by element‐ and layer‐projected band structure and DOS calculations (Figures S14–S16). Any interfacial or gap states formed at the SnSe₂ interface are energetically positioned below the Fermi level due to its degenerate n‐type character, and therefore remain fully occupied. As a result, these states do not induce Fermi‐level pinning nor generate additional transport barriers for carrier injection across the junction.

Consistent with this picture, monolayer WSe₂ p‐type FETs employing SnSe₂ as the source‐side injector exhibit more than three orders of magnitude higher on‐current (I _ON) than control devices with evaporated Ni electrodes, despite their similar work functions. To enable a direct comparison, both device types were fabricated on monolayer WSe₂ flakes located on the same 300‐nm SiO₂ global back‐gated substrate (Figures 2c and S17a). The >1000‐fold enhancement in I _ON is defined based on the maximum current achievable within the operable voltage range under same structure of gate stack configuration. The large performance gap between SnSe₂‐ and Ni‐contacted devices indicates that carrier injection across the vdW SnSe₂/WSe₂ interface is dominated by efficient interband tunneling rather than thermionic emission over a SB. This tunneling‐dominated injection picture is further corroborated by the temperature‐dependent transport analysis in Figure S18. In a conventional Schottky‐barrier‐limited contact, Arrhenius analysis is expected to yield a positive activation energy associated with thermionic emission over the effective barrier. In contrast, the SnSe₂‐injected monolayer WSe₂ transistor exhibits negative apparent activation energies across the relevant gate‐bias range, indicating that carrier transport is not governed by thermally activated carrier emission over a Schottky barrier. This behavior is instead consistent with field‐driven interband tunneling across the vdW SnSe₂/WSe₂ junction. The symmetric SnSe₂/monolayer WSe₂/SnSe₂ device exhibits clear p‐type transfer characteristics for both polarities of V _DS, as shown in Figure S19. Because BTBT injection is controlled primarily by gate‐field modulation of the tunneling barrier, observed current is largely insensitive to drain‐bias polarity. This polarity‐independent p‐type behavior confirms that carrier injection is governed by the field‐modulated SnSe₂/WSe₂ vdW tunneling junction, rather than by a unidirectional rectifying contact.

As for n‐type monolayer MoS₂, the identical SnSe₂ injector behaves as a high‐work‐function contact and forms a Schottky‐type junction. DFT calculations show an asymmetric straddling type‐I band alignment where the CBM of SnSe₂ (−5.25 eV) lies considerably deeper than that of MoS₂ (−4.19 eV) while its VBM (−6.26 eV) is positioned slightly above the MoS₂ VBM (−6.32 eV) (Figures 2d and S13). This offset naturally establishes a SB and scanning photocurrent microscopy (SPCM) measurements further reveal barrier‐limited photoresponse localized at the SnSe₂/MoS₂ contact edge (Figure S20). Notably, the ultrathin channel allows electrons to efficiently traverse the sizeable energy barrier through field‐induced tunneling, as illustrated in Figure 2e. Because the dominant barrier is set by the intrinsic band offsets rather than process‐induced nonideality, the SnSe₂/MoS₂ interface approaches an ideal Schottky‐tunneling contact. The resulting gate‐tunable Schottky barrier gives rise to a barrier‐shape‐dependent crossover from a field‐controlled FNT‐like to a thickness‐limited thermally assisted tunneling regime, as discussed in Section 2.3. Here, FNT‐like and thickness‐limited tunneling refer to the field‐dependent barrier geometry and effective tunneling distance, whereas thermionic‐field‐emission (TFE) and field‐emission (FE) denote the dominant carrier‐energy range and thermal occupation within the same tunneling process [40]. Temperature‐dependent measurements on an SnSe₂‐injected monolayer MoS₂ device further support this tunneling‐assisted injection picture (Figure S21). The extracted activation energy decreases nonlinearly with increasing gate‐induced electric field, indicating that the gate primarily modulates the tunneling width of the Schottky barrier rather than simply lowering a thermionic barrier height. This behavior is consistent with TFE and FE transport. Although weak near‐band‐edge states appear near the conduction band edges of both materials (Figure 2e and Note SI), they reside within the band‐edge region rather than deep in the gap and fall within the primary tunneling window of the sub‐1‐nm barrier, so they behave as ordinary band‐edge states rather than as in‐gap traps and exert only a limited influence on the overall injection process (Figures S22 and S23).

Within this band‐alignment framework, monolayer MoS₂ FETs contacted with SnSe₂ show a more than fivefold reduction in subthreshold swing (S.S) compared with Ni‐contacted controls (Figures 2f and S17b), reflecting a pronounced suppression of contact‐limited transport and a steep switching mechanism governed by tunneling probability.

Injection‐interface‐limited conduction is primarily dictated by the source‐side contact. To isolate the role of the injector within a common channel, we further fabricated asymmetric devices in which SnSe₂ and Ni electrodes are placed at opposite ends of identical WSe₂ or MoS₂ flakes, and the measurement configuration selectively designates either electrode as the grounded source (Figure S24). In both monolayer and few‐layer WSe₂, when SnSe₂ is grounded acting as the source‐side injector, the transfer curves consistently show higher current and a lower apparent injection barrier than when Ni provides the injection. Similarly, in monolayer MoS₂, the SnSe₂‐grounded configuration yields a noticeably steeper S.S compared with the Ni‐grounded case. Because the grounded electrode defines the injection interface, these measurements directly attribute the improved drive current in p‐FETs and the steeper S.S in n‐FETs to the SnSe₂ vdW injector. Both channel polarities benefit from the ideal band alignment offered by SnSe₂, which consistently promotes tunneling‐assisted carrier injection. As a result, deficient drive current in p‐FETs is substantially boosted, while n‐FETs achieve markedly steeper subthreshold switching. This dual‐polarity improvement positions SnSe₂ as a single‐material vdW injector capable of delivering efficient and uniform carrier supply across both transistor types.

2.3. Field‐Induced Tunneling in Sub‐Depletion‐Width Channels

Conventional Schottky junction models, originally formulated for a semi‐infinite semiconductor, are inadequate to describe carrier injection across the SnSe₂/n‐type monolayer channel junction. In particular, they assume a thick semiconductor body in which the built‐in field is fully screened within a depletion region adjacent to the contact, leaving the potential flat in the neutral bulk region. Once the channel thickness approaches or falls below the depletion width, this assumption breaks down: the electric field penetrates the entire body, and so carrier injection is governed by finite‐thickness electrostatics and field‐induced tunneling in an atomically thin channel.

To capture this regime, we analyze the dependence of carrier injection on channel thickness and electrostatic gating. In bulk‐like MoS₂ channels, where the semiconductor thickness t _S exceeds the depletion width regime (W _D), the depletion region is confined near the interface and the built‐in field is fully screened, such that the potential at the back surface relaxes to zero (ψ(W _D) ≈ 0) (Figure 3a). Under this condition, the electrostatics can be described by the standard one‐dimensional Poisson equation for a uniformly depleted Schottky junction:

$$\frac{d^2\psi }{d{x}^2}=-\frac{q{N}_{\mathrm{D}}}{{\epsilon }_{\mathrm{s}}}$$ (1)

where q is the elementary charge, N _D is the donor concentration, and ε_s is the semiconductor permittivity. The constant right‐hand side (−qN _D/ε_s) corresponds to the uniform space charge of ionized donors that generates the familiar parabolic bending of the electrostatic potential. When the channel thickness is reduced below W _D, the entire body becomes depleted and the usual boundary condition ψ(W _D) = 0 can no longer be satisfied. Instead, the potential profile follows a modified solution that explicitly incorporates the finite thickness:

$$\psi (x)=-\frac{q{N}_{\mathrm{D}}}{2{\epsilon }_{\mathrm{s}}}{(x-t_{\mathrm{s}})}^2+\psi (t_{\mathrm{s}})$$ (2)

where t _s is the channel thickness and ψ(t _s) denotes a residual back‐surface potential in the fully depleted thin‐body regime. In such a case, the barrier is no longer localized near the interface but extends across the full thickness of the channel, and large residual potential amplifies the electric field across the junction, transforming the injection barrier into a sharp triangular profile that is inherently favorable for tunneling (Figure 3b). Carriers therefore traverse the minimum‐action path through the 2D barrier landscape defined by the combined vertical and lateral field components [41]. COMSOL simulations further confirm this behavior and explicitly visualize the triangular tunneling barrier induced by the residual potential along the x‐direction (Figure S25). Importantly, this residual potential should not be interpreted as an uncompensated field extending indefinitely into the channel. In practice, the source‐side electrostatic perturbation induces compensating mobile charge near the channel interface, which screens the field and establishes electrostatic equilibrium within the junction.

FIGURE 3.

Field‐induced tunneling in the sub‐depletion‐width n‐channel. (a) Band diagram of a bulk Schottky junction, where the W _D fully screens the built‐in field, leaving no residual potential at the back interface. (b) Band diagram of a sub‐depletion‐width junction (t _S < W _D), showing strong band bending that creates a tunneling‐favorable barrier profile. (c) Band diagram of the energy barrier along the lowest‐resistance path (path 1 and path 2), which dominates carrier injection across the junction. (d) Reverse‐bias I–V comparison between monolayer (0.7 nm) and bulk (61 nm) MoS₂ with a SnSe₂ injector. The monolayer device exhibits a nearly linear voltage dependence, consistent with a thickness‐limited thermally assisted tunneling response, whereas the bulk channel shows suppressed tunneling. (e) Gate‐dependent FN‐type tunneling analysis of the monolayer MoS₂ device, plotted as ln(I _DS/V _DS ²) versus 1/V _DS at different gate biases. In the subthreshold region (V _GS = −40 and −20 V), the barrier adopts a triangular profile, giving rise to an FNT‐like, field‐controlled thermally assisted tunneling response. As the gate field increases (V _GS ≥ 0 V), the effective barrier width becomes extremely thin, leading to a crossover toward a thickness‐limited tunneling response. At sufficiently high gate bias (e.g., V _GS = 60 V), the device enters an ohmic regime exhibiting a linear current response across the entire V _DS range. (f) FN‐type analysis of the output characteristics measured at V _GS = 0 V, plotted as ln(I _DS/V _DS ²) versus 1/V _DS at different temperatures. As temperature decreases, the TFE contribution diminishes and the response moves toward the FE regime, in which a triangular‐approximable potential barrier near the Fermi level is revealed. The upper inset shows a qualitative schematic of the barrier profile in this state, and the lower inset shows a qualitative schematic of the TE–TFE–FE regime distribution as a function of temperature (T) and effective local electric field (E _eff).

In this regime, transport is governed by a composite pathway: (i) vertical tunneling across the SnSe₂/MoS₂ interface (Path 1 along the x‐direction) followed by (ii) lateral drift (Path 2), as illustrated in Figure 3c. This composite trajectory effectively defines the injection process and highlights that the rate‐limiting step is vertical tunneling through the barrier, rather than thermionic emission over a static Schottky height. To verify this, we experimentally analyzed thickness‐dependent rectification in asymmetric SnSe₂/MoS₂/Bi devices (Figure S26). One side of the device forms an ohmic‐like Bi contact [14], while the opposite side retains a SB at the SnSe₂/MoS₂ interface. As a result, the rectification behavior is strongly thickness‐dependent, so thick channels (e.g., 61 nm) show diode‐like I–V characteristics consistent with thermionic emission, whereas monolayer channels (∼0.7 nm) exhibit substantially enhanced reverse current, evidencing tunneling transport. The rectification ratio I _F/I _R at ±2 V decreases systematically from ∼6 in the thick channel to below 2 in the monolayer device (the inset of Figure S26a), corresponding to a roughly threefold reduction and highlighting the growing contribution of tunneling as the channel becomes thinner.

A direct comparison of reverse‐bias characteristics between monolayer and bulk (61 nm) MoS₂ diodes further corroborates the tunneling origin of injection (Figure 3d). The monolayer device exhibits a nearly linear I–V dependence consistent with a thickness‐limited tunneling response under finite‐temperature carrier injection (Figure S27), which can be represented by the phenomenological WKB limiting form:

$$I_{\mathrm{thickness}-\mathrm{limited}}\propto V\exp \left(-\frac{4\pi d\sqrt{2m^{\ast }{\varphi }_{\mathrm{B}}}}{h}\right)$$ (3)

where V is the applied voltage, d is the barrier thickness, m* is the effective mass, ${\varphi }_{\mathrm{B}}$ is the SB height, and h is Planck's constant [42]. Under the thickness‐limited approximation, integrating the Wentzel–Kramers–Brillouin (WKB) transmission with the energy distribution of electrons up to the barrier yields a simplified tunneling current whose bias dependence is linear in V, while being exponentially suppressed by the barrier thickness and height as $\exp (-4\pi d\sqrt{2m^{\ast }{\varphi }_{\mathrm{B}}}/h)$. In this thickness‐limited regime, the barrier thickness is essentially set by the atomic thickness of the channel and remains nearly unchanged over the relevant drain‐bias range. Accordingly, the drain bias primarily widens the available transport window, whereas the WKB transmission varies only weakly relative to that in a depletion‐controlled thick‐channel barrier. These expressions are not intended to assign ideal Fermi‐level direct tunneling emission as exclusive microscopic mechanisms; rather, they describe how the effective tunneling probability evolves from a thickness‐limited barrier, whose transmission is essentially insensitive to drain bias.

Deviations from the near‐linear I–V behavior at very small reverse biases (V ≲ 0.5 V) are attributed to a crossover region in which a residual thermally activated component and field‐assisted tunneling may coexist.

As a conventional order‐of‐magnitude reference for the thermally activated contribution, we estimate the reverse saturation current density using the Richardson form, $J_s=A^{\ast }{T}^2\exp (-q{\varphi }_B/k_{B}T)$, where A* is the effective Richardson constant [43]. Using A* =  80.3 A cm⁻² K⁻², ${\varphi }_B$ ≈ 0.8 eV, and T  =  300 K gives J _s ≈ 10⁻⁷ A cm⁻². This value is used only as a conventional reference estimate for the magnitude of the purely over‐barrier thermionic contribution. Residual field‐assisted tunneling can therefore still contribute within this low‐bias crossover region. For the measurement conditions of Figure 3d, reverse biases of approximately 0.5 V and higher evolve into the thickness‐limited tunneling regime described above.

By contrast, the larger thickness of the bulk MoS₂ channel permits the formation of an extended, depletion‐controlled barrier, suppressing direct tunneling and producing a more fully developed rectifying response. The governing electrostatic length scale in a reverse‐biased junction is the depletion width. To rationalize the rectifying behavior observed in the 27‐nm (Figure S26) and 61‐nm (Figure 3d) MoS₂ devices, we estimated the characteristic depletion width in the MoS₂ channel as:

$$W_{\mathrm{dep},\max }\simeq {\left(\frac{2{\epsilon }_{\mathrm{Mo}{\mathrm{S}}_2}\mathrm{\Delta }{\varphi }_{\mathrm{eff}}}{q{N}_{\mathrm{eff}}}\right)}^{\frac{1}{2}}$$ (4)

Using $\mathrm{\Delta }{\varphi }_{\mathrm{eff}}$ ≈ 0.8 V [36], ε _r ≈ 6.2 [44], and N _eff ≈ 1×10¹⁸ cm⁻³ [45], we obtain W _{dep, max} ≈ 23.4 nm, comparable to the 27‐nm channel thickness and well accommodated within the 61‐nm channel. This estimate is consistent with the emergent rectifying behavior in the 27‐nm device and the more fully developed rectification in the 61‐nm device. Under forward bias, barrier lowering and narrowing enable carrier injection, producing the observed rectification.

Gate‐dependent measurements reveal a clear crossover between FNT‐like and thickness‐limited tunneling regimes in the sub‐depletion‐width channel (Figure 3e). In the subthreshold region (V _GS = −40 and −20 V), the gate bias holds the channel in full depletion so that the injection barrier retains a triangular profile; under this gate‐defined triangular barrier, the reverse drain bias modulates the barrier steepness and thus the effective tunneling distance, producing an FNT‐like, field‐controlled thermally assisted tunneling response. This regime can be phenomenologically described by an FNT‐like WKB limiting expression:

$$I_{\mathrm{FN}-\mathrm{like}}\propto V^2\exp \left(-\frac{4d\sqrt{2m^{\ast }{\varphi }_{\mathrm{B}}^3}}{3\hslash q\mathrm{V}}\right)$$ (5)

where ℏ is the reduced Planck's constant. For this FNT‐like regime, the slope of the ln(I/V ²) versus 1/V plot is given by $S_{\mathrm{FNT}}=-4d\sqrt{2m^{\ast }{\varphi }_B^3}/3\hslash q$. Using d = 0.7 nm, m* = 0.5m ₀ [46], and ${\varphi }_B$ = 0.8 eV, we obtain a theoretical slope S _FNT ≈ −2.4. Experimentally, a slope with a smaller magnitude of approximately −1.7 is observed. This deviation suggests that the actual tunneling process is governed by an effective, spatially nonuniform barrier rather than an ideal, uniform Schottky barrier. In particular, the underlying gate dielectric can introduce local electrostatic disorder, such as trapped charges or interfacial potential fluctuations [36], which locally reduces the effective barrier height and creates preferential low‐barrier tunneling pathways. Consequently, the experimentally extracted slope can be smaller in magnitude than the ideal WKB estimate derived from a uniform nominal barrier.

As the gate bias increases, the barrier width progressively contracts, driving the device first from the field‐controlled FNT‐like regime into a thickness‐limited thermally assisted tunneling regime [40, 41]. At still more positive gate biases, the extracted apparent activation energy becomes low and approximately constant across the entire measured drain‐bias range, consistent with a near‐ohmic injection regime (Figures S28 and S29).

To further clarify the role of thermal carrier occupation, we performed temperature‐dependent Fowler–Nordheim analysis at V _GS = 0 V (Figure 3f). TFE and FE represent different carrier‐occupation limits within the same energy‐resolved tunneling process through a field‐thinned Schottky barrier, rather than distinct tunneling mechanisms. In the TFE regime, thermally populated carriers tunnel through the upper, thinner portion of the barrier, whereas in the FE regime, carriers tunnel from states closer to the Fermi level with reduced thermal activation. As temperature increases, thermally populated carriers contribute to tunneling through a reduced effective barrier thickness, giving rise to TFE behavior. Upon cooling, the thermally assisted contribution is progressively suppressed and transport converges toward an FE‐dominated response. To verify that this assignment reflects the coupled effects of temperature, local field, and barrier parameters rather than the FN‐plot trend alone, we examined the FE/TFE applicability boundary from a dimensionless, image‐force‐corrected barrier model as a function of temperature and local field [44, 47], as schematically summarized in the lower‐right inset of Figure 3f: the low‐temperature, high‐local‐field corner falls in the FE region, while increasing temperature at comparable field shifts transport into the TFE region. This confirms that the FNT‐like/thickness‐limited terminology describes the barrier‐shape‐dependent tunneling geometry under finite‐temperature carrier injection, rather than the thermal occupation of carriers. To visualize the gate‐ and drain‐bias dependence of the temperature sensitivity of the total measured current without imposing a specific thermionic prefactor, Figure S29 maps the apparent activation energy extracted directly from linear fits of ln|I _D| versus 1/T. Its bias‐dependent evolution provides complementary support for the corresponding injection‐regime evolution. Overall, the progressive gate‐driven evolution from FNT‐like tunneling at V _GS = −40 V and −20 V, through a thickness‐limited tunneling regime with a finite thermally assisted contribution, toward near‐ohmic injection at more positive V _GS, supports field‐induced modulation of the injection barrier in sub‐depletion‐width channels.

This tunneling‐based model also explains the observed improvement in S.S. In conventional SB injection limited by thermionic emission, S.S is fundamentally constrained to the thermal limit of ∼60 mV dec⁻¹ at room temperature. In contrast, in the FNT‐like thermally assisted tunneling regime, the gate field reshapes the barrier and reduces the effective tunneling distance, causing the injection probability to vary more steeply than thermionic emission current. This field‐controlled barrier modulation accounts for the reduced S.S. Although any residual gap states along the vertical tunneling path (Path 1) cannot be entirely excluded, the channel thickness was optimized at the monolayer limit, where the finite‐thickness electrostatics predict the steepest gate‐induced modulation of the source‐injection barrier. The resulting strong field modulation minimizes the relative influence of such gap‐state‐mediated transport on the measured switching response, further supporting field‐modulated thermally assisted tunneling as the primary injection mechanism in the vdW SnSe₂/MoS₂ contacts.

2.4. Steep‐Slope, High‐On/Off‐Ratio Schottky‐Barrier Tunneling FETs Enabled by Field‐Induced Tunneling Injection

We integrated the field‐induced tunneling mechanism into a transistor scheme to demonstrate high‐performance low‐power switching. As shown in Figure 4a, we fabricated SB tunneling FETs (SB‐TFETs) incorporating a monolayer MoS₂ channel, an SnSe₂ source injector, and a high‐κ HfO₂ (8 nm) gate dielectric. In this architecture, the atomically thin channel operates in the sub‐depletion‐width regime, so the physical thickness of the SB is essentially fixed by monolayer itself. Consequently, the drain current is determined exclusively by the electrostatic band alignment at the vdW junction, rather than by geometrical scaling of the depletion region. Under gate modulation, the barrier profile evolves from a field‐controlled FNT‐like thermally assisted tunneling regime in the subthreshold region to a thickness‐limited tunneling regime at higher gate overdrive. This gate‐induced FNT‐like‐to‐thickness‐limited tunneling crossover in the effective tunneling barrier constitutes the central mechanism for steep, low‐power switching in the SB‐TFET.

FIGURE 4.

Low‐power operation characteristics of SB‐TFET. (a) Schematic illustration of the fabricated SB‐TFET structure with SnSe₂ source and MoS₂ channel. The inset shows an OM image of the device (scale bar: 5 µm). (b) Transfer characteristics of the SB‐TFET, exhibiting steep S.S_min (< 70 mV dec⁻¹) and gate‐controlled turn‐on behavior. (c) Output characteristics measured under various gate biases. (d) Transfer curves of seven identically fabricated devices, confirming reproducibility. (e) The corresponding S.S plot extracted from (d). The finite‐difference S.S values are assigned to the lower‐current point of each interval. (f) Benchmark comparison of on/off current ratio and minimum S.S with previously reported low‐power FET technologies with TMD channels. Devices in this work (red stars) are positioned near the desired operation corner (arrow sign), demonstrating competitive low‐power switching performance. The comparison metrics are shown as reported in the respective publications (DSFET [50], Fluoride gate [51], hBN dual gate [52], Semimetal contact [20], NCFET [53], NC‐TFET [54] and high‐κ dielectric [7, 55]).

The resulting SB‐TFETs exhibit a minimum S.S approaching the thermionic limit of 60 mV/dec, while maintaining an extremely low off‐current and competitive on‐current, consistent with FNT‐dominated injection through a gate‐controlled tunneling barrier (Figure 4b,c). Although HfO₂ gate stacks are often associated with relatively large S.S and pronounced charge trapping due to interface states [48, 49], our device demonstrates near‐ideal switching characteristics, underscoring the stabilizing role of the SnSe₂ injector in suppressing trap‐assisted leakage. The transfer characteristics show negligible hysteresis (<100 mV; Figure S30), indicating that the required on/off ratio can be achieved without sweeping the gate into trap‐activating regimes. At the same time, the sufficiently thinned barrier enabled by the sub‐depletion‐width monolayer channel supports a high on‐current, yielding an I _ON/I _OFF exceeding 10⁹ with steep switching characteristics. This performance is consistently reproduced across seven identically fabricated devices with minimal device‐to‐device variation (Figure 4d,e). More importantly, across the same device set, switching the grounding configuration so that Ni, rather than SnSe₂, served as the injection electrode led to a pronounced degradation in S.S (Figure S31). This deterioration directly confirms that the steep‐slope behavior originates from the SnSe₂‐enabled, field‐modulated tunneling injection pathway.

By reinforcing the mechanistic role of the SnSe₂ injector, these results demonstrate that the proposed SB‐TFET architecture effectively resolves the low‐power/high‐performance trade‐off and outperforms previously reported TMD‐based device platforms (Figure 4f). Beyond these device‐level characteristics, the SB‐TFET architecture further benefits from the intrinsic geometrical confinement of monolayer channels, which amplifies the sensitivity of the tunneling barrier to gate‐induced electrostatics. This strong gate leverage sharpens the barrier‐shape‐dependent crossover between the FNT‐like and thickness‐limited thermally assisted tunneling regimes, ensuring that the tunneling pathway governs switching before thermionic leakage becomes dominant. Furthermore, around the turn‐on regime, the gate leakage remains below the drain‐current level in the adjacent off‐state region (Figure S32), ensuring negligible static power consumption and reinforcing the suitability of this architecture for ultra‐low‐power operation. The simplicity of the vdW contact configuration, combined with the naturally minimized barrier width, thus establishes a practical route toward energy‐efficient switching in atomically thin semiconductors.

2.5. High‐Gain CMOS Inverter With 2D Monolayer Channels via the Carrier‐Type‐Independent vdW Injector

The SnSe₂ dual‐polarity tunneling injector, when integrated with a high‐κ gate stack, simultaneously enhances the transport characteristics of both monolayer p‐ and n‐type channels, enabling high‐gain CMOS inverter operation (Figure 5a). The SnSe₂‐mediated injection mechanism suppresses S.S and substantially boosts I _on, sharpening the voltage transfer characteristics. Critically, the near‐symmetric threshold voltages of the p‐ and n‐FETs, achieved without channel‐specific contact engineering, produce balanced switching behavior inherent to well‐matched CMOS design. As a result, the fabricated inverter exhibits an abrupt mid‐rail transition with a peak voltage gain of 340 at V _DD = 2 V (Figure 5b,c), surpassing previously reported monolayer CMOS inverters by a significant margin. The crossing of the p‐ and n‐FET transfer curves within the subthreshold regime (Figure S33) further confirms proper CMOS operation.

FIGURE 5.

CMOS inverter operation utilizing SnSe₂ as a carrier‐type‐independent injector. (a) Schematic illustration and OM image of a 2D CMOS inverter composed of monolayer p‐FET and monolayer n‐FET devices, each contacted with SnSe₂ as the carrier injector (scale bar: 10 µm). (b) Voltage transfer curve (VTC) of the inverter at various V _DD. (c) Voltage gain (−dV _OUT/dV _IN) profiles at different V _DD levels, extracted from the measured VTCs by finite‐difference differentiation using a V _IN sweep step of 0.005 V. The profiles show the peak gain behavior near the inverter switching region. (d) Peak switching power consumption (top) and noise margin (bottom) as a function of V _DD. The power was extracted as the maximum I _DD·V _DD in the VTC transition region. The normalized total noise margin, NM_total/V _DD, was calculated as [(V _OH −V _OL)−(V _IH−V _IL)]/V _DD, where V _OH and V _OL were taken as the measured maximum and minimum output voltages, respectively. V _IL and V _IH were determined by linearly interpolating the two unity‐gain crossings in the central‐finite‐difference gain profile and assigning each crossing to the nearest measured V _IN grid point. (e) Time‐domain switching characteristics of the SnSe₂‐injected monolayer CMOS inverter. A periodic square‐wave input signal (V _IN) switching between −1 and +1 V was applied, and the corresponding output voltage (V _OUT) was simultaneously recorded. V _OUT exhibits near rail‐to‐rail switching between 0 V and V _DD = 2 V in response to consecutive V _IN modulations. (f) Benchmark comparison of voltage gain versus V _DD among reported 2D CMOS inverters. The arrow indicates the desired performance direction. Comparison metrics were taken from reported values or extracted from the corresponding published plots when necessary (p‐MoTe₂/n‐MoS₂ [56], p‐WSe₂/n‐MoS₂ [57], p‐MoS₂/n‐MoS₂ [58], p‐MoTe₂/n‐MoTe₂ [59], and p‐WSe₂/n‐WSe₂ [60].

The inverter exhibits a wide noise margin and nW‐level peak switching power (Figure 5d), confirming that the SnSe₂‐injected monolayer CMOS inverter maintains clear logic‐level separation under low‐power operating conditions. Stable logic operation was further confirmed by repeated input switching measurements, in which V _OUT consistently followed the expected inverted response under consecutive V _IN modulation (Figure 5e). Reproducibility was verified across four independently fabricated devices sharing the identical SnSe₂ injector structure, all of which exhibited clear voltage transfer characteristics with comparable switching windows and peak voltage gains ranging from 174 to 340 (263.9 ± 76.3, n = 4) at V _DD = 2 V (Figures 5 and S34). Together, these results demonstrate reproducible high‐gain monolayer CMOS inverter operation with wide noise margins, stable logic switching, and low peak power consumption.

Comprehensive benchmarking against reported 2D‐channel CMOS inverters (Figure 5f and Table S2) places the present work in quantitative context among representative 2D CMOS technologies. Among the benchmarked TMD‐channel CMOS inverter reports, no prior demonstration explicitly integrates monolayer semiconductor channels for both p‐ and n‐type branches. This comparison underscores the practical difficulty of achieving complementary operation in a strictly monolayer‐channel platform where carrier injection must be effectively controlled for both polarities. Most previously reported approaches instead rely on polarity‐ or channel‐specific contact engineering to optimize p‐ and n‐type injection separately. In contrast, this work employs a single SnSe₂ vdW injector for both monolayer p‐ and n‐channel transistors. Combined with the steep switching characteristics, high on/off current ratios, and high voltage gain at low supply voltage, this unified injection strategy represents the central advance of the present monolayer CMOS platform.

Collectively, these results constitute a decisive demonstration of high‐gain monolayer CMOS logic enabled by a material‐level, carrier‐type‐independent carrier injection strategy. By unifying n‐FET and p‐FET injection physics through a single, scalable contact platform, SnSe₂ offers a promising route toward next‐generation 2D CMOS integration, circumventing the long‐standing challenge of dual‐contact optimization in heterogeneous 2D material systems.

3. Conclusion

We have demonstrated that crystalline SnSe₂ functions as a carrier‐type‐independent vdW injector for both p‐type and n‐type monolayer channels, providing a scalable route toward 2D CMOS logic. Its high electron affinity, degenerate carrier density, and atomically uniform interface enable tunneling‐dominant carrier injection across both polarities, while the clean vdW interface suppresses interfacial gap states that typically degrade contact performance.

By moving beyond conventional Schottky‐barrier‐based injection models, this work introduces a tunneling‐based injection framework tailored for sub‐depletion‐width monolayer channels. This approach eliminates the need for polarity‐specific electrodes, establishing a unified contact strategy applicable to both p‐FETs and n‐FETs within the exact same material platform.

Importantly, this single‐material injection scheme yields polarity‐specific performance advantages. Enhanced drive current is achieved in p‐FETs through efficient carrier tunneling, while n‐FETs exhibit a steeper S.S due to the improved electrostatic control enabled by tunneling‐mediated injection. Integration of these SnSe₂ injectors into monolayer transistors resulted in a CMOS inverter with high gain, conclusively demonstrating the feasibility of low‐power and high‐performance logic based entirely on bottom‐up synthesized 2D layers. Future progress in direct growth and lithography‐compatible patterning will be essential for wafer‐scale implementation, firmly positioning SnSe₂ as a practical and versatile platform for next‐generation 2D nanoelectronics.

4. Methods

4.1. Low‐Temperature CVD Growth of Morphology‐Tailored SnSe₂

SnSe₂ flakes and thin films were synthesized via a two‐zone CVD process (see schematic in Figure S7a). In the standard recipe, 50 mg of Se powder was placed in zone 1, while a mixture of 50 mg NaCl and 100 mg SnBr₂ in an alumina boat together with the target substrate was positioned in zone 2. Both zones were ramped to 270 °C over 20 min and maintained at this temperature under a pressure of 50 Torr, with an Ar carrier gas flow of 200 sccm and an additional H₂ flow of 20 sccm. The film morphology was tuned by varying the substrate type and growth process time. Vertically oriented SnSe₂ flakes were obtained on SiO₂ substrates, whereas lateral flake growth was achieved on mica substrates with a growth time of 15 min. For fully merged continuous films, growth was extended to 25 min on mica substrates. Based on this standard recipe, the tube conditions were slightly adjusted according to ambient humidity and reactor environment.

4.2. Low‐Temperature MOCVD Growth of Wafer‐Scale SnSe₂ Film

SnSe₂ films were grown in a custom‐built horizontal hot‐wall MOCVD system equipped with four independently controlled heating zones (see schematic in Figure S7c). The temperature of each heating zone was maintained at 650 °C (zone 1), 500 °C (zone 2), 400 °C (zone 3), and 200 °C (zone 4), respectively, where zone 1 served as the precursor decomposition zone and zone 4 as the growth zone. 2‐inch c‐plane sapphire wafers were used as growth substrates and positioned at the growth zone (200 °C). Tetramethyl tin (Sn(CH₃)₄, Sigma‐Aldrich) and dimethyl selenide (Se(CH₃)₂, Thermo Fisher Scientific) were used as Sn and Se precursors, respectively, with Ar as the carrier gas. The flow of each precursor was regulated by MFCs, and the Sn and Se precursors were introduced into the reaction chamber at optimized flow rates of 0.04 and 0.20 sccm, respectively. The film thickness could be controlled from 3 to 20 nm by regulating the growth time (4–6 h) and the Ar carrier gas flow rate from 200 to 350 sccm.. The process pressure was controlled at ∼7 Torr during the growth.

4.3. Material Properties Characterization

Raman spectroscopy (XperRAM S Series, Nanobase) with a 532 nm laser source was used to identify the intrinsic vibrational modes of the synthesized material. The same laser source, along with a mini‐chamber (MPS‐CHH, Nextron), was employed for SPCM measurements. To evaluate crystallinity at the atomic scale, HR‐TEM combined with TEM‐EDS analysis was performed at an accelerating voltage of 200 kV (JEM‐2100F, JEOL). The thickness of the synthesized 2D material flakes and fabricated device structures was characterized by atomic force microscopy (AFM; MFP‐3D Origin, Oxford Instruments; NX10, Park Systems). KPFM was carried out using a conductive cantilever (ASYELEC.01‐R2; resonance frequency 75 kHz, spring constant 2.8 N/m).

4.4. Structural Characterization

Crosssectional TEM specimens were prepared by Ga ion beam milling using an FEI system (Helios NanoLab 450, FEI). To minimize Ga ion‐beam‐induced surface damage, a final low‐voltage milling step was performed at 5 kV and 2 kV. HAADF‐STEM imaging was performed using a probe‐corrected TEM system (Spectra 300, Thermo Fisher Scientific) operated at 200 kV with a convergence semi‐angle of 30.0 mrad and a screen current of 39 pA. The collection semi‐angle for HAADF detector was set to 63–300 mrad. EDS elemental mapping was carried out using the same microscope equipped with a high‐solid‐angle Super‐X EDS detector system featuring four symmetrically integrated silicon drift detectors (SDDs). STEM‐EDS data were acquired in HAADF mode.

4.5. Hall‐Bar Device Fabrication and Measurements

A Hall‐bar device was fabricated by patterned SnSe₂ films using a maskless lithography system (MicroWriter, Durham Magneto Optics), followed by plasma dry etching with inductively coupled plasma‐reactive ion etching (FABStar, TTL) to define the device geometry. Electrodes were deposited using an electron‐beam evaporator (WC‐4000, Woosung Hi‐vac); Ni electrodes were first deposited, followed by additional Ti/Au pads to enable wire‐bonding for electrical measurements. The electrical transport measurements were carried out using a physical property measurement system (PPMS, Quantum Design), in which the chamber environment is maintained under helium atmosphere and a superconducting magnet is used to apply external magnetic fields. An AC current was supplied by a current source (Keithley 6221, Tektronix), while the Hall voltage was detected using lock‐in amplifiers (SR860, Stanford Research Systems).

4.6. First‐Principles Calculations

All DFT calculations were performed using the Vienna Ab initio Simulation Package (VASP) [61]. The projector‐augmented wave (PAW) pseudopotential was employed to describe electron–ion interactions [62], and the generalized gradient approximation (GGA) with the Perdew–Burke–Ernzerhof (PBE) exchange–correlation functional was applied for structural optimizations. Interlayer van der Waals interactions were included using the DFT‐D3 method with Becke–Johnson damping [63]. Since spin‐orbit coupling (SOC) effects in SnSe₂ are weak, raising only the VBM by no more than 0.04 eV, SOC was included only for monolayer MoS₂ and WSe₂. After confirming that the band alignment obtained with PBE is consistent with the Heyd–Scuseria–Ernzerhof hybrid functional [64] and SOC, we employed the PBE functional for the calculations of large heterostructure models. A vacuum spacing of at least 15 Å was introduced along the out‐of‐plane direction to avoid spurious interactions between periodic images.

4.7. Device Fabrication and Electrical Characterization

Monolayer WSe₂ synthesized by CVD and monolayer MoS₂ grown by metal–organic chemical vapor deposition (MOCVD) were used as channel materials. To fabricate the high‐κ metal gate structure, a photolithography mask aligner (MA6, Suss Microtec) was employed, followed by deposition of a ∼30 nm tungsten gate by DC sputtering (SRN‐120, SORONA). Subsequently, ∼8 nm HfO₂ was deposited as the gate dielectric by atomic layer deposition (Lucida D100, NCD). The monolayer channels were transferred using a polymer‐assisted wet‐transfer method, in which either polymethyl methacrylate (PMMA) or polystyrene (PS) support layers were employed depending on the sample. For the devices shown in Figures 2, 4, and 5, vertically oriented SnSe₂ flakes were positioned at the designated locations using a polydimethylsiloxane (PDMS)‐assisted aligned dry‐transfer technique. Electrode patterns were defined using either a maskless lithography system (MicroWriter, Durham Magneto Optics) or electron‐beam lithography (eLine Plus, RAITH), depending on the required pattern resolution. The electrodes, serving as probe‐contact pads and reference electrodes, were deposited by electron‐beam evaporation (WC‐4000, Woosung Hi‐vac and KVE‐E2000, Korea Vacuum Tech). Electrical characterization was performed under vacuum and dark conditions using a probe station (M5VC, MS Tech) and a semiconductor parameter analyzer equipped with preamplifiers (Keithley 4200A‐SCS, Tektronix). SPCM measurement was performed using a mini‐chamber (MPS‐CHH, Nextron) and a source measure unit (Keithley 2636B, Tektronix).

4.8. Statistical Analysis

For data normalization, the measured values were normalized using the minimum and maximum values of each corresponding dataset. Unless otherwise specified, the data were used as directly measured without additional transformation, correction, or outlier exclusion. Statistical data are presented as mean ± standard deviation, and the sample size is provided in the relevant figure captions or manuscript text. The statistical analyses in this work were descriptive, and no hypothesis testing or statistical significance testing was performed. Linear regression analyses were performed where applicable, and the corresponding coefficients of determination (R ²) are reported in the Supporting Information to assess the goodness of fit. All statistical analyses and data visualization were conducted using OriginPro (OriginLab Corporation) and MATLAB (MathWorks).

Conflicts of Interest

The authors declare no conflicts of interest.

Supporting information

Supporting file: adma74597‐sup‐0001‐SuppMat.pdf.

Data Availability Statement

The data that support the findings of this study are available from the corresponding author on reasonable request.