Polaronic transport and current blockades in epitaxial silicide nanowires and nanowire arrays

Abstract

Crystalline micrometer-long YSi₂ nanowires with cross sections as small as 1×0.5 nm₂ can be grown on the Si(001) surface. Their extreme aspect ratios make electron conduction within these nanowires almost ideally one-dimensional, while their compatibility with the silicon platform suggests application as metallic interconnect in Si-based nano-electronic devices. Here we combine bottom-up epitaxial wire synthesis in ultrahigh vacuum with top-down miniaturization of the electrical measurement probes to elucidate the electronic conduction mechanism of both individual wires and arrays of nanowires. Temperature-dependent transport through individual nanowires is indicative of thermally-assisted tunneling of small polarons between atomic-scale defect centers. In-depth analysis of complex wire networks emphasize significant electronic crosstalk between the nanowires, due to the long-range Coulomb fields associated with polaronic charge fluctuations. This work establishes a semi-quantitative correlation between the density and distributions of atomic-scale defects and resulting current-voltage characteristics of nanoscale network devices.

Quantum transport is at the heart of nanoscience and marries a fundamental law of nature, quantum mechanics, with applied electrical engineering and emerging materials technologies. Ultimately, nanoscale electronic devices will contain networks of wires whose cross sections will be so small as to represent one-dimensional conductors with novel transport properties. Among the many intriguing nanowire systems synthesized in recent years, epitaxial metal-silicide nanowires may be the most practical electrical interconnects because of their compatibility with the established silicon platform.^1–10 Here, we investigate the electrical properties of ultrathin epitaxial YSi₂ nanowires on Si(001) with a four-tip scanning tunneling microscope. Conduction through individual nanowires follows an inverse Arrhenius behavior indicative of thermally-assisted tunneling of small polarons between defect centers. Analysis of individual wire resistances, probe resistances, and negative differential resistances of nanowire networks indicates significant electronic interwire coupling below 150 K. The long-range coupling mechanism involves the dielectric polarization of the substrate, inducing current blockades in neighboring conduction channels. Establishing such semi-quantitative correlations between the density and distribution of atomic-scale defects and resulting current-voltage behavior is a critical first step towards designing novel nano architectures with desirable electrical properties.

The YSi₂ wires are formed by depositing about 0.5 monolayer (ML) yttrium on atomically- clean heated Si(100) substrates in ultrahigh vacuum (UHV). Their formation proceeds in two steps. First, 0.35 ML yttrium is incorporated into a Si(100)(2 × 7) surface reconstruction or template layer.¹¹ The remaining yttrium atoms subsequently self-assemble into epitaxial YSi₂ nanowires. The wires grow parallel to the atom rows of the template.^9,11,12 Figure 1a is a large-scale scanning tunneling microscopy (STM) image of a Si surface decorated with YSi₂ nanowires. Orthogonal wires represent different surface terraces, a consequence of the four-fold symmetry of the (100) substrate. Depending on the growth conditions and deposition amount, the wires are isolated or bundled.¹² The widths of individual nanowires are quantized in units of the Si(001) lattice constant (a₀ = 0.384 nm), the thinnest being only 3a₀ (1.15 nm) wide and about 1 µm long.⁹

Figure 1.

Scanning probe characterization of YSi² nanowires. (a) STM image showing numerous YSi² wire bundles on the Si(100) surface before patterning (scale bar: 450 nm). The tunneling parameters are −1.9 V and 0.08 nA. (b) Enlarged area of panel (a) showing two orthogonal bundles with segments of a second silicide layer (scale bar: 22 nm). (c) Cross-sectional structure of a wire bundle containing a 3a₀ and a 5a₀ nanowire, according to Ref. 12, with a₀ = 0.384 nm; silicon atoms are shown in yellow and yttrium atoms are shown in red. (d) Non-contact atomic force microscopy (AFM) image of a capped YSi₂ nanowire contacted by Pt leads and Pt contact pads (squares) (scale bar: 400 nm). (e) AFM image of the center area of the device presented in (d), showing the Pt leads and a YSi₂ nanowire bridging the leads (scale bar: 300 nm). (f) Scanning electron microscopy (SEM) image showing four STM tips in close proximity to the Pt pads (scale bar: 5 µm).

The bundles used for our transport studies are all 0.5 nm high. Many of them are decorated with segments of a second silicide layer that show up as bright segments in the STM images of Figure 1b. These bundles can grow several microns long. STM images show that the nanowires inside a bundle are mostly 3a₀, 4a₀ and 5a₀ wide, though wire widths of up to 9a₀ are occasionally observed. Figure 1c displays a cross-sectional structure of a bundle containing a 3a₀ and a 5a₀ nanowire. The strongly uni-directional growth and extreme aspect ratio of these wires are attributed to the perfect lattice match along the [112̄0] direction of YSi₂ and [11̄0] direction of the Si substrate, along with the absence of a close lattice match along the other crystal axes.⁹ A detailed study of the structure and growth was presented in Ref 12.

Electrical transport measurements on these tiny objects pose a formidable challenge, especially in light of the difficulty of establishing reliable probe contacts, and because the wires cannot be decoupled electronically from their surrounding. A four-tip STM apparatus with two outer current contacts and two inner voltage probes¹³ should in principle eliminate problems related to contact resistances for single nanowires and would furthermore seem ideal for imaging and positioning of the wire and contact probes, respectively, provided that the wires are clearly resolved during probe positioning. However, because of the extremely small dimensions and fragility of these ultrathin nanowires (0.5 nm high), mechanical contact to the STM tips unavoidably damages these wires. To circumvent this problem, we established electrical contact using a four-tip STM in conjunction with nano-lithography. First, we contacted the wires to ultrathin Pt leads, fabricated ex-situ by electron-beam-induced deposition (EBID) in a focused ion beam system (FIB; see Experimental section). To prevent oxidation, the samples were capped with an ultrathin amorphous Si layer prior to removal from UHV. Figure 1d and Figure 1e are AFM images of one of the devices. Here a YSi₂ wire-bundle is contacted by four thin Pt electrodes connecting the nanowires to four structurally robust Pt contact pads (squares). Next, we positioned the STM tips onto the contact pads (Figure 1f). The electrical characteristics of the wires were determined by measuring the voltage drop as a function of current for temperatures between 85 K and 300 K. In separate control measurements, we verified that the conductance through the substrate or (2 × 7) wetting layer is negligible in this temperature range (see Supporting Information for further details). In all, we have measured 12 devices in a 4-probe setup. The YSi₂ bundles in these studies are 7 to 14 nm wide, as measured with non-contact AFM (see Experimental section).

Scanning tunneling spectroscopy studies from uncapped wires suggest that the wire bundles are metallic, as they reveal a finite tunneling density of states at the Fermi level.^9,12 Figure 2a displays the transport I – V characteristics for a single bundle device (10 nm wide) for different temperatures, measured with the 4-tip STM. The I – V characteristics are indeed linear at 161 K and above but they are non-linear at 121 K and below. Figure 2b shows the zero-bias conductance as a function of temperature, plotted on a semi-logarithmic scale. The conductance drops over three decades when cooling from room temperature to 85 K.¹⁵ This temperature-dependence indicates that the conductance is thermally activated, in spite of the metallicity of uncapped wires.^9,12 Nonetheless, the inverse Arrhenius behavior of the wire conductance, i.e. ln σ ∝ T, is highly unusual.

Figure 2.

Transport properties of a YSi₂ wire-bundle. (a) I –V characteristics at various temperatures. (b) Temperature dependence of the zero-bias conductance of the YSi₂ bundle. (c) (I, T) data plotted for small voltages; solid lines are fits to the data using eq 1.¹⁴ (d) I/f(T) plotted against eV/kT for I_p = 0.36 ± 0.02 eV and ℏω = 0.057 ± 0.002 eV. The solid line is a fit to the data using eq 1; the fitting parameter, n, is 50.

So far, the exponential dependence of conductance on temperature has only been observed for disordered films^16,17 and for organic monolayers of eicosanoic acid (C20) sandwiched between Pt electrodes.¹⁸ The latter was theoretically explained in terms of small polaron hopping via defect centers.¹⁴ According to this theory, the current at high temperatures and small bias can be expressed as:

$$I(V,T)\approx V\text{exp}[\frac{-2I_p}{\hslash \omega }\text{tanh}\frac{\hslash \omega }{4kT}+\frac{\left|eV\right|}{2nkT}]$$ (1)

where I_p is the polaron shift, ω is (surface) phonon frequency, and n is the number of defects or impurities in the wire (see Supporting Information for further details). The first two parameters are determined by fitting the (I, T) data at different bias (Figure 2c) to be I_p = 0.36 ± 0.02 eV and ℏω = 0.057±0.002 eV. I(V, T) can then be scaled by plotting I(V, T)/f(T) against eV/kT where f(T) is the voltage independent part of the exponential function in eq (1). The scaled data nicely collapse when using I_p and ω values mentioned above (see Figure 2d). None of the other known transport models, including that of a Luttinger Liquid,¹⁹ produced satisfactory results. The small deviations from the fit that are seen for the 85 K data (Figure 2d) for eV/kT > 50 are attributed to the fact that eq 1 is valid in the limit of small voltage.¹⁴

The numbers above seem quite reasonable for the YSi₂ nanowires as the bonding configurations of the Si atoms in the wires resemble those at reconstructed Si(001) surfaces.⁹ For instance, the 57 meV phonon frequency is very close to the frequency of the backbond stretching mode of Si dimers on the Si(001)(2×1) surface.²⁰ The polaron shift represents the energy lowering of the defect levels resulting from the local bond deformation or restructuring upon electron capture. For Si surfaces, the polaron shift is indeed expected to be of the order of 0.4 eV.^21,22

A fit using eq 1 determines the number of defects or impurities to be 50 for a wire-bundle segment of 314 nm long, i.e., one defect per 6 nm on average. STM images of uncapped wires reveal a defect frequency distribution peaking at one defect per 5 nm per wire when both vacancy and adatom defects (i.e., extra adatoms) are taken into consideration. The close match between the two defect frequencies suggests that vacancy and adatom defects are responsible for the charge trapping.

Figure 3a presents an AFM image of the center part of a nanowire network device, where one easily distinguishes multiple YSi₂ nanowires in between the Pt electrodes. Figure 3c-e shows three I–V characteristics representative of such a device. To understand the strong S shapes (Figure 3c) and the ’negative resistances’ (Figure 3e) in these devices, we construct a simple resistor network to simulate the experimental wire network and derive a simple nonlinear I – V formula, eq 2, that fits the measurements (see Supporting Information for further details). Here, we assert that the transport through a nanowire is strongly influenced by the long-range Coulomb field in the substrate surface and/or capping layer, emanating from trapped charges at local defect sites.

Figure 3.

Characterization of YSi₂ wire network devices. (a) AFM image illustrating one example of a YSi₂ network device (wire 15) (scale bar: 370 nm). (b) Temperature dependence of the corrected zero bias resistance (see text) of two YSi₂ network devices, wire 14 (Supporting Information) and wire 15. The solid lines represent linear fits. (c), (d), (e) I – V characteristics of a network device (wire 15) at the indicated temperatures. The solid lines represent fits to the data using eq 2.

As an example, we consider two parallel wires, one with a low resistance and the other with a large resistance due to the presence of a strong scattering (defect) center in this wire. As the current increases, the high-resistance wire builds up a local charge that is proportional to the current. The Coulomb field from this charge build-up then creates a scattering potential in the neighboring low-resistance wire. For sufficiently strong coupling this will completely shut off transport in the low-resistance wire. We implemented this concept using two different circuit models and derived a simple nonlinear I – V formula (see Supporting Information for further details):

$$V=\frac{B-\left|I\right|}{C+\left|I\right|}{R}_{1}I,$$ (2)

Equation 2 was fitted to the experimental I – V curves in Figure 3c-e. The fitted ratio B/C is related to the resistances of other YSi₂ wire fragments and the Pt leads (measured separately; see Supporting Information). R₁ is the contact resistance of one of the voltage probes. We assert that eq 2 has a rather general validity for interacting nanowires where the coupling between the nanowires originates from the long-range Coulomb fields. The particular meanings of the fitting parameters R₁, B and C depends on the details of the circuit model. For data measured below 150 K, three parameters B, C, and R₁ suffice. But for data measured above 150 K only the slope of the I –V curve can be reliably determined, which gives us (B/C)R₁. Following this rationale we can express the corrected nanowire resistance as,

$$R_{\text{WIRE}}\approx 2\frac{B}{C}{R}_1+R_C.$$ (3)

where RC is an effective contact resistance and is estimated from the resistance of the Pt leads. The corrected wire resistance for two devices is plotted in Figure 3b at different temperatures.

The change from nonlinear I –V (or negative resistances) to linear I –V above 150 K reflects the changing interwire coupling constant λ, which vanishes above 150 K. Below 150 K, interwire coupling arises from the dielectric polarization of the substrate (or capping layer) by the charge fluctuations in the wires. The dielectric polarization, in turn, enhances the polaron activation energy (see Supporting Information for further details). This mechanism makes two predictions: 1. There should be two distinct temperature dependences above and below the critical temperature (150 K), corresponding to the polaron activation energies of a single wire and coupled wires, respectively; 2. At the critical temperature the polaron hopping frequency is approximately the transverse optical phonon mode frequency. The first prediction is confirmed by the temperature dependence of the wire resistance in Figure 3b, revealing two distinct slopes. The second prediction can be verified by the relationship between the measured resistance and the polaron hopping frequency in the Supporting Information. At the critical temperature (T_c ≈ 150 K), the measured resistance is R(T_c) ≈ 20 MΩ (for wire 14). From the fitted single wire data we know that the optical phonon energy is approximately ℏω_TO ≈ 0.057 eV. Based on density functional theory calculations, the impurity density of states D_imp ≈ 1 eV₋₁ (see Supporting Information for further details). From these values we find,

$$n\approx \frac{e^{2}R(T_c)D_{\text{imp}}{\omega }_{TO}}{2\pi }\approx 43.$$ (4)

This is in good agreement with the fitted value of n = 50 for single wires.

The combination of EBID nano-lithography and four-probe STM is shown to be capable of measuring the transport properties of ultrathin epitaxial nanowires while eliminating contact resistances and minimizing bulk conduction. No doubt, the electrical characteristics of nanowires approaching the one-dimensional limit will always be heavily influenced by atomic-scale charge trapping defects, and the resulting polarization of the surroundings as shown here for the YSi₂ wires. This poses severe constraints on the materials quality and circuit designs of future nanoarchitectures. For fundamental studies, it will be highly beneficial to grow both nanowires and nanowire contacts in-situ (UHV), which would allow one to cherry pick wires with certain cross-sectional dimensions and defect configurations. Such studies should be feasible and would pave the way for major achievements in nanoscale electrical engineering.

Experimental

The YSi₂ wires were grown in a UHV system with a base pressure of 1 × 10⁻¹⁰ mbar. A sub-monolayer amount of yttrium was deposited by electron-beam evaporation onto an atomically clean Si(001)(2 × 1) substrate held at 625 ± 25°C. STM imaging was carried out with a single-tip Omicron variable temperature VT-STM at room temperature. The wires were protected against oxidation by a thin layer of amorphous silicon prior to air exposure. Pt contacts were deposited using electron-beam induced deposition (EBID) of trimethyl(methylcyclopentadienyl)platinum(IV) on a Helios NanoLab 600 DualBeam focused ion beam (FIB) system (FEI Company). An accelerating voltage and beam current of 10 kV and 21 pA, respectively, were used for the deposition. The Pt contacts have cross-sections of 20 × 20 nm² and required less than one second each to deposit. Thin contacts and short deposition times were used in order to prevent electron beam-induced damage to the YSi² nanowires and to minimize the deposition of platinum peripheral to the patterned regions, which could result in leakage currents.²³ The (400 × 400 nm²) contact pads were 50 nm thick, i.e. sufficiently thick to withstand potential damage from STM tip contacting. Contact resistances proved to be highly reproducible. For the measurement of electrical transport properties, four STM probes were positioned on the contact pads, guided by SEM.¹³ Once the probes are close enough to the contact pads, the probes can be placed just a few nm above the contact pads using a controlled tunneling feedback mechanism (typically 4 V, 50 pA at 1 nA/V gain) so as to avoid unwanted crash. After the feedback current is stabilized, the probes are positioned on the contact pads. The outer two probes (Figure 1d) serve as the current contacts and the two inner probes (Figure 1d) detect the voltage drop due to the finite resistance of the nanowires. I –V curves were obtained as a function of sample temperature using a UHV cryostat with built-in counter heater. The temperature was measured with a calibrated silicon diode (Lakeshore, DT-670-SD-4D) and is accurate to within 50 mK. Ex-situ AFM images of the measurement devices were obtained after the transport measurements were completed. The widths of the wire-bundles are extracted from full width at half maximum (FWHM) of the AFM line profiles, after deconvolution following the method described by Villarrubia.²⁴ The tip profiles used for the deconvolution were determined by AFM imaging of an ultrasharp silicon grating sample. Note that the capping layer dilation was not accounted for; we believe the actual widths are slightly smaller than those reported here. The STM and AFM images were analyzed using the WSxM software.²⁵